mv_ddr_topology.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include "ddr_ml_wrapper.h"
  6. #include "mv_ddr_plat.h"
  7. #include "mv_ddr_topology.h"
  8. #include "mv_ddr_common.h"
  9. #include "mv_ddr_spd.h"
  10. #include "ddr_topology_def.h"
  11. #include "ddr3_training_ip_db.h"
  12. #include "ddr3_training_ip.h"
  13. #include "mv_ddr_training_db.h"
  14. unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk)
  15. {
  16. unsigned int cl = ceil_div(taa_min, tclk);
  17. return mv_ddr_spd_supported_cl_get(cl);
  18. }
  19. unsigned int mv_ddr_cwl_calc(unsigned int tclk)
  20. {
  21. unsigned int cwl;
  22. if (tclk >= 1250)
  23. cwl = 9;
  24. else if (tclk >= 1071)
  25. cwl = 10;
  26. else if (tclk >= 938)
  27. cwl = 11;
  28. else if (tclk >= 833)
  29. cwl = 12;
  30. else if (tclk >= 750)
  31. cwl = 14;
  32. else if (tclk >= 625)
  33. cwl = 16;
  34. else
  35. cwl = 0;
  36. return cwl;
  37. }
  38. int mv_ddr_topology_map_update(void)
  39. {
  40. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  41. struct if_params *iface_params = &(tm->interface_params[0]);
  42. unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
  43. enum mv_ddr_speed_bin speed_bin_index;
  44. enum mv_ddr_freq freq = MV_DDR_FREQ_LAST;
  45. unsigned int tclk;
  46. unsigned char val = 0;
  47. int i;
  48. if (iface_params->memory_freq == MV_DDR_FREQ_SAR)
  49. iface_params->memory_freq = mv_ddr_init_freq_get();
  50. if (tm->cfg_src == MV_DDR_CFG_SPD) {
  51. /* check dram device type */
  52. val = mv_ddr_spd_dev_type_get(&tm->spd_data);
  53. if (val != MV_DDR_SPD_DEV_TYPE_DDR4) {
  54. printf("mv_ddr: unsupported dram device type found\n");
  55. return -1;
  56. }
  57. /* update topology map with timing data */
  58. if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) {
  59. printf("mv_ddr: negative timing data found\n");
  60. return -1;
  61. }
  62. /* update device width in topology map */
  63. iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
  64. /* update die capacity in topology map */
  65. iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
  66. /* update bus bit mask in topology map */
  67. tm->bus_act_mask = mv_ddr_bus_bit_mask_get();
  68. /* update cs bit mask in topology map */
  69. val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data);
  70. for (i = 0; i < octets_per_if_num; i++)
  71. iface_params->as_bus_params[i].cs_bitmask = val;
  72. /* check dram module type */
  73. val = mv_ddr_spd_module_type_get(&tm->spd_data);
  74. switch (val) {
  75. case MV_DDR_SPD_MODULE_TYPE_UDIMM:
  76. case MV_DDR_SPD_MODULE_TYPE_SO_DIMM:
  77. case MV_DDR_SPD_MODULE_TYPE_MINI_UDIMM:
  78. case MV_DDR_SPD_MODULE_TYPE_72BIT_SO_UDIMM:
  79. case MV_DDR_SPD_MODULE_TYPE_16BIT_SO_DIMM:
  80. case MV_DDR_SPD_MODULE_TYPE_32BIT_SO_DIMM:
  81. break;
  82. default:
  83. printf("mv_ddr: unsupported dram module type found\n");
  84. return -1;
  85. }
  86. /* update mirror bit mask in topology map */
  87. val = mv_ddr_spd_mem_mirror_get(&tm->spd_data);
  88. for (i = 0; i < octets_per_if_num; i++)
  89. iface_params->as_bus_params[i].mirror_enable_bitmask = val << 1;
  90. tclk = 1000000 / mv_ddr_freq_get(iface_params->memory_freq);
  91. /* update cas write latency (cwl) */
  92. val = mv_ddr_cwl_calc(tclk);
  93. if (val == 0) {
  94. printf("mv_ddr: unsupported cas write latency value found\n");
  95. return -1;
  96. }
  97. iface_params->cas_wl = val;
  98. /* update cas latency (cl) */
  99. mv_ddr_spd_supported_cls_calc(&tm->spd_data);
  100. val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
  101. if (val == 0) {
  102. printf("mv_ddr: unsupported cas latency value found\n");
  103. return -1;
  104. }
  105. iface_params->cas_l = val;
  106. } else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) {
  107. /* set cas and cas-write latencies per speed bin, if they unset */
  108. speed_bin_index = iface_params->speed_bin_index;
  109. freq = iface_params->memory_freq;
  110. if (iface_params->cas_l == 0)
  111. iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
  112. if (iface_params->cas_wl == 0)
  113. iface_params->cas_wl = mv_ddr_cwl_val_get(speed_bin_index, freq);
  114. }
  115. return 0;
  116. }
  117. unsigned short mv_ddr_bus_bit_mask_get(void)
  118. {
  119. unsigned short pri_and_ext_bus_width = 0x0;
  120. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  121. unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
  122. if (tm->cfg_src == MV_DDR_CFG_SPD) {
  123. enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
  124. enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
  125. switch (pri_bus_width) {
  126. case MV_DDR_PRI_BUS_WIDTH_16:
  127. pri_and_ext_bus_width = BUS_MASK_16BIT;
  128. break;
  129. case MV_DDR_PRI_BUS_WIDTH_32:
  130. pri_and_ext_bus_width = BUS_MASK_32BIT;
  131. break;
  132. case MV_DDR_PRI_BUS_WIDTH_64:
  133. pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK;
  134. break;
  135. default:
  136. pri_and_ext_bus_width = 0x0;
  137. }
  138. if (bus_width_ext == MV_DDR_BUS_WIDTH_EXT_8)
  139. pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1);
  140. }
  141. return pri_and_ext_bus_width;
  142. }
  143. unsigned int mv_ddr_if_bus_width_get(void)
  144. {
  145. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  146. unsigned int bus_width;
  147. switch (tm->bus_act_mask) {
  148. case BUS_MASK_16BIT:
  149. case BUS_MASK_16BIT_ECC:
  150. case BUS_MASK_16BIT_ECC_PUP3:
  151. bus_width = 16;
  152. break;
  153. case BUS_MASK_32BIT:
  154. case BUS_MASK_32BIT_ECC:
  155. case MV_DDR_32BIT_ECC_PUP8_BUS_MASK:
  156. bus_width = 32;
  157. break;
  158. case MV_DDR_64BIT_BUS_MASK:
  159. case MV_DDR_64BIT_ECC_PUP8_BUS_MASK:
  160. bus_width = 64;
  161. break;
  162. default:
  163. printf("mv_ddr: unsupported bus active mask parameter found\n");
  164. bus_width = 0;
  165. }
  166. return bus_width;
  167. }
  168. unsigned int mv_ddr_cs_num_get(void)
  169. {
  170. unsigned int cs_num = 0;
  171. unsigned int cs, sphy;
  172. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  173. struct if_params *iface_params = &(tm->interface_params[0]);
  174. unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
  175. for (sphy = 0; sphy < sphy_max; sphy++) {
  176. VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
  177. break;
  178. }
  179. for (cs = 0; cs < MAX_CS_NUM; cs++) {
  180. VALIDATE_ACTIVE(iface_params->as_bus_params[sphy].cs_bitmask, cs);
  181. cs_num++;
  182. }
  183. return cs_num;
  184. }
  185. int mv_ddr_is_ecc_ena(void)
  186. {
  187. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  188. if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
  189. DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) ||
  190. DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))
  191. return 1;
  192. else
  193. return 0;
  194. }
  195. int mv_ddr_ck_delay_get(void)
  196. {
  197. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  198. if (tm->ck_delay)
  199. return tm->ck_delay;
  200. return -1;
  201. }
  202. /* translate topology map definition to real memory size in bits */
  203. static unsigned int mem_size[] = {
  204. ADDR_SIZE_512MB,
  205. ADDR_SIZE_1GB,
  206. ADDR_SIZE_2GB,
  207. ADDR_SIZE_4GB,
  208. ADDR_SIZE_8GB
  209. /* TODO: add capacity up to 256GB */
  210. };
  211. unsigned long long mv_ddr_mem_sz_per_cs_get(void)
  212. {
  213. unsigned long long mem_sz_per_cs;
  214. unsigned int i, sphys, sphys_per_dunit;
  215. unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
  216. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  217. struct if_params *iface_params = &(tm->interface_params[0]);
  218. /* calc number of active subphys excl. ecc one */
  219. for (i = 0, sphys = 0; i < sphy_max - 1; i++) {
  220. VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i);
  221. sphys++;
  222. }
  223. /* calc number of subphys per ddr unit */
  224. if (iface_params->bus_width == MV_DDR_DEV_WIDTH_8BIT)
  225. sphys_per_dunit = MV_DDR_ONE_SPHY_PER_DUNIT;
  226. else if (iface_params->bus_width == MV_DDR_DEV_WIDTH_16BIT)
  227. sphys_per_dunit = MV_DDR_TWO_SPHY_PER_DUNIT;
  228. else {
  229. printf("mv_ddr: unsupported bus width type found\n");
  230. return 0;
  231. }
  232. /* calc dram size per cs */
  233. mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
  234. (unsigned long long)sphys /
  235. (unsigned long long)sphys_per_dunit;
  236. return mem_sz_per_cs;
  237. }
  238. unsigned long long mv_ddr_mem_sz_get(void)
  239. {
  240. unsigned long long tot_mem_sz = 0;
  241. unsigned long long mem_sz_per_cs = 0;
  242. unsigned long long max_cs = mv_ddr_cs_num_get();
  243. mem_sz_per_cs = mv_ddr_mem_sz_per_cs_get();
  244. tot_mem_sz = max_cs * mem_sz_per_cs;
  245. return tot_mem_sz;
  246. }
  247. unsigned int mv_ddr_rtt_nom_get(void)
  248. {
  249. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  250. unsigned int rtt_nom = tm->edata.mem_edata.rtt_nom;
  251. if (rtt_nom >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
  252. printf("error: %s: unsupported rtt_nom parameter found\n", __func__);
  253. rtt_nom = PARAM_UNDEFINED;
  254. }
  255. return rtt_nom;
  256. }
  257. unsigned int mv_ddr_rtt_park_get(void)
  258. {
  259. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  260. unsigned int cs_num = mv_ddr_cs_num_get();
  261. unsigned int rtt_park = MV_DDR_RTT_NOM_PARK_RZQ_LAST;
  262. if (cs_num > 0 && cs_num <= MAX_CS_NUM)
  263. rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1];
  264. if (rtt_park >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
  265. printf("error: %s: unsupported rtt_park parameter found\n", __func__);
  266. rtt_park = PARAM_UNDEFINED;
  267. }
  268. return rtt_park;
  269. }
  270. unsigned int mv_ddr_rtt_wr_get(void)
  271. {
  272. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  273. unsigned int cs_num = mv_ddr_cs_num_get();
  274. unsigned int rtt_wr = MV_DDR_RTT_WR_RZQ_LAST;
  275. if (cs_num > 0 && cs_num <= MAX_CS_NUM)
  276. rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1];
  277. if (rtt_wr >= MV_DDR_RTT_WR_RZQ_LAST) {
  278. printf("error: %s: unsupported rtt_wr parameter found\n", __func__);
  279. rtt_wr = PARAM_UNDEFINED;
  280. }
  281. return rtt_wr;
  282. }
  283. unsigned int mv_ddr_dic_get(void)
  284. {
  285. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  286. unsigned int dic = tm->edata.mem_edata.dic;
  287. if (dic >= MV_DDR_DIC_RZQ_LAST) {
  288. printf("error: %s: unsupported dic parameter found\n", __func__);
  289. dic = PARAM_UNDEFINED;
  290. }
  291. return dic;
  292. }