ddr_topology_def.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #ifndef _DDR_TOPOLOGY_DEF_H
  6. #define _DDR_TOPOLOGY_DEF_H
  7. #include "ddr3_training_ip_def.h"
  8. #include "mv_ddr_topology.h"
  9. #include "mv_ddr_spd.h"
  10. #include "ddr3_logging_def.h"
  11. #define MV_DDR_MAX_BUS_NUM 9
  12. #define MV_DDR_MAX_IFACE_NUM 1
  13. struct bus_params {
  14. /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
  15. u8 cs_bitmask;
  16. /*
  17. * mirror enable/disable
  18. * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
  19. */
  20. int mirror_enable_bitmask;
  21. /* DQS Swap (polarity) - true if enable */
  22. int is_dqs_swap;
  23. /* CK swap (polarity) - true if enable */
  24. int is_ck_swap;
  25. };
  26. struct if_params {
  27. /* bus configuration */
  28. struct bus_params as_bus_params[MV_DDR_MAX_BUS_NUM];
  29. /* Speed Bin Table */
  30. enum mv_ddr_speed_bin speed_bin_index;
  31. /* sdram device width */
  32. enum mv_ddr_dev_width bus_width;
  33. /* total sdram capacity per die, megabits */
  34. enum mv_ddr_die_capacity memory_size;
  35. /* The DDR frequency for each interfaces */
  36. enum mv_ddr_freq memory_freq;
  37. /*
  38. * delay CAS Write Latency
  39. * - 0 for using default value (jedec suggested)
  40. */
  41. u8 cas_wl;
  42. /*
  43. * delay CAS Latency
  44. * - 0 for using default value (jedec suggested)
  45. */
  46. u8 cas_l;
  47. /* operation temperature */
  48. enum mv_ddr_temperature interface_temp;
  49. /* 2T vs 1T mode (by default computed from number of CSs) */
  50. enum mv_ddr_timing timing;
  51. };
  52. /* memory electrical configuration */
  53. struct mv_ddr_mem_edata {
  54. enum mv_ddr_rtt_nom_park_evalue rtt_nom;
  55. enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM];
  56. enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM];
  57. enum mv_ddr_dic_evalue dic;
  58. };
  59. /* phy electrical configuration */
  60. struct mv_ddr_phy_edata {
  61. enum mv_ddr_ohm_evalue drv_data_p;
  62. enum mv_ddr_ohm_evalue drv_data_n;
  63. enum mv_ddr_ohm_evalue drv_ctrl_p;
  64. enum mv_ddr_ohm_evalue drv_ctrl_n;
  65. enum mv_ddr_ohm_evalue odt_p[MAX_CS_NUM];
  66. enum mv_ddr_ohm_evalue odt_n[MAX_CS_NUM];
  67. };
  68. /* mac electrical configuration */
  69. struct mv_ddr_mac_edata {
  70. enum mv_ddr_odt_cfg_evalue odt_cfg_pat;
  71. enum mv_ddr_odt_cfg_evalue odt_cfg_wr;
  72. enum mv_ddr_odt_cfg_evalue odt_cfg_rd;
  73. };
  74. struct mv_ddr_edata {
  75. struct mv_ddr_mem_edata mem_edata;
  76. struct mv_ddr_phy_edata phy_edata;
  77. struct mv_ddr_mac_edata mac_edata;
  78. };
  79. struct mv_ddr_topology_map {
  80. /* debug level configuration */
  81. enum mv_ddr_debug_level debug_level;
  82. /* Number of interfaces (default is 12) */
  83. u8 if_act_mask;
  84. /* Controller configuration per interface */
  85. struct if_params interface_params[MV_DDR_MAX_IFACE_NUM];
  86. /* Bit mask for active buses */
  87. u16 bus_act_mask;
  88. /* source of ddr configuration data */
  89. enum mv_ddr_cfg_src cfg_src;
  90. /* raw spd data */
  91. union mv_ddr_spd_data spd_data;
  92. /* timing parameters */
  93. unsigned int timing_data[MV_DDR_TDATA_LAST];
  94. /* electrical configuration */
  95. struct mv_ddr_edata edata;
  96. /* electrical parameters */
  97. unsigned int electrical_data[MV_DDR_EDATA_LAST];
  98. /* Clock enable mask */
  99. u32 clk_enable;
  100. /* Clock delay */
  101. int ck_delay;
  102. };
  103. enum mv_ddr_iface_mode {
  104. MV_DDR_RAR_ENA,
  105. MV_DDR_RAR_DIS,
  106. };
  107. enum mv_ddr_iface_state {
  108. MV_DDR_IFACE_NRDY, /* not ready */
  109. MV_DDR_IFACE_INIT, /* init'd */
  110. MV_DDR_IFACE_RDY, /* ready */
  111. MV_DDR_IFACE_DNE /* does not exist */
  112. };
  113. enum mv_ddr_validation {
  114. MV_DDR_VAL_DIS,
  115. MV_DDR_VAL_RX,
  116. MV_DDR_VAL_TX,
  117. MV_DDR_VAL_RX_TX
  118. };
  119. struct mv_ddr_iface {
  120. /* base addr of ap ddr interface belongs to */
  121. unsigned int ap_base;
  122. /* ddr interface id */
  123. unsigned int id;
  124. /* ddr interface state */
  125. enum mv_ddr_iface_state state;
  126. /* ddr interface mode (rar enabled/disabled) */
  127. enum mv_ddr_iface_mode iface_mode;
  128. /* ddr interface base address */
  129. unsigned long long iface_base_addr;
  130. /* ddr interface size - ddr flow will update this parameter */
  131. unsigned long long iface_byte_size;
  132. /* ddr i2c spd data address */
  133. unsigned int spd_data_addr;
  134. /* ddr i2c spd page 0 select address */
  135. unsigned int spd_page_sel_addr;
  136. /* ddr interface validation mode */
  137. enum mv_ddr_validation validation;
  138. /* ddr interface topology map */
  139. struct mv_ddr_topology_map tm;
  140. };
  141. struct mv_ddr_iface *mv_ddr_iface_get(void);
  142. /* DDR3 training global configuration parameters */
  143. struct tune_train_params {
  144. u32 ck_delay;
  145. u32 phy_reg3_val;
  146. u32 g_zpri_data;
  147. u32 g_znri_data;
  148. u32 g_zpri_ctrl;
  149. u32 g_znri_ctrl;
  150. u32 g_zpodt_data;
  151. u32 g_znodt_data;
  152. u32 g_zpodt_ctrl;
  153. u32 g_znodt_ctrl;
  154. u32 g_dic;
  155. u32 g_odt_config;
  156. u32 g_rtt_nom;
  157. u32 g_rtt_wr;
  158. u32 g_rtt_park;
  159. };
  160. #endif /* _DDR_TOPOLOGY_DEF_H */