ddr3_init.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include "ddr3_init.h"
  6. #include "mv_ddr_common.h"
  7. static char *ddr_type = "DDR3";
  8. /*
  9. * generic_init_controller controls D-unit configuration:
  10. * '1' - dynamic D-unit configuration,
  11. */
  12. u8 generic_init_controller = 1;
  13. static int mv_ddr_training_params_set(u8 dev_num);
  14. /*
  15. * Name: ddr3_init - Main DDR3 Init function
  16. * Desc: This routine initialize the DDR3 MC and runs HW training.
  17. * Args: None.
  18. * Notes:
  19. * Returns: None.
  20. */
  21. int ddr3_init(void)
  22. {
  23. int status;
  24. int is_manual_cal_done;
  25. /* Print mv_ddr version */
  26. mv_ddr_ver_print();
  27. mv_ddr_pre_training_fixup();
  28. /* SoC/Board special initializations */
  29. mv_ddr_pre_training_soc_config(ddr_type);
  30. /* Set log level for training library */
  31. mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
  32. mv_ddr_early_init();
  33. if (mv_ddr_topology_map_update()) {
  34. printf("mv_ddr: failed to update topology\n");
  35. return MV_FAIL;
  36. }
  37. if (mv_ddr_early_init2() != MV_OK)
  38. return MV_FAIL;
  39. /* Set training algorithm's parameters */
  40. status = mv_ddr_training_params_set(0);
  41. if (MV_OK != status)
  42. return status;
  43. mv_ddr_mc_config();
  44. is_manual_cal_done = mv_ddr_manual_cal_do();
  45. mv_ddr_mc_init();
  46. if (!is_manual_cal_done) {
  47. }
  48. status = ddr3_silicon_post_init();
  49. if (MV_OK != status) {
  50. printf("DDR3 Post Init - FAILED 0x%x\n", status);
  51. return status;
  52. }
  53. /* PHY initialization (Training) */
  54. status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC);
  55. if (MV_OK != status) {
  56. printf("%s Training Sequence - FAILED\n", ddr_type);
  57. return status;
  58. }
  59. #if defined(CONFIG_PHY_STATIC_PRINT)
  60. mv_ddr_phy_static_print();
  61. #endif
  62. /* Post MC/PHY initializations */
  63. mv_ddr_post_training_soc_config(ddr_type);
  64. mv_ddr_post_training_fixup();
  65. if (mv_ddr_is_ecc_ena())
  66. mv_ddr_mem_scrubbing();
  67. printf("mv_ddr: completed successfully\n");
  68. return MV_OK;
  69. }
  70. /*
  71. * Name: mv_ddr_training_params_set
  72. * Desc:
  73. * Args:
  74. * Notes: sets internal training params
  75. * Returns:
  76. */
  77. static int mv_ddr_training_params_set(u8 dev_num)
  78. {
  79. struct tune_train_params params;
  80. int status;
  81. u32 cs_num;
  82. int ck_delay;
  83. cs_num = mv_ddr_cs_num_get();
  84. ck_delay = mv_ddr_ck_delay_get();
  85. /* NOTE: do not remove any field initilization */
  86. params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
  87. params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
  88. params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA;
  89. params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA;
  90. params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL;
  91. params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL;
  92. params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA;
  93. params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL;
  94. params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL;
  95. params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA;
  96. params.g_dic = TUNE_TRAINING_PARAMS_DIC;
  97. params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM;
  98. if (cs_num == 1) {
  99. params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
  100. params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
  101. } else {
  102. params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
  103. params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
  104. }
  105. if (ck_delay > 0)
  106. params.ck_delay = ck_delay;
  107. status = ddr3_tip_tune_training_params(dev_num, &params);
  108. if (MV_OK != status) {
  109. printf("%s Training Sequence - FAILED\n", ddr_type);
  110. return status;
  111. }
  112. return MV_OK;
  113. }