meson_dw_hdmi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 BayLibre, SAS
  4. * Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <display.h>
  8. #include <dm.h>
  9. #include <edid.h>
  10. #include <asm/io.h>
  11. #include <dw_hdmi.h>
  12. #include <dm/device-internal.h>
  13. #include <dm/uclass-internal.h>
  14. #include <power/regulator.h>
  15. #include <clk.h>
  16. #include <linux/delay.h>
  17. #include <reset.h>
  18. #include <media_bus_format.h>
  19. #include "meson_dw_hdmi.h"
  20. #include "meson_vpu.h"
  21. /* TOP Block Communication Channel */
  22. #define HDMITX_TOP_ADDR_REG 0x0
  23. #define HDMITX_TOP_DATA_REG 0x4
  24. #define HDMITX_TOP_CTRL_REG 0x8
  25. /* Controller Communication Channel */
  26. #define HDMITX_DWC_ADDR_REG 0x10
  27. #define HDMITX_DWC_DATA_REG 0x14
  28. #define HDMITX_DWC_CTRL_REG 0x18
  29. /* HHI Registers */
  30. #define HHI_MEM_PD_REG0 0x100 /* 0x40 */
  31. #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
  32. #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
  33. #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
  34. #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
  35. #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
  36. struct meson_dw_hdmi {
  37. struct udevice *dev;
  38. struct dw_hdmi hdmi;
  39. void __iomem *hhi_base;
  40. };
  41. enum hdmi_compatible {
  42. HDMI_COMPATIBLE_GXBB = 0,
  43. HDMI_COMPATIBLE_GXL = 1,
  44. HDMI_COMPATIBLE_GXM = 2,
  45. };
  46. static inline bool meson_hdmi_is_compatible(struct meson_dw_hdmi *priv,
  47. enum hdmi_compatible family)
  48. {
  49. enum hdmi_compatible compat = dev_get_driver_data(priv->dev);
  50. return compat == family;
  51. }
  52. static unsigned int dw_hdmi_top_read(struct dw_hdmi *hdmi, unsigned int addr)
  53. {
  54. unsigned int data;
  55. /* ADDR must be written twice */
  56. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  57. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  58. /* Read needs a second DATA read */
  59. data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  60. data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  61. return data;
  62. }
  63. static inline void dw_hdmi_top_write(struct dw_hdmi *hdmi,
  64. unsigned int addr, unsigned int data)
  65. {
  66. /* ADDR must be written twice */
  67. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  68. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  69. /* Write needs single DATA write */
  70. writel(data, hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  71. }
  72. static inline void dw_hdmi_top_write_bits(struct dw_hdmi *hdmi,
  73. unsigned int addr,
  74. unsigned int mask,
  75. unsigned int val)
  76. {
  77. unsigned int data = dw_hdmi_top_read(hdmi, addr);
  78. data &= ~mask;
  79. data |= val;
  80. dw_hdmi_top_write(hdmi, addr, data);
  81. }
  82. static u8 dw_hdmi_dwc_read(struct dw_hdmi *hdmi, int addr)
  83. {
  84. unsigned int data;
  85. /* ADDR must be written twice */
  86. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  87. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  88. /* Read needs a second DATA read */
  89. data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  90. data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  91. return data;
  92. }
  93. static inline void dw_hdmi_dwc_write(struct dw_hdmi *hdmi, u8 data, int addr)
  94. {
  95. /* ADDR must be written twice */
  96. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  97. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  98. /* Write needs single DATA write */
  99. writel(data, hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  100. }
  101. static inline void dw_hdmi_dwc_write_bits(struct dw_hdmi *hdmi,
  102. unsigned int addr,
  103. unsigned int mask,
  104. unsigned int val)
  105. {
  106. u8 data = dw_hdmi_dwc_read(hdmi, addr);
  107. data &= ~mask;
  108. data |= val;
  109. dw_hdmi_dwc_write(hdmi, data, addr);
  110. }
  111. static inline void dw_hdmi_hhi_write(struct meson_dw_hdmi *priv,
  112. unsigned int addr, unsigned int data)
  113. {
  114. hhi_write(addr, data);
  115. }
  116. __attribute__((unused))
  117. static unsigned int dw_hdmi_hhi_read(struct meson_dw_hdmi *priv,
  118. unsigned int addr)
  119. {
  120. return hhi_read(addr);
  121. }
  122. static inline void dw_hdmi_hhi_update_bits(struct meson_dw_hdmi *priv,
  123. unsigned int addr,
  124. unsigned int mask,
  125. unsigned int val)
  126. {
  127. hhi_update_bits(addr, mask, val);
  128. }
  129. static int meson_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  130. {
  131. #if defined DEBUG
  132. struct display_timing timing;
  133. int panel_bits_per_colour;
  134. #endif
  135. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  136. int ret;
  137. ret = dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
  138. #if defined DEBUG
  139. if (!ret)
  140. return ret;
  141. edid_print_info((struct edid1_info *)buf);
  142. edid_get_timing(buf, ret, &timing, &panel_bits_per_colour);
  143. debug("Display timing:\n");
  144. debug(" hactive %04d, hfrontp %04d, hbackp %04d hsync %04d\n"
  145. " vactive %04d, vfrontp %04d, vbackp %04d vsync %04d\n",
  146. timing.hactive.typ, timing.hfront_porch.typ,
  147. timing.hback_porch.typ, timing.hsync_len.typ,
  148. timing.vactive.typ, timing.vfront_porch.typ,
  149. timing.vback_porch.typ, timing.vsync_len.typ);
  150. debug(" flags: ");
  151. if (timing.flags & DISPLAY_FLAGS_INTERLACED)
  152. debug("interlaced ");
  153. if (timing.flags & DISPLAY_FLAGS_DOUBLESCAN)
  154. debug("doublescan ");
  155. if (timing.flags & DISPLAY_FLAGS_DOUBLECLK)
  156. debug("doubleclk ");
  157. if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
  158. debug("hsync_low ");
  159. if (timing.flags & DISPLAY_FLAGS_HSYNC_HIGH)
  160. debug("hsync_high ");
  161. if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
  162. debug("vsync_low ");
  163. if (timing.flags & DISPLAY_FLAGS_VSYNC_HIGH)
  164. debug("vsync_high ");
  165. debug("\n");
  166. #endif
  167. return ret;
  168. }
  169. static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *priv)
  170. {
  171. /* Enable and software reset */
  172. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
  173. mdelay(2);
  174. /* Enable and unreset */
  175. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
  176. mdelay(2);
  177. }
  178. static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv,
  179. uint pixel_clock)
  180. {
  181. pixel_clock = pixel_clock / 1000;
  182. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
  183. meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM)) {
  184. if (pixel_clock >= 371250) {
  185. /* 5.94Gbps, 3.7125Gbps */
  186. hhi_write(HHI_HDMI_PHY_CNTL0, 0x333d3282);
  187. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2136315b);
  188. } else if (pixel_clock >= 297000) {
  189. /* 2.97Gbps */
  190. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303382);
  191. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2036315b);
  192. } else if (pixel_clock >= 148500) {
  193. /* 1.485Gbps */
  194. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303362);
  195. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2016315b);
  196. } else {
  197. /* 742.5Mbps, and below */
  198. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33604142);
  199. hhi_write(HHI_HDMI_PHY_CNTL3, 0x0016315b);
  200. }
  201. } else {
  202. if (pixel_clock >= 371250) {
  203. /* 5.94Gbps, 3.7125Gbps */
  204. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33353245);
  205. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2100115b);
  206. } else if (pixel_clock >= 297000) {
  207. /* 2.97Gbps */
  208. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33634283);
  209. hhi_write(HHI_HDMI_PHY_CNTL3, 0xb000115b);
  210. } else {
  211. /* 1.485Gbps, and below */
  212. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33632122);
  213. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2000115b);
  214. }
  215. }
  216. }
  217. static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock)
  218. {
  219. struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  220. hdmi);
  221. /* Enable clocks */
  222. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
  223. /* Bring HDMITX MEM output of power down */
  224. dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
  225. /* Bring out of reset */
  226. dw_hdmi_top_write(hdmi, HDMITX_TOP_SW_RESET, 0);
  227. /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
  228. dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3, 0x3);
  229. dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3 << 4, 0x3 << 4);
  230. /* Enable normal output to PHY */
  231. dw_hdmi_top_write(hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
  232. /* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */
  233. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
  234. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
  235. /* Load TMDS pattern */
  236. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
  237. mdelay(20);
  238. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
  239. /* Setup PHY parameters */
  240. meson_dw_hdmi_phy_setup_mode(priv, pixel_clock);
  241. /* Setup PHY */
  242. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
  243. 0xffff << 16, 0x0390 << 16);
  244. /* BIT_INVERT */
  245. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
  246. meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM))
  247. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, BIT(17), 0);
  248. else
  249. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
  250. BIT(17), BIT(17));
  251. /* Disable clock, fifo, fifo_wr */
  252. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0);
  253. mdelay(100);
  254. /* Reset PHY 3 times in a row */
  255. meson_dw_hdmi_phy_reset(priv);
  256. meson_dw_hdmi_phy_reset(priv);
  257. meson_dw_hdmi_phy_reset(priv);
  258. return 0;
  259. }
  260. static int meson_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
  261. const struct display_timing *edid)
  262. {
  263. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  264. /* will back into meson_dw_hdmi_phy_init */
  265. return dw_hdmi_enable(&priv->hdmi, edid);
  266. }
  267. static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
  268. {
  269. int i;
  270. /* Poll 1 second for HPD signal */
  271. for (i = 0; i < 10; ++i) {
  272. if (dw_hdmi_top_read(hdmi, HDMITX_TOP_STAT0))
  273. return 0;
  274. mdelay(100);
  275. }
  276. return -ETIMEDOUT;
  277. }
  278. static int meson_dw_hdmi_probe(struct udevice *dev)
  279. {
  280. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  281. struct reset_ctl_bulk resets;
  282. struct clk_bulk clocks;
  283. struct udevice *supply;
  284. int ret;
  285. priv->dev = dev;
  286. priv->hdmi.ioaddr = (ulong)dev_remap_addr_index(dev, 0);
  287. if (!priv->hdmi.ioaddr)
  288. return -EINVAL;
  289. priv->hhi_base = dev_remap_addr_index(dev, 1);
  290. if (!priv->hhi_base)
  291. return -EINVAL;
  292. priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  293. priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
  294. priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
  295. priv->hdmi.write_reg = dw_hdmi_dwc_write;
  296. priv->hdmi.read_reg = dw_hdmi_dwc_read;
  297. priv->hdmi.i2c_clk_high = 0x67;
  298. priv->hdmi.i2c_clk_low = 0x78;
  299. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  300. ret = device_get_supply_regulator(dev, "hdmi-supply", &supply);
  301. if (ret && ret != -ENOENT) {
  302. pr_err("Failed to get HDMI regulator\n");
  303. return ret;
  304. }
  305. if (!ret) {
  306. ret = regulator_set_enable(supply, true);
  307. if (ret)
  308. return ret;
  309. }
  310. #endif
  311. ret = reset_get_bulk(dev, &resets);
  312. if (ret)
  313. return ret;
  314. ret = clk_get_bulk(dev, &clocks);
  315. if (ret)
  316. return ret;
  317. ret = clk_enable_bulk(&clocks);
  318. if (ret)
  319. return ret;
  320. /* Enable clocks */
  321. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
  322. /* Bring HDMITX MEM output of power down */
  323. dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
  324. /* Reset HDMITX APB & TX & PHY: cycle needed for EDID */
  325. ret = reset_deassert_bulk(&resets);
  326. if (ret)
  327. return ret;
  328. ret = reset_assert_bulk(&resets);
  329. if (ret)
  330. return ret;
  331. ret = reset_deassert_bulk(&resets);
  332. if (ret)
  333. return ret;
  334. /* Enable APB3 fail on error */
  335. writel_bits(BIT(15), BIT(15), priv->hdmi.ioaddr + HDMITX_TOP_CTRL_REG);
  336. writel_bits(BIT(15), BIT(15), priv->hdmi.ioaddr + HDMITX_DWC_CTRL_REG);
  337. /* Bring out of reset */
  338. dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_SW_RESET, 0);
  339. mdelay(20);
  340. dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_CLK_CNTL, 0xff);
  341. dw_hdmi_init(&priv->hdmi);
  342. dw_hdmi_phy_init(&priv->hdmi);
  343. /* wait for connector */
  344. ret = meson_dw_hdmi_wait_hpd(&priv->hdmi);
  345. if (ret)
  346. debug("hdmi can not get hpd signal\n");
  347. return ret;
  348. }
  349. static bool meson_dw_hdmi_mode_valid(struct udevice *dev,
  350. const struct display_timing *timing)
  351. {
  352. return meson_venc_hdmi_supported_mode(timing);
  353. }
  354. static const struct dm_display_ops meson_dw_hdmi_ops = {
  355. .read_edid = meson_dw_hdmi_read_edid,
  356. .enable = meson_dw_hdmi_enable,
  357. .mode_valid = meson_dw_hdmi_mode_valid,
  358. };
  359. static const struct udevice_id meson_dw_hdmi_ids[] = {
  360. { .compatible = "amlogic,meson-gxbb-dw-hdmi",
  361. .data = HDMI_COMPATIBLE_GXBB },
  362. { .compatible = "amlogic,meson-gxl-dw-hdmi",
  363. .data = HDMI_COMPATIBLE_GXL },
  364. { .compatible = "amlogic,meson-gxm-dw-hdmi",
  365. .data = HDMI_COMPATIBLE_GXM },
  366. { }
  367. };
  368. U_BOOT_DRIVER(meson_dw_hdmi) = {
  369. .name = "meson_dw_hdmi",
  370. .id = UCLASS_DISPLAY,
  371. .of_match = meson_dw_hdmi_ids,
  372. .ops = &meson_dw_hdmi_ops,
  373. .probe = meson_dw_hdmi_probe,
  374. .priv_auto_alloc_size = sizeof(struct meson_dw_hdmi),
  375. };