MPC8548CDS.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * mpc8548cds board configuration file
  8. *
  9. * Please refer to doc/README.mpc85xxcds for more info.
  10. *
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. #define CONFIG_SYS_SRIO
  15. #define CONFIG_SRIO1 /* SRIO port 1 */
  16. #define CONFIG_PCI1 /* PCI controller 1 */
  17. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  18. #undef CONFIG_PCI2
  19. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  20. #define CONFIG_ENV_OVERWRITE
  21. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  22. #define CONFIG_FSL_VIA
  23. #ifndef __ASSEMBLY__
  24. #include <linux/stringify.h>
  25. extern unsigned long get_clock_freq(void);
  26. #endif
  27. #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  28. /*
  29. * These can be toggled for performance analysis, otherwise use default.
  30. */
  31. #define CONFIG_L2_CACHE /* toggle L2 cache */
  32. #define CONFIG_BTB /* toggle branch predition */
  33. /*
  34. * Only possible on E500 Version 2 or newer cores.
  35. */
  36. #define CONFIG_ENABLE_36BIT_PHYS 1
  37. #ifdef CONFIG_PHYS_64BIT
  38. #define CONFIG_ADDR_MAP
  39. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  40. #endif
  41. #define CONFIG_SYS_CCSRBAR 0xe0000000
  42. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  43. /* DDR Setup */
  44. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  45. #define CONFIG_DDR_SPD
  46. #define CONFIG_DDR_ECC
  47. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  48. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  49. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  50. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  51. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  52. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  53. /* I2C addresses of SPD EEPROMs */
  54. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  55. /* Make sure required options are set */
  56. #ifndef CONFIG_SPD_EEPROM
  57. #error ("CONFIG_SPD_EEPROM is required")
  58. #endif
  59. /*
  60. * Physical Address Map
  61. *
  62. * 32bit:
  63. * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
  64. * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
  65. * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
  66. * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
  67. * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
  68. * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
  69. * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
  70. * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
  71. * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
  72. * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
  73. * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
  74. *
  75. * 36bit:
  76. * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
  77. * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
  78. * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
  79. * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
  80. * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
  81. * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
  82. * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
  83. * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
  84. * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
  85. * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
  86. * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
  87. *
  88. */
  89. /*
  90. * Local Bus Definitions
  91. */
  92. /*
  93. * FLASH on the Local Bus
  94. * Two banks, 8M each, using the CFI driver.
  95. * Boot from BR0/OR0 bank at 0xff00_0000
  96. * Alternate BR1/OR1 bank at 0xff80_0000
  97. *
  98. * BR0, BR1:
  99. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  100. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  101. * Port Size = 16 bits = BRx[19:20] = 10
  102. * Use GPCM = BRx[24:26] = 000
  103. * Valid = BRx[31] = 1
  104. *
  105. * 0 4 8 12 16 20 24 28
  106. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  107. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  108. *
  109. * OR0, OR1:
  110. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  111. * Reserved ORx[17:18] = 11, confusion here?
  112. * CSNT = ORx[20] = 1
  113. * ACS = half cycle delay = ORx[21:22] = 11
  114. * SCY = 6 = ORx[24:27] = 0110
  115. * TRLX = use relaxed timing = ORx[29] = 1
  116. * EAD = use external address latch delay = OR[31] = 1
  117. *
  118. * 0 4 8 12 16 20 24 28
  119. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  120. */
  121. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  122. #ifdef CONFIG_PHYS_64BIT
  123. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
  124. #else
  125. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  126. #endif
  127. #define CONFIG_SYS_BR0_PRELIM \
  128. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
  129. #define CONFIG_SYS_BR1_PRELIM \
  130. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  131. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  132. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  133. #define CONFIG_SYS_FLASH_BANKS_LIST \
  134. {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
  135. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  136. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  137. #undef CONFIG_SYS_FLASH_CHECKSUM
  138. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  139. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  140. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  141. #define CONFIG_SYS_FLASH_EMPTY_INFO
  142. #define CONFIG_HWCONFIG /* enable hwconfig */
  143. /*
  144. * SDRAM on the Local Bus
  145. */
  146. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  147. #ifdef CONFIG_PHYS_64BIT
  148. #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
  149. #else
  150. #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
  151. #endif
  152. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  153. /*
  154. * Base Register 2 and Option Register 2 configure SDRAM.
  155. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  156. *
  157. * For BR2, need:
  158. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  159. * port-size = 32-bits = BR2[19:20] = 11
  160. * no parity checking = BR2[21:22] = 00
  161. * SDRAM for MSEL = BR2[24:26] = 011
  162. * Valid = BR[31] = 1
  163. *
  164. * 0 4 8 12 16 20 24 28
  165. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  166. *
  167. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  168. * FIXME: the top 17 bits of BR2.
  169. */
  170. #define CONFIG_SYS_BR2_PRELIM \
  171. (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
  172. | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
  173. /*
  174. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  175. *
  176. * For OR2, need:
  177. * 64MB mask for AM, OR2[0:7] = 1111 1100
  178. * XAM, OR2[17:18] = 11
  179. * 9 columns OR2[19-21] = 010
  180. * 13 rows OR2[23-25] = 100
  181. * EAD set for extra time OR[31] = 1
  182. *
  183. * 0 4 8 12 16 20 24 28
  184. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  185. */
  186. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  187. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  188. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  189. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  190. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  191. /*
  192. * Common settings for all Local Bus SDRAM commands.
  193. * At run time, either BSMA1516 (for CPU 1.1)
  194. * or BSMA1617 (for CPU 1.0) (old)
  195. * is OR'ed in too.
  196. */
  197. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  198. | LSDMR_PRETOACT7 \
  199. | LSDMR_ACTTORW7 \
  200. | LSDMR_BL8 \
  201. | LSDMR_WRC4 \
  202. | LSDMR_CL3 \
  203. | LSDMR_RFEN \
  204. )
  205. /*
  206. * The CADMUS registers are connected to CS3 on CDS.
  207. * The new memory map places CADMUS at 0xf8000000.
  208. *
  209. * For BR3, need:
  210. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  211. * port-size = 8-bits = BR[19:20] = 01
  212. * no parity checking = BR[21:22] = 00
  213. * GPMC for MSEL = BR[24:26] = 000
  214. * Valid = BR[31] = 1
  215. *
  216. * 0 4 8 12 16 20 24 28
  217. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  218. *
  219. * For OR3, need:
  220. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  221. * disable buffer ctrl OR[19] = 0
  222. * CSNT OR[20] = 1
  223. * ACS OR[21:22] = 11
  224. * XACS OR[23] = 1
  225. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  226. * SETA OR[28] = 0
  227. * TRLX OR[29] = 1
  228. * EHTR OR[30] = 1
  229. * EAD extra time OR[31] = 1
  230. *
  231. * 0 4 8 12 16 20 24 28
  232. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  233. */
  234. #define CONFIG_FSL_CADMUS
  235. #define CADMUS_BASE_ADDR 0xf8000000
  236. #ifdef CONFIG_PHYS_64BIT
  237. #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
  238. #else
  239. #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
  240. #endif
  241. #define CONFIG_SYS_BR3_PRELIM \
  242. (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
  243. #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
  244. #define CONFIG_SYS_INIT_RAM_LOCK 1
  245. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  246. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  247. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  248. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  249. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  250. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  251. /* Serial Port */
  252. #define CONFIG_SYS_NS16550_SERIAL
  253. #define CONFIG_SYS_NS16550_REG_SIZE 1
  254. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  255. #define CONFIG_SYS_BAUDRATE_TABLE \
  256. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  257. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  258. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  259. /*
  260. * I2C
  261. */
  262. #ifndef CONFIG_DM_I2C
  263. #define CONFIG_SYS_I2C
  264. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  265. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  266. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  267. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  268. #else
  269. #define CONFIG_SYS_SPD_BUS_NUM 0
  270. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  271. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  272. #endif
  273. #define CONFIG_SYS_I2C_FSL
  274. /* EEPROM */
  275. #define CONFIG_ID_EEPROM
  276. #define CONFIG_SYS_I2C_EEPROM_CCID
  277. #define CONFIG_SYS_ID_EEPROM
  278. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  279. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  280. /*
  281. * General PCI
  282. * Memory space is mapped 1-1, but I/O space must start from 0.
  283. */
  284. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  285. #ifdef CONFIG_PHYS_64BIT
  286. #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
  287. #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
  288. #else
  289. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  290. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  291. #endif
  292. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  293. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  294. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  295. #ifdef CONFIG_PHYS_64BIT
  296. #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
  297. #else
  298. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  299. #endif
  300. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  301. #ifdef CONFIG_PCIE1
  302. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  303. #ifdef CONFIG_PHYS_64BIT
  304. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
  305. #else
  306. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  307. #endif
  308. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
  309. #ifdef CONFIG_PHYS_64BIT
  310. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
  311. #else
  312. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
  313. #endif
  314. #endif
  315. /*
  316. * RapidIO MMU
  317. */
  318. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
  319. #ifdef CONFIG_PHYS_64BIT
  320. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
  321. #else
  322. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
  323. #endif
  324. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
  325. #ifdef CONFIG_LEGACY
  326. #define BRIDGE_ID 17
  327. #define VIA_ID 2
  328. #else
  329. #define BRIDGE_ID 28
  330. #define VIA_ID 4
  331. #endif
  332. #if defined(CONFIG_PCI)
  333. #undef CONFIG_TULIP
  334. #if !defined(CONFIG_DM_PCI)
  335. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  336. #define CONFIG_PCI_INDIRECT_BRIDGE 1
  337. #define CONFIG_SYS_PCIE1_NAME "Slot"
  338. #ifdef CONFIG_PHYS_64BIT
  339. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  340. #else
  341. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  342. #endif
  343. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  344. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  345. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
  346. #endif
  347. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  348. #endif /* CONFIG_PCI */
  349. #if defined(CONFIG_TSEC_ENET)
  350. #define CONFIG_TSEC1 1
  351. #define CONFIG_TSEC1_NAME "eTSEC0"
  352. #define CONFIG_TSEC2 1
  353. #define CONFIG_TSEC2_NAME "eTSEC1"
  354. #define CONFIG_TSEC3 1
  355. #define CONFIG_TSEC3_NAME "eTSEC2"
  356. #define CONFIG_TSEC4
  357. #define CONFIG_TSEC4_NAME "eTSEC3"
  358. #undef CONFIG_MPC85XX_FEC
  359. #define TSEC1_PHY_ADDR 0
  360. #define TSEC2_PHY_ADDR 1
  361. #define TSEC3_PHY_ADDR 2
  362. #define TSEC4_PHY_ADDR 3
  363. #define TSEC1_PHYIDX 0
  364. #define TSEC2_PHYIDX 0
  365. #define TSEC3_PHYIDX 0
  366. #define TSEC4_PHYIDX 0
  367. #define TSEC1_FLAGS TSEC_GIGABIT
  368. #define TSEC2_FLAGS TSEC_GIGABIT
  369. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  370. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  371. /* Options are: eTSEC[0-3] */
  372. #define CONFIG_ETHPRIME "eTSEC0"
  373. #endif /* CONFIG_TSEC_ENET */
  374. /*
  375. * Environment
  376. */
  377. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  378. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  379. /*
  380. * BOOTP options
  381. */
  382. #define CONFIG_BOOTP_BOOTFILESIZE
  383. #undef CONFIG_WATCHDOG /* watchdog disabled */
  384. /*
  385. * Miscellaneous configurable options
  386. */
  387. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  388. /*
  389. * For booting Linux, the board info and command line data
  390. * have to be in the first 64 MB of memory, since this is
  391. * the maximum mapped by the Linux kernel during initialization.
  392. */
  393. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  394. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  395. #if defined(CONFIG_CMD_KGDB)
  396. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  397. #endif
  398. /*
  399. * Environment Configuration
  400. */
  401. #if defined(CONFIG_TSEC_ENET)
  402. #define CONFIG_HAS_ETH0
  403. #define CONFIG_HAS_ETH1
  404. #define CONFIG_HAS_ETH2
  405. #define CONFIG_HAS_ETH3
  406. #endif
  407. #define CONFIG_IPADDR 192.168.1.253
  408. #define CONFIG_HOSTNAME "unknown"
  409. #define CONFIG_ROOTPATH "/nfsroot"
  410. #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
  411. #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
  412. #define CONFIG_SERVERIP 192.168.1.1
  413. #define CONFIG_GATEWAYIP 192.168.1.1
  414. #define CONFIG_NETMASK 255.255.255.0
  415. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  416. #define CONFIG_EXTRA_ENV_SETTINGS \
  417. "hwconfig=fsl_ddr:ecc=off\0" \
  418. "netdev=eth0\0" \
  419. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  420. "tftpflash=tftpboot $loadaddr $uboot; " \
  421. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  422. " +$filesize; " \
  423. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  424. " +$filesize; " \
  425. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  426. " $filesize; " \
  427. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  428. " +$filesize; " \
  429. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  430. " $filesize\0" \
  431. "consoledev=ttyS1\0" \
  432. "ramdiskaddr=2000000\0" \
  433. "ramdiskfile=ramdisk.uboot\0" \
  434. "fdtaddr=1e00000\0" \
  435. "fdtfile=mpc8548cds.dtb\0"
  436. #define CONFIG_NFSBOOTCOMMAND \
  437. "setenv bootargs root=/dev/nfs rw " \
  438. "nfsroot=$serverip:$rootpath " \
  439. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  440. "console=$consoledev,$baudrate $othbootargs;" \
  441. "tftp $loadaddr $bootfile;" \
  442. "tftp $fdtaddr $fdtfile;" \
  443. "bootm $loadaddr - $fdtaddr"
  444. #define CONFIG_RAMBOOTCOMMAND \
  445. "setenv bootargs root=/dev/ram rw " \
  446. "console=$consoledev,$baudrate $othbootargs;" \
  447. "tftp $ramdiskaddr $ramdiskfile;" \
  448. "tftp $loadaddr $bootfile;" \
  449. "tftp $fdtaddr $fdtfile;" \
  450. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  451. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  452. #endif /* __CONFIG_H */