MPC8541CDS.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2011 Freescale Semiconductor.
  4. */
  5. /*
  6. * mpc8541cds board configuration file
  7. *
  8. * Please refer to doc/README.mpc85xxcds for more info.
  9. *
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /* High Level Configuration Options */
  14. #define CONFIG_CPM2 1 /* has CPM2 */
  15. #define CONFIG_PCI_INDIRECT_BRIDGE
  16. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  17. #define CONFIG_ENV_OVERWRITE
  18. #define CONFIG_FSL_VIA
  19. #ifndef __ASSEMBLY__
  20. extern unsigned long get_clock_freq(void);
  21. #endif
  22. #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  23. /*
  24. * These can be toggled for performance analysis, otherwise use default.
  25. */
  26. #define CONFIG_L2_CACHE /* toggle L2 cache */
  27. #define CONFIG_BTB /* toggle branch predition */
  28. #define CONFIG_SYS_CCSRBAR 0xe0000000
  29. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  30. /* DDR Setup */
  31. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  32. #define CONFIG_DDR_SPD
  33. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  34. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  35. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  36. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  37. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  38. /* I2C addresses of SPD EEPROMs */
  39. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  40. /*
  41. * Make sure required options are set
  42. */
  43. #ifndef CONFIG_SPD_EEPROM
  44. #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  45. #endif
  46. /*
  47. * Local Bus Definitions
  48. */
  49. /*
  50. * FLASH on the Local Bus
  51. * Two banks, 8M each, using the CFI driver.
  52. * Boot from BR0/OR0 bank at 0xff00_0000
  53. * Alternate BR1/OR1 bank at 0xff80_0000
  54. *
  55. * BR0, BR1:
  56. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  57. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  58. * Port Size = 16 bits = BRx[19:20] = 10
  59. * Use GPCM = BRx[24:26] = 000
  60. * Valid = BRx[31] = 1
  61. *
  62. * 0 4 8 12 16 20 24 28
  63. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  64. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  65. *
  66. * OR0, OR1:
  67. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  68. * Reserved ORx[17:18] = 11, confusion here?
  69. * CSNT = ORx[20] = 1
  70. * ACS = half cycle delay = ORx[21:22] = 11
  71. * SCY = 6 = ORx[24:27] = 0110
  72. * TRLX = use relaxed timing = ORx[29] = 1
  73. * EAD = use external address latch delay = OR[31] = 1
  74. *
  75. * 0 4 8 12 16 20 24 28
  76. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  77. */
  78. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
  79. #define CONFIG_SYS_BR0_PRELIM 0xff801001
  80. #define CONFIG_SYS_BR1_PRELIM 0xff001001
  81. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  82. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  83. #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
  84. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  85. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  86. #undef CONFIG_SYS_FLASH_CHECKSUM
  87. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  88. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  89. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  90. #define CONFIG_SYS_FLASH_EMPTY_INFO
  91. /*
  92. * SDRAM on the Local Bus
  93. */
  94. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  95. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  96. /*
  97. * Base Register 2 and Option Register 2 configure SDRAM.
  98. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  99. *
  100. * For BR2, need:
  101. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  102. * port-size = 32-bits = BR2[19:20] = 11
  103. * no parity checking = BR2[21:22] = 00
  104. * SDRAM for MSEL = BR2[24:26] = 011
  105. * Valid = BR[31] = 1
  106. *
  107. * 0 4 8 12 16 20 24 28
  108. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  109. *
  110. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  111. * FIXME: the top 17 bits of BR2.
  112. */
  113. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  114. /*
  115. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  116. *
  117. * For OR2, need:
  118. * 64MB mask for AM, OR2[0:7] = 1111 1100
  119. * XAM, OR2[17:18] = 11
  120. * 9 columns OR2[19-21] = 010
  121. * 13 rows OR2[23-25] = 100
  122. * EAD set for extra time OR[31] = 1
  123. *
  124. * 0 4 8 12 16 20 24 28
  125. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  126. */
  127. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  128. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  129. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  130. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  131. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  132. /*
  133. * Common settings for all Local Bus SDRAM commands.
  134. * At run time, either BSMA1516 (for CPU 1.1)
  135. * or BSMA1617 (for CPU 1.0) (old)
  136. * is OR'ed in too.
  137. */
  138. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  139. | LSDMR_PRETOACT7 \
  140. | LSDMR_ACTTORW7 \
  141. | LSDMR_BL8 \
  142. | LSDMR_WRC4 \
  143. | LSDMR_CL3 \
  144. | LSDMR_RFEN \
  145. )
  146. /*
  147. * The CADMUS registers are connected to CS3 on CDS.
  148. * The new memory map places CADMUS at 0xf8000000.
  149. *
  150. * For BR3, need:
  151. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  152. * port-size = 8-bits = BR[19:20] = 01
  153. * no parity checking = BR[21:22] = 00
  154. * GPMC for MSEL = BR[24:26] = 000
  155. * Valid = BR[31] = 1
  156. *
  157. * 0 4 8 12 16 20 24 28
  158. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  159. *
  160. * For OR3, need:
  161. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  162. * disable buffer ctrl OR[19] = 0
  163. * CSNT OR[20] = 1
  164. * ACS OR[21:22] = 11
  165. * XACS OR[23] = 1
  166. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  167. * SETA OR[28] = 0
  168. * TRLX OR[29] = 1
  169. * EHTR OR[30] = 1
  170. * EAD extra time OR[31] = 1
  171. *
  172. * 0 4 8 12 16 20 24 28
  173. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  174. */
  175. #define CONFIG_FSL_CADMUS
  176. #define CADMUS_BASE_ADDR 0xf8000000
  177. #define CONFIG_SYS_BR3_PRELIM 0xf8000801
  178. #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
  179. #define CONFIG_SYS_INIT_RAM_LOCK 1
  180. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  181. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  182. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  183. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  184. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  185. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  186. /* Serial Port */
  187. #define CONFIG_SYS_NS16550_SERIAL
  188. #define CONFIG_SYS_NS16550_REG_SIZE 1
  189. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  190. #define CONFIG_SYS_BAUDRATE_TABLE \
  191. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  192. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  193. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  194. /*
  195. * I2C
  196. */
  197. #define CONFIG_SYS_I2C
  198. #define CONFIG_SYS_I2C_FSL
  199. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  200. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  201. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  202. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  203. /* EEPROM */
  204. #define CONFIG_ID_EEPROM
  205. #define CONFIG_SYS_I2C_EEPROM_CCID
  206. #define CONFIG_SYS_ID_EEPROM
  207. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  208. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  209. /*
  210. * General PCI
  211. * Memory space is mapped 1-1, but I/O space must start from 0.
  212. */
  213. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  214. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  215. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  216. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  217. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  218. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  219. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  220. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  221. #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
  222. #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  223. #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
  224. #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
  225. #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
  226. #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
  227. #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
  228. #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
  229. #ifdef CONFIG_LEGACY
  230. #define BRIDGE_ID 17
  231. #define VIA_ID 2
  232. #else
  233. #define BRIDGE_ID 28
  234. #define VIA_ID 4
  235. #endif
  236. #if defined(CONFIG_PCI)
  237. #define CONFIG_MPC85XX_PCI2
  238. #undef CONFIG_TULIP
  239. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  240. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  241. #endif /* CONFIG_PCI */
  242. #if defined(CONFIG_TSEC_ENET)
  243. #define CONFIG_TSEC1 1
  244. #define CONFIG_TSEC1_NAME "TSEC0"
  245. #define CONFIG_TSEC2 1
  246. #define CONFIG_TSEC2_NAME "TSEC1"
  247. #define TSEC1_PHY_ADDR 0
  248. #define TSEC2_PHY_ADDR 1
  249. #define TSEC1_PHYIDX 0
  250. #define TSEC2_PHYIDX 0
  251. #define TSEC1_FLAGS TSEC_GIGABIT
  252. #define TSEC2_FLAGS TSEC_GIGABIT
  253. /* Options are: TSEC[0-1] */
  254. #define CONFIG_ETHPRIME "TSEC0"
  255. #endif /* CONFIG_TSEC_ENET */
  256. /*
  257. * Environment
  258. */
  259. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  260. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  261. /*
  262. * BOOTP options
  263. */
  264. #define CONFIG_BOOTP_BOOTFILESIZE
  265. #undef CONFIG_WATCHDOG /* watchdog disabled */
  266. /*
  267. * Miscellaneous configurable options
  268. */
  269. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  270. /*
  271. * For booting Linux, the board info and command line data
  272. * have to be in the first 64 MB of memory, since this is
  273. * the maximum mapped by the Linux kernel during initialization.
  274. */
  275. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  276. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  277. #if defined(CONFIG_CMD_KGDB)
  278. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  279. #endif
  280. /*
  281. * Environment Configuration
  282. */
  283. /* The mac addresses for all ethernet interface */
  284. #if defined(CONFIG_TSEC_ENET)
  285. #define CONFIG_HAS_ETH0
  286. #define CONFIG_HAS_ETH1
  287. #define CONFIG_HAS_ETH2
  288. #endif
  289. #define CONFIG_IPADDR 192.168.1.253
  290. #define CONFIG_HOSTNAME "unknown"
  291. #define CONFIG_ROOTPATH "/nfsroot"
  292. #define CONFIG_BOOTFILE "your.uImage"
  293. #define CONFIG_SERVERIP 192.168.1.1
  294. #define CONFIG_GATEWAYIP 192.168.1.1
  295. #define CONFIG_NETMASK 255.255.255.0
  296. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  297. #define CONFIG_EXTRA_ENV_SETTINGS \
  298. "netdev=eth0\0" \
  299. "consoledev=ttyS1\0" \
  300. "ramdiskaddr=600000\0" \
  301. "ramdiskfile=your.ramdisk.u-boot\0" \
  302. "fdtaddr=400000\0" \
  303. "fdtfile=your.fdt.dtb\0"
  304. #define CONFIG_NFSBOOTCOMMAND \
  305. "setenv bootargs root=/dev/nfs rw " \
  306. "nfsroot=$serverip:$rootpath " \
  307. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  308. "console=$consoledev,$baudrate $othbootargs;" \
  309. "tftp $loadaddr $bootfile;" \
  310. "tftp $fdtaddr $fdtfile;" \
  311. "bootm $loadaddr - $fdtaddr"
  312. #define CONFIG_RAMBOOTCOMMAND \
  313. "setenv bootargs root=/dev/ram rw " \
  314. "console=$consoledev,$baudrate $othbootargs;" \
  315. "tftp $ramdiskaddr $ramdiskfile;" \
  316. "tftp $loadaddr $bootfile;" \
  317. "bootm $loadaddr $ramdiskaddr"
  318. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  319. #endif /* __CONFIG_H */