MPC8540ADS.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2011 Freescale Semiconductor.
  4. * (C) Copyright 2002,2003 Motorola,Inc.
  5. * Xianghua Xiao <X.Xiao@motorola.com>
  6. */
  7. /*
  8. * mpc8540ads board configuration file
  9. *
  10. * Please refer to doc/README.mpc85xx for more info.
  11. *
  12. * Make sure you change the MAC address and other network params first,
  13. * search for CONFIG_SERVERIP, etc in this file.
  14. */
  15. #ifndef __CONFIG_H
  16. #define __CONFIG_H
  17. /*
  18. * default CCARBAR is at 0xff700000
  19. * assume U-Boot is less than 0.5MB
  20. */
  21. #ifndef CONFIG_HAS_FEC
  22. #define CONFIG_HAS_FEC 1 /* 8540 has FEC */
  23. #endif
  24. #define CONFIG_PCI_INDIRECT_BRIDGE
  25. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  26. #define CONFIG_ENV_OVERWRITE
  27. /*
  28. * sysclk for MPC85xx
  29. *
  30. * Two valid values are:
  31. * 33000000
  32. * 66000000
  33. *
  34. * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  35. * is likely the desired value here, so that is now the default.
  36. * The board, however, can run at 66MHz. In any event, this value
  37. * must match the settings of some switches. Details can be found
  38. * in the README.mpc85xxads.
  39. *
  40. * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
  41. * 33MHz to accommodate, based on a PCI pin.
  42. * Note that PCI-X won't work at 33MHz.
  43. */
  44. #ifndef CONFIG_SYS_CLK_FREQ
  45. #define CONFIG_SYS_CLK_FREQ 33000000
  46. #endif
  47. /*
  48. * These can be toggled for performance analysis, otherwise use default.
  49. */
  50. #define CONFIG_L2_CACHE /* toggle L2 cache */
  51. #define CONFIG_BTB /* toggle branch predition */
  52. #define CONFIG_SYS_CCSRBAR 0xe0000000
  53. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  54. /* DDR Setup */
  55. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  56. #define CONFIG_DDR_SPD
  57. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  58. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  59. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  60. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  61. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  62. /* I2C addresses of SPD EEPROMs */
  63. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  64. /* These are used when DDR doesn't use SPD. */
  65. #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
  66. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
  67. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
  68. #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  69. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  70. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  71. #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  72. #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
  73. /*
  74. * SDRAM on the Local Bus
  75. */
  76. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  77. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  78. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  79. #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
  80. #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
  81. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  82. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  83. #undef CONFIG_SYS_FLASH_CHECKSUM
  84. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  85. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  86. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  87. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  88. #define CONFIG_SYS_RAMBOOT
  89. #else
  90. #undef CONFIG_SYS_RAMBOOT
  91. #endif
  92. #define CONFIG_SYS_FLASH_EMPTY_INFO
  93. /*
  94. * Local Bus Definitions
  95. */
  96. /*
  97. * Base Register 2 and Option Register 2 configure SDRAM.
  98. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  99. *
  100. * For BR2, need:
  101. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  102. * port-size = 32-bits = BR2[19:20] = 11
  103. * no parity checking = BR2[21:22] = 00
  104. * SDRAM for MSEL = BR2[24:26] = 011
  105. * Valid = BR[31] = 1
  106. *
  107. * 0 4 8 12 16 20 24 28
  108. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  109. *
  110. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  111. * FIXME: the top 17 bits of BR2.
  112. */
  113. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  114. /*
  115. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  116. *
  117. * For OR2, need:
  118. * 64MB mask for AM, OR2[0:7] = 1111 1100
  119. * XAM, OR2[17:18] = 11
  120. * 9 columns OR2[19-21] = 010
  121. * 13 rows OR2[23-25] = 100
  122. * EAD set for extra time OR[31] = 1
  123. *
  124. * 0 4 8 12 16 20 24 28
  125. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  126. */
  127. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  128. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  129. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  130. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  131. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
  132. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
  133. | LSDMR_RFCR5 \
  134. | LSDMR_PRETOACT3 \
  135. | LSDMR_ACTTORW3 \
  136. | LSDMR_BL8 \
  137. | LSDMR_WRC2 \
  138. | LSDMR_CL3 \
  139. | LSDMR_RFEN \
  140. )
  141. /*
  142. * SDRAM Controller configuration sequence.
  143. */
  144. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  145. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  146. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  147. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  148. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  149. /*
  150. * 32KB, 8-bit wide for ADS config reg
  151. */
  152. #define CONFIG_SYS_BR4_PRELIM 0xf8000801
  153. #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
  154. #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
  155. #define CONFIG_SYS_INIT_RAM_LOCK 1
  156. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  157. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  158. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  159. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  160. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  161. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  162. /* Serial Port */
  163. #define CONFIG_SYS_NS16550_SERIAL
  164. #define CONFIG_SYS_NS16550_REG_SIZE 1
  165. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  166. #define CONFIG_SYS_BAUDRATE_TABLE \
  167. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  168. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  169. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  170. /*
  171. * I2C
  172. */
  173. #define CONFIG_SYS_I2C
  174. #define CONFIG_SYS_I2C_FSL
  175. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  176. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  177. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  178. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  179. /* RapidIO MMU */
  180. #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
  181. #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
  182. #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
  183. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
  184. /*
  185. * General PCI
  186. * Memory space is mapped 1-1, but I/O space must start from 0.
  187. */
  188. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  189. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  190. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  191. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  192. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  193. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  194. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  195. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  196. #if defined(CONFIG_PCI)
  197. #undef CONFIG_TULIP
  198. #if !defined(CONFIG_PCI_PNP)
  199. #define PCI_ENET0_IOADDR 0xe0000000
  200. #define PCI_ENET0_MEMADDR 0xe0000000
  201. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  202. #endif
  203. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  204. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  205. #endif /* CONFIG_PCI */
  206. #if defined(CONFIG_TSEC_ENET)
  207. #define CONFIG_TSEC1 1
  208. #define CONFIG_TSEC1_NAME "TSEC0"
  209. #define CONFIG_TSEC2 1
  210. #define CONFIG_TSEC2_NAME "TSEC1"
  211. #define TSEC1_PHY_ADDR 0
  212. #define TSEC2_PHY_ADDR 1
  213. #define TSEC1_PHYIDX 0
  214. #define TSEC2_PHYIDX 0
  215. #define TSEC1_FLAGS TSEC_GIGABIT
  216. #define TSEC2_FLAGS TSEC_GIGABIT
  217. #if CONFIG_HAS_FEC
  218. #define CONFIG_MPC85XX_FEC 1
  219. #define CONFIG_MPC85XX_FEC_NAME "FEC"
  220. #define FEC_PHY_ADDR 3
  221. #define FEC_PHYIDX 0
  222. #define FEC_FLAGS 0
  223. #endif
  224. /* Options are: TSEC[0-1], FEC */
  225. #define CONFIG_ETHPRIME "TSEC0"
  226. #endif /* CONFIG_TSEC_ENET */
  227. /*
  228. * Environment
  229. */
  230. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  231. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  232. /*
  233. * BOOTP options
  234. */
  235. #define CONFIG_BOOTP_BOOTFILESIZE
  236. #undef CONFIG_WATCHDOG /* watchdog disabled */
  237. /*
  238. * Miscellaneous configurable options
  239. */
  240. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  241. /*
  242. * For booting Linux, the board info and command line data
  243. * have to be in the first 64 MB of memory, since this is
  244. * the maximum mapped by the Linux kernel during initialization.
  245. */
  246. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  247. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  248. #if defined(CONFIG_CMD_KGDB)
  249. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  250. #endif
  251. /*
  252. * Environment Configuration
  253. */
  254. /* The mac addresses for all ethernet interface */
  255. #if defined(CONFIG_TSEC_ENET)
  256. #define CONFIG_HAS_ETH0
  257. #define CONFIG_HAS_ETH1
  258. #define CONFIG_HAS_ETH2
  259. #endif
  260. #define CONFIG_IPADDR 192.168.1.253
  261. #define CONFIG_HOSTNAME "unknown"
  262. #define CONFIG_ROOTPATH "/nfsroot"
  263. #define CONFIG_BOOTFILE "your.uImage"
  264. #define CONFIG_SERVERIP 192.168.1.1
  265. #define CONFIG_GATEWAYIP 192.168.1.1
  266. #define CONFIG_NETMASK 255.255.255.0
  267. #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  268. #define CONFIG_EXTRA_ENV_SETTINGS \
  269. "netdev=eth0\0" \
  270. "consoledev=ttyS0\0" \
  271. "ramdiskaddr=1000000\0" \
  272. "ramdiskfile=your.ramdisk.u-boot\0" \
  273. "fdtaddr=400000\0" \
  274. "fdtfile=your.fdt.dtb\0"
  275. #define CONFIG_NFSBOOTCOMMAND \
  276. "setenv bootargs root=/dev/nfs rw " \
  277. "nfsroot=$serverip:$rootpath " \
  278. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  279. "console=$consoledev,$baudrate $othbootargs;" \
  280. "tftp $loadaddr $bootfile;" \
  281. "tftp $fdtaddr $fdtfile;" \
  282. "bootm $loadaddr - $fdtaddr"
  283. #define CONFIG_RAMBOOTCOMMAND \
  284. "setenv bootargs root=/dev/ram rw " \
  285. "console=$consoledev,$baudrate $othbootargs;" \
  286. "tftp $ramdiskaddr $ramdiskfile;" \
  287. "tftp $loadaddr $bootfile;" \
  288. "tftp $fdtaddr $fdtfile;" \
  289. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  290. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  291. #endif /* __CONFIG_H */