dwc3-meson-g12a.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic G12A DWC3 Glue layer
  4. *
  5. * Copyright (C) 2019 BayLibre, SAS
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #include <common.h>
  9. #include <asm-generic/io.h>
  10. #include <dm.h>
  11. #include <dm/device-internal.h>
  12. #include <dm/lists.h>
  13. #include <dwc3-uboot.h>
  14. #include <generic-phy.h>
  15. #include <linux/usb/ch9.h>
  16. #include <linux/usb/gadget.h>
  17. #include <malloc.h>
  18. #include <regmap.h>
  19. #include <usb.h>
  20. #include "core.h"
  21. #include "gadget.h"
  22. #include <reset.h>
  23. #include <clk.h>
  24. #include <power/regulator.h>
  25. #include <linux/bitfield.h>
  26. #include <linux/bitops.h>
  27. #include <linux/compat.h>
  28. /* USB2 Ports Control Registers */
  29. #define U2P_REG_SIZE 0x20
  30. #define U2P_R0 0x0
  31. #define U2P_R0_HOST_DEVICE BIT(0)
  32. #define U2P_R0_POWER_OK BIT(1)
  33. #define U2P_R0_HAST_MODE BIT(2)
  34. #define U2P_R0_POWER_ON_RESET BIT(3)
  35. #define U2P_R0_ID_PULLUP BIT(4)
  36. #define U2P_R0_DRV_VBUS BIT(5)
  37. #define U2P_R1 0x4
  38. #define U2P_R1_PHY_READY BIT(0)
  39. #define U2P_R1_ID_DIG BIT(1)
  40. #define U2P_R1_OTG_SESSION_VALID BIT(2)
  41. #define U2P_R1_VBUS_VALID BIT(3)
  42. /* USB Glue Control Registers */
  43. #define USB_R0 0x80
  44. #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
  45. #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
  46. #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
  47. #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
  48. #define USB_R0_U2D_ACT BIT(31)
  49. #define USB_R1 0x84
  50. #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
  51. #define USB_R1_U3H_PME_ENABLE BIT(1)
  52. #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2)
  53. #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7)
  54. #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12)
  55. #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
  56. #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
  57. #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
  58. #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
  59. #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
  60. #define USB_R2 0x88
  61. #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
  62. #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
  63. #define USB_R3 0x8c
  64. #define USB_R3_P30_SSC_ENABLE BIT(0)
  65. #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
  66. #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
  67. #define USB_R3_P30_REF_SSP_EN BIT(13)
  68. #define USB_R4 0x90
  69. #define USB_R4_P21_PORT_RESET_0 BIT(0)
  70. #define USB_R4_P21_SLEEP_M0 BIT(1)
  71. #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
  72. #define USB_R4_P21_ONLY BIT(4)
  73. #define USB_R5 0x94
  74. #define USB_R5_ID_DIG_SYNC BIT(0)
  75. #define USB_R5_ID_DIG_REG BIT(1)
  76. #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
  77. #define USB_R5_ID_DIG_EN_0 BIT(4)
  78. #define USB_R5_ID_DIG_EN_1 BIT(5)
  79. #define USB_R5_ID_DIG_CURR BIT(6)
  80. #define USB_R5_ID_DIG_IRQ BIT(7)
  81. #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
  82. #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
  83. enum {
  84. USB2_HOST_PHY = 0,
  85. USB2_OTG_PHY,
  86. USB3_HOST_PHY,
  87. PHY_COUNT,
  88. };
  89. static const char *phy_names[PHY_COUNT] = {
  90. "usb2-phy0", "usb2-phy1", "usb3-phy0",
  91. };
  92. struct dwc3_meson_g12a {
  93. struct udevice *dev;
  94. struct regmap *regmap;
  95. struct clk clk;
  96. struct reset_ctl reset;
  97. struct phy phys[PHY_COUNT];
  98. enum usb_dr_mode otg_mode;
  99. enum usb_dr_mode otg_phy_mode;
  100. unsigned int usb2_ports;
  101. unsigned int usb3_ports;
  102. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  103. struct udevice *vbus_supply;
  104. #endif
  105. };
  106. #define U2P_REG_SIZE 0x20
  107. #define USB_REG_OFFSET 0x80
  108. static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
  109. int i, enum usb_dr_mode mode)
  110. {
  111. switch (mode) {
  112. case USB_DR_MODE_HOST:
  113. case USB_DR_MODE_OTG:
  114. case USB_DR_MODE_UNKNOWN:
  115. regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
  116. U2P_R0_HOST_DEVICE,
  117. U2P_R0_HOST_DEVICE);
  118. break;
  119. case USB_DR_MODE_PERIPHERAL:
  120. regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
  121. U2P_R0_HOST_DEVICE, 0);
  122. break;
  123. }
  124. }
  125. static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
  126. {
  127. int i;
  128. if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
  129. priv->otg_phy_mode = USB_DR_MODE_PERIPHERAL;
  130. else
  131. priv->otg_phy_mode = USB_DR_MODE_HOST;
  132. for (i = 0 ; i < USB3_HOST_PHY ; ++i) {
  133. if (!priv->phys[i].dev)
  134. continue;
  135. regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
  136. U2P_R0_POWER_ON_RESET,
  137. U2P_R0_POWER_ON_RESET);
  138. if (i == USB2_OTG_PHY) {
  139. regmap_update_bits(priv->regmap,
  140. U2P_R0 + (U2P_REG_SIZE * i),
  141. U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
  142. U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS);
  143. dwc3_meson_g12a_usb2_set_mode(priv, i,
  144. priv->otg_phy_mode);
  145. } else
  146. dwc3_meson_g12a_usb2_set_mode(priv, i,
  147. USB_DR_MODE_HOST);
  148. regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
  149. U2P_R0_POWER_ON_RESET, 0);
  150. }
  151. return 0;
  152. }
  153. static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
  154. {
  155. regmap_update_bits(priv->regmap, USB_R3,
  156. USB_R3_P30_SSC_RANGE_MASK |
  157. USB_R3_P30_REF_SSP_EN,
  158. USB_R3_P30_SSC_ENABLE |
  159. FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) |
  160. USB_R3_P30_REF_SSP_EN);
  161. udelay(2);
  162. regmap_update_bits(priv->regmap, USB_R2,
  163. USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
  164. FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));
  165. regmap_update_bits(priv->regmap, USB_R2,
  166. USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
  167. FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));
  168. udelay(2);
  169. regmap_update_bits(priv->regmap, USB_R1,
  170. USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
  171. USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);
  172. regmap_update_bits(priv->regmap, USB_R1,
  173. USB_R1_P30_PCS_TX_SWING_FULL_MASK,
  174. FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
  175. }
  176. static void dwc3_meson_g12a_usb_init_mode(struct dwc3_meson_g12a *priv)
  177. {
  178. if (priv->otg_phy_mode == USB_DR_MODE_PERIPHERAL) {
  179. regmap_update_bits(priv->regmap, USB_R0,
  180. USB_R0_U2D_ACT, USB_R0_U2D_ACT);
  181. regmap_update_bits(priv->regmap, USB_R0,
  182. USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
  183. regmap_update_bits(priv->regmap, USB_R4,
  184. USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
  185. } else {
  186. regmap_update_bits(priv->regmap, USB_R0,
  187. USB_R0_U2D_ACT, 0);
  188. regmap_update_bits(priv->regmap, USB_R4,
  189. USB_R4_P21_SLEEP_M0, 0);
  190. }
  191. }
  192. static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
  193. {
  194. int ret;
  195. ret = dwc3_meson_g12a_usb2_init(priv);
  196. if (ret)
  197. return ret;
  198. regmap_update_bits(priv->regmap, USB_R1,
  199. USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
  200. FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
  201. regmap_update_bits(priv->regmap, USB_R5,
  202. USB_R5_ID_DIG_EN_0,
  203. USB_R5_ID_DIG_EN_0);
  204. regmap_update_bits(priv->regmap, USB_R5,
  205. USB_R5_ID_DIG_EN_1,
  206. USB_R5_ID_DIG_EN_1);
  207. regmap_update_bits(priv->regmap, USB_R5,
  208. USB_R5_ID_DIG_TH_MASK,
  209. FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
  210. /* If we have an actual SuperSpeed port, initialize it */
  211. if (priv->usb3_ports)
  212. dwc3_meson_g12a_usb3_init(priv);
  213. dwc3_meson_g12a_usb_init_mode(priv);
  214. return 0;
  215. }
  216. int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode)
  217. {
  218. struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
  219. if (!priv)
  220. return -EINVAL;
  221. if (mode != USB_DR_MODE_HOST && mode != USB_DR_MODE_PERIPHERAL)
  222. return -EINVAL;
  223. if (!priv->phys[USB2_OTG_PHY].dev)
  224. return -EINVAL;
  225. if (mode == priv->otg_mode)
  226. return 0;
  227. if (mode == USB_DR_MODE_HOST)
  228. debug("%s: switching to Host Mode\n", __func__);
  229. else
  230. debug("%s: switching to Device Mode\n", __func__);
  231. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  232. if (priv->vbus_supply) {
  233. int ret = regulator_set_enable(priv->vbus_supply,
  234. (mode == USB_DR_MODE_PERIPHERAL));
  235. if (ret)
  236. return ret;
  237. }
  238. #endif
  239. priv->otg_phy_mode = mode;
  240. dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode);
  241. dwc3_meson_g12a_usb_init_mode(priv);
  242. return 0;
  243. }
  244. static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
  245. {
  246. int i, ret;
  247. for (i = 0 ; i < PHY_COUNT ; ++i) {
  248. ret = generic_phy_get_by_name(priv->dev, phy_names[i],
  249. &priv->phys[i]);
  250. if (ret == -ENOENT)
  251. continue;
  252. if (ret)
  253. return ret;
  254. if (i == USB3_HOST_PHY)
  255. priv->usb3_ports++;
  256. else
  257. priv->usb2_ports++;
  258. }
  259. debug("%s: usb2 ports: %d\n", __func__, priv->usb2_ports);
  260. debug("%s: usb3 ports: %d\n", __func__, priv->usb3_ports);
  261. return 0;
  262. }
  263. static int dwc3_meson_g12a_reset_init(struct dwc3_meson_g12a *priv)
  264. {
  265. int ret;
  266. ret = reset_get_by_index(priv->dev, 0, &priv->reset);
  267. if (ret)
  268. return ret;
  269. ret = reset_assert(&priv->reset);
  270. udelay(1);
  271. ret |= reset_deassert(&priv->reset);
  272. if (ret) {
  273. reset_free(&priv->reset);
  274. return ret;
  275. }
  276. return 0;
  277. }
  278. static int dwc3_meson_g12a_clk_init(struct dwc3_meson_g12a *priv)
  279. {
  280. int ret;
  281. ret = clk_get_by_index(priv->dev, 0, &priv->clk);
  282. if (ret)
  283. return ret;
  284. #if CONFIG_IS_ENABLED(CLK)
  285. ret = clk_enable(&priv->clk);
  286. if (ret) {
  287. clk_free(&priv->clk);
  288. return ret;
  289. }
  290. #endif
  291. return 0;
  292. }
  293. static int dwc3_meson_g12a_probe(struct udevice *dev)
  294. {
  295. struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
  296. int ret, i;
  297. priv->dev = dev;
  298. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  299. if (ret)
  300. return ret;
  301. ret = dwc3_meson_g12a_clk_init(priv);
  302. if (ret)
  303. return ret;
  304. ret = dwc3_meson_g12a_reset_init(priv);
  305. if (ret)
  306. return ret;
  307. ret = dwc3_meson_g12a_get_phys(priv);
  308. if (ret)
  309. return ret;
  310. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  311. ret = device_get_supply_regulator(dev, "vbus-supply",
  312. &priv->vbus_supply);
  313. if (ret && ret != -ENOENT) {
  314. pr_err("Failed to get PHY regulator\n");
  315. return ret;
  316. }
  317. if (priv->vbus_supply) {
  318. ret = regulator_set_enable(priv->vbus_supply, true);
  319. if (ret)
  320. return ret;
  321. }
  322. #endif
  323. priv->otg_mode = usb_get_dr_mode(dev->node);
  324. ret = dwc3_meson_g12a_usb_init(priv);
  325. if (ret)
  326. return ret;
  327. for (i = 0 ; i < PHY_COUNT ; ++i) {
  328. if (!priv->phys[i].dev)
  329. continue;
  330. ret = generic_phy_init(&priv->phys[i]);
  331. if (ret)
  332. goto err_phy_init;
  333. }
  334. for (i = 0; i < PHY_COUNT; ++i) {
  335. if (!priv->phys[i].dev)
  336. continue;
  337. ret = generic_phy_power_on(&priv->phys[i]);
  338. if (ret)
  339. goto err_phy_init;
  340. }
  341. return 0;
  342. err_phy_init:
  343. for (i = 0 ; i < PHY_COUNT ; ++i) {
  344. if (!priv->phys[i].dev)
  345. continue;
  346. generic_phy_exit(&priv->phys[i]);
  347. }
  348. return ret;
  349. }
  350. static int dwc3_meson_g12a_remove(struct udevice *dev)
  351. {
  352. struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
  353. int i;
  354. reset_release_all(&priv->reset, 1);
  355. clk_release_all(&priv->clk, 1);
  356. for (i = 0; i < PHY_COUNT; ++i) {
  357. if (!priv->phys[i].dev)
  358. continue;
  359. generic_phy_power_off(&priv->phys[i]);
  360. }
  361. for (i = 0 ; i < PHY_COUNT ; ++i) {
  362. if (!priv->phys[i].dev)
  363. continue;
  364. generic_phy_exit(&priv->phys[i]);
  365. }
  366. return dm_scan_fdt_dev(dev);
  367. }
  368. static const struct udevice_id dwc3_meson_g12a_ids[] = {
  369. { .compatible = "amlogic,meson-g12a-usb-ctrl" },
  370. { }
  371. };
  372. U_BOOT_DRIVER(dwc3_generic_wrapper) = {
  373. .name = "dwc3-meson-g12a",
  374. .id = UCLASS_SIMPLE_BUS,
  375. .of_match = dwc3_meson_g12a_ids,
  376. .probe = dwc3_meson_g12a_probe,
  377. .remove = dwc3_meson_g12a_remove,
  378. .platdata_auto_alloc_size = sizeof(struct dwc3_meson_g12a),
  379. };