g12a.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 - BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock-g12a.h>
  9. #include <asm/io.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <div64.h>
  15. #include <dt-bindings/clock/g12a-clkc.h>
  16. #include <linux/err.h>
  17. #include <linux/kernel.h>
  18. #include "clk_meson.h"
  19. /* This driver support only basic clock tree operations :
  20. * - Can calculate clock frequency on a limited tree
  21. * - Can Read muxes and basic dividers (0-based only)
  22. * - Can enable/disable gates with limited propagation
  23. * - Can reparent without propagation, only on muxes
  24. * - Can set rates without reparenting
  25. * This driver is adapted to what is actually supported by U-Boot
  26. */
  27. /* Only the clocks ids we don't want to expose, such as the internal muxes
  28. * and dividers of composite clocks, will remain defined here.
  29. */
  30. #define CLKID_MPEG_SEL 8
  31. #define CLKID_MPEG_DIV 9
  32. #define CLKID_SD_EMMC_A_CLK0_SEL 63
  33. #define CLKID_SD_EMMC_A_CLK0_DIV 64
  34. #define CLKID_SD_EMMC_B_CLK0_SEL 65
  35. #define CLKID_SD_EMMC_B_CLK0_DIV 66
  36. #define CLKID_SD_EMMC_C_CLK0_SEL 67
  37. #define CLKID_SD_EMMC_C_CLK0_DIV 68
  38. #define CLKID_MPLL0_DIV 69
  39. #define CLKID_MPLL1_DIV 70
  40. #define CLKID_MPLL2_DIV 71
  41. #define CLKID_MPLL3_DIV 72
  42. #define CLKID_MPLL_PREDIV 73
  43. #define CLKID_FCLK_DIV2_DIV 75
  44. #define CLKID_FCLK_DIV3_DIV 76
  45. #define CLKID_FCLK_DIV4_DIV 77
  46. #define CLKID_FCLK_DIV5_DIV 78
  47. #define CLKID_FCLK_DIV7_DIV 79
  48. #define CLKID_FCLK_DIV2P5_DIV 100
  49. #define CLKID_FIXED_PLL_DCO 101
  50. #define CLKID_SYS_PLL_DCO 102
  51. #define CLKID_GP0_PLL_DCO 103
  52. #define CLKID_HIFI_PLL_DCO 104
  53. #define CLKID_VPU_0_DIV 111
  54. #define CLKID_VPU_1_DIV 114
  55. #define CLKID_VAPB_0_DIV 118
  56. #define CLKID_VAPB_1_DIV 121
  57. #define CLKID_HDMI_PLL_DCO 125
  58. #define CLKID_HDMI_PLL_OD 126
  59. #define CLKID_HDMI_PLL_OD2 127
  60. #define CLKID_VID_PLL_SEL 130
  61. #define CLKID_VID_PLL_DIV 131
  62. #define CLKID_VCLK_SEL 132
  63. #define CLKID_VCLK2_SEL 133
  64. #define CLKID_VCLK_INPUT 134
  65. #define CLKID_VCLK2_INPUT 135
  66. #define CLKID_VCLK_DIV 136
  67. #define CLKID_VCLK2_DIV 137
  68. #define CLKID_VCLK_DIV2_EN 140
  69. #define CLKID_VCLK_DIV4_EN 141
  70. #define CLKID_VCLK_DIV6_EN 142
  71. #define CLKID_VCLK_DIV12_EN 143
  72. #define CLKID_VCLK2_DIV2_EN 144
  73. #define CLKID_VCLK2_DIV4_EN 145
  74. #define CLKID_VCLK2_DIV6_EN 146
  75. #define CLKID_VCLK2_DIV12_EN 147
  76. #define CLKID_CTS_ENCI_SEL 158
  77. #define CLKID_CTS_ENCP_SEL 159
  78. #define CLKID_CTS_VDAC_SEL 160
  79. #define CLKID_HDMI_TX_SEL 161
  80. #define CLKID_HDMI_SEL 166
  81. #define CLKID_HDMI_DIV 167
  82. #define CLKID_MALI_0_DIV 170
  83. #define CLKID_MALI_1_DIV 173
  84. #define CLKID_XTAL 0x10000000
  85. #define XTAL_RATE 24000000
  86. struct meson_clk {
  87. struct regmap *map;
  88. };
  89. static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
  90. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  91. ulong current_rate);
  92. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  93. unsigned long parent_id);
  94. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
  95. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  96. ulong rate, ulong current_rate);
  97. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
  98. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  99. #define NUM_CLKS 178
  100. static struct meson_gate gates[NUM_CLKS] = {
  101. /* Everything Else (EE) domain gates */
  102. MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
  103. MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  104. MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  105. MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
  106. MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 4),
  107. MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
  108. MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
  109. MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
  110. MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
  111. MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
  112. MESON_GATE(CLKID_HTX_PCLK, HHI_GCLK_MPEG2, 4),
  113. MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
  114. MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
  115. /* Peripheral Gates */
  116. MESON_GATE(CLKID_FCLK_DIV2, HHI_FIX_PLL_CNTL1, 24),
  117. MESON_GATE(CLKID_FCLK_DIV3, HHI_FIX_PLL_CNTL1, 20),
  118. MESON_GATE(CLKID_FCLK_DIV4, HHI_FIX_PLL_CNTL1, 21),
  119. MESON_GATE(CLKID_FCLK_DIV5, HHI_FIX_PLL_CNTL1, 22),
  120. MESON_GATE(CLKID_FCLK_DIV7, HHI_FIX_PLL_CNTL1, 23),
  121. MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
  122. MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
  123. MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
  124. MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
  125. MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
  126. MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
  127. MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
  128. MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
  129. MESON_GATE(CLKID_HDMI, HHI_HDMI_CLK_CNTL, 8),
  130. };
  131. static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
  132. {
  133. struct meson_clk *priv = dev_get_priv(clk->dev);
  134. struct meson_gate *gate;
  135. debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
  136. /* Propagate through muxes */
  137. switch (id) {
  138. case CLKID_VPU:
  139. return meson_set_gate_by_id(clk,
  140. meson_mux_get_parent(clk, CLKID_VPU), on);
  141. case CLKID_VAPB_SEL:
  142. return meson_set_gate_by_id(clk,
  143. meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
  144. }
  145. if (id >= ARRAY_SIZE(gates))
  146. return -ENOENT;
  147. gate = &gates[id];
  148. if (gate->reg == 0)
  149. return 0;
  150. debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
  151. regmap_update_bits(priv->map, gate->reg,
  152. BIT(gate->bit), on ? BIT(gate->bit) : 0);
  153. /* Propagate to next gate(s) */
  154. switch (id) {
  155. case CLKID_VAPB:
  156. return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
  157. case CLKID_VAPB_0:
  158. return meson_set_gate_by_id(clk,
  159. meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
  160. case CLKID_VAPB_1:
  161. return meson_set_gate_by_id(clk,
  162. meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
  163. case CLKID_VPU_0:
  164. return meson_set_gate_by_id(clk,
  165. meson_mux_get_parent(clk, CLKID_VPU_0_SEL), on);
  166. case CLKID_VPU_1:
  167. return meson_set_gate_by_id(clk,
  168. meson_mux_get_parent(clk, CLKID_VPU_1_SEL), on);
  169. }
  170. return 0;
  171. }
  172. static int meson_clk_enable(struct clk *clk)
  173. {
  174. return meson_set_gate_by_id(clk, clk->id, true);
  175. }
  176. static int meson_clk_disable(struct clk *clk)
  177. {
  178. return meson_set_gate_by_id(clk, clk->id, false);
  179. }
  180. static struct parm meson_vpu_0_div_parm = {
  181. HHI_VPU_CLK_CNTL, 0, 7,
  182. };
  183. int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
  184. static struct parm meson_vpu_1_div_parm = {
  185. HHI_VPU_CLK_CNTL, 16, 7,
  186. };
  187. int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
  188. static struct parm meson_vapb_0_div_parm = {
  189. HHI_VAPBCLK_CNTL, 0, 7,
  190. };
  191. int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
  192. static struct parm meson_vapb_1_div_parm = {
  193. HHI_VAPBCLK_CNTL, 16, 7,
  194. };
  195. int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
  196. static struct parm meson_hdmi_div_parm = {
  197. HHI_HDMI_CLK_CNTL, 0, 7,
  198. };
  199. int meson_hdmi_div_parent = CLKID_HDMI_SEL;
  200. static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
  201. {
  202. struct meson_clk *priv = dev_get_priv(clk->dev);
  203. unsigned int rate, parent_rate;
  204. struct parm *parm;
  205. int parent;
  206. uint reg;
  207. switch (id) {
  208. case CLKID_VPU_0_DIV:
  209. parm = &meson_vpu_0_div_parm;
  210. parent = meson_vpu_0_div_parent;
  211. break;
  212. case CLKID_VPU_1_DIV:
  213. parm = &meson_vpu_1_div_parm;
  214. parent = meson_vpu_1_div_parent;
  215. break;
  216. case CLKID_VAPB_0_DIV:
  217. parm = &meson_vapb_0_div_parm;
  218. parent = meson_vapb_0_div_parent;
  219. break;
  220. case CLKID_VAPB_1_DIV:
  221. parm = &meson_vapb_1_div_parm;
  222. parent = meson_vapb_1_div_parent;
  223. break;
  224. case CLKID_HDMI_DIV:
  225. parm = &meson_hdmi_div_parm;
  226. parent = meson_hdmi_div_parent;
  227. break;
  228. default:
  229. return -ENOENT;
  230. }
  231. regmap_read(priv->map, parm->reg_off, &reg);
  232. reg = PARM_GET(parm->width, parm->shift, reg);
  233. debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
  234. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  235. if (IS_ERR_VALUE(parent_rate))
  236. return parent_rate;
  237. debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
  238. rate = parent_rate / (reg + 1);
  239. debug("%s: rate of %ld is %d\n", __func__, id, rate);
  240. return rate;
  241. }
  242. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  243. ulong current_rate)
  244. {
  245. struct meson_clk *priv = dev_get_priv(clk->dev);
  246. unsigned int new_div = -EINVAL;
  247. unsigned long parent_rate;
  248. struct parm *parm;
  249. int parent;
  250. int ret;
  251. if (current_rate == rate)
  252. return 0;
  253. debug("%s: setting rate of %ld from %ld to %ld\n",
  254. __func__, id, current_rate, rate);
  255. switch (id) {
  256. case CLKID_VPU_0_DIV:
  257. parm = &meson_vpu_0_div_parm;
  258. parent = meson_vpu_0_div_parent;
  259. break;
  260. case CLKID_VPU_1_DIV:
  261. parm = &meson_vpu_1_div_parm;
  262. parent = meson_vpu_1_div_parent;
  263. break;
  264. case CLKID_VAPB_0_DIV:
  265. parm = &meson_vapb_0_div_parm;
  266. parent = meson_vapb_0_div_parent;
  267. break;
  268. case CLKID_VAPB_1_DIV:
  269. parm = &meson_vapb_1_div_parm;
  270. parent = meson_vapb_1_div_parent;
  271. break;
  272. case CLKID_HDMI_DIV:
  273. parm = &meson_hdmi_div_parm;
  274. parent = meson_hdmi_div_parent;
  275. break;
  276. default:
  277. return -ENOENT;
  278. }
  279. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  280. if (IS_ERR_VALUE(parent_rate))
  281. return parent_rate;
  282. debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
  283. /* If can't divide, set parent instead */
  284. if (!parent_rate || rate > parent_rate)
  285. return meson_clk_set_rate_by_id(clk, parent, rate,
  286. current_rate);
  287. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  288. debug("%s: new div of %ld is %d\n", __func__, id, new_div);
  289. /* If overflow, try to set parent rate and retry */
  290. if (!new_div || new_div > (1 << parm->width)) {
  291. ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
  292. if (IS_ERR_VALUE(ret))
  293. return ret;
  294. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  295. if (IS_ERR_VALUE(parent_rate))
  296. return parent_rate;
  297. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  298. debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
  299. if (!new_div || new_div > (1 << parm->width))
  300. return -EINVAL;
  301. }
  302. debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
  303. regmap_update_bits(priv->map, parm->reg_off,
  304. SETPMASK(parm->width, parm->shift),
  305. (new_div - 1) << parm->shift);
  306. debug("%s: new rate of %ld is %ld\n",
  307. __func__, id, meson_div_get_rate(clk, id));
  308. return 0;
  309. }
  310. static struct parm meson_vpu_mux_parm = {
  311. HHI_VPU_CLK_CNTL, 31, 1,
  312. };
  313. int meson_vpu_mux_parents[] = {
  314. CLKID_VPU_0,
  315. CLKID_VPU_1,
  316. };
  317. static struct parm meson_vpu_0_mux_parm = {
  318. HHI_VPU_CLK_CNTL, 9, 3,
  319. };
  320. static struct parm meson_vpu_1_mux_parm = {
  321. HHI_VPU_CLK_CNTL, 25, 3,
  322. };
  323. static int meson_vpu_0_1_mux_parents[] = {
  324. CLKID_FCLK_DIV3,
  325. CLKID_FCLK_DIV4,
  326. CLKID_FCLK_DIV5,
  327. CLKID_FCLK_DIV7,
  328. -ENOENT,
  329. -ENOENT,
  330. -ENOENT,
  331. -ENOENT,
  332. };
  333. static struct parm meson_vapb_sel_mux_parm = {
  334. HHI_VAPBCLK_CNTL, 31, 1,
  335. };
  336. int meson_vapb_sel_mux_parents[] = {
  337. CLKID_VAPB_0,
  338. CLKID_VAPB_1,
  339. };
  340. static struct parm meson_vapb_0_mux_parm = {
  341. HHI_VAPBCLK_CNTL, 9, 2,
  342. };
  343. static struct parm meson_vapb_1_mux_parm = {
  344. HHI_VAPBCLK_CNTL, 25, 2,
  345. };
  346. static int meson_vapb_0_1_mux_parents[] = {
  347. CLKID_FCLK_DIV4,
  348. CLKID_FCLK_DIV3,
  349. CLKID_FCLK_DIV5,
  350. CLKID_FCLK_DIV7,
  351. };
  352. static struct parm meson_hdmi_mux_parm = {
  353. HHI_HDMI_CLK_CNTL, 9, 2,
  354. };
  355. static int meson_hdmi_mux_parents[] = {
  356. CLKID_XTAL,
  357. CLKID_FCLK_DIV4,
  358. CLKID_FCLK_DIV3,
  359. CLKID_FCLK_DIV5,
  360. };
  361. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
  362. {
  363. struct meson_clk *priv = dev_get_priv(clk->dev);
  364. struct parm *parm;
  365. int *parents;
  366. uint reg;
  367. switch (id) {
  368. case CLKID_VPU:
  369. parm = &meson_vpu_mux_parm;
  370. parents = meson_vpu_mux_parents;
  371. break;
  372. case CLKID_VPU_0_SEL:
  373. parm = &meson_vpu_0_mux_parm;
  374. parents = meson_vpu_0_1_mux_parents;
  375. break;
  376. case CLKID_VPU_1_SEL:
  377. parm = &meson_vpu_1_mux_parm;
  378. parents = meson_vpu_0_1_mux_parents;
  379. break;
  380. case CLKID_VAPB_SEL:
  381. parm = &meson_vapb_sel_mux_parm;
  382. parents = meson_vapb_sel_mux_parents;
  383. break;
  384. case CLKID_VAPB_0_SEL:
  385. parm = &meson_vapb_0_mux_parm;
  386. parents = meson_vapb_0_1_mux_parents;
  387. break;
  388. case CLKID_VAPB_1_SEL:
  389. parm = &meson_vapb_1_mux_parm;
  390. parents = meson_vapb_0_1_mux_parents;
  391. break;
  392. case CLKID_HDMI_SEL:
  393. parm = &meson_hdmi_mux_parm;
  394. parents = meson_hdmi_mux_parents;
  395. break;
  396. default:
  397. return -ENOENT;
  398. }
  399. regmap_read(priv->map, parm->reg_off, &reg);
  400. reg = PARM_GET(parm->width, parm->shift, reg);
  401. debug("%s: parent of %ld is %d (%d)\n",
  402. __func__, id, parents[reg], reg);
  403. return parents[reg];
  404. }
  405. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  406. unsigned long parent_id)
  407. {
  408. unsigned long cur_parent = meson_mux_get_parent(clk, id);
  409. struct meson_clk *priv = dev_get_priv(clk->dev);
  410. unsigned int new_index = -EINVAL;
  411. struct parm *parm;
  412. int *parents;
  413. int i;
  414. if (IS_ERR_VALUE(cur_parent))
  415. return cur_parent;
  416. debug("%s: setting parent of %ld from %ld to %ld\n",
  417. __func__, id, cur_parent, parent_id);
  418. if (cur_parent == parent_id)
  419. return 0;
  420. switch (id) {
  421. case CLKID_VPU:
  422. parm = &meson_vpu_mux_parm;
  423. parents = meson_vpu_mux_parents;
  424. break;
  425. case CLKID_VPU_0_SEL:
  426. parm = &meson_vpu_0_mux_parm;
  427. parents = meson_vpu_0_1_mux_parents;
  428. break;
  429. case CLKID_VPU_1_SEL:
  430. parm = &meson_vpu_1_mux_parm;
  431. parents = meson_vpu_0_1_mux_parents;
  432. break;
  433. case CLKID_VAPB_SEL:
  434. parm = &meson_vapb_sel_mux_parm;
  435. parents = meson_vapb_sel_mux_parents;
  436. break;
  437. case CLKID_VAPB_0_SEL:
  438. parm = &meson_vapb_0_mux_parm;
  439. parents = meson_vapb_0_1_mux_parents;
  440. break;
  441. case CLKID_VAPB_1_SEL:
  442. parm = &meson_vapb_1_mux_parm;
  443. parents = meson_vapb_0_1_mux_parents;
  444. break;
  445. case CLKID_HDMI_SEL:
  446. parm = &meson_hdmi_mux_parm;
  447. parents = meson_hdmi_mux_parents;
  448. break;
  449. default:
  450. /* Not a mux */
  451. return -ENOENT;
  452. }
  453. for (i = 0 ; i < (1 << parm->width) ; ++i) {
  454. if (parents[i] == parent_id)
  455. new_index = i;
  456. }
  457. if (IS_ERR_VALUE(new_index))
  458. return new_index;
  459. debug("%s: new index of %ld is %d\n", __func__, id, new_index);
  460. regmap_update_bits(priv->map, parm->reg_off,
  461. SETPMASK(parm->width, parm->shift),
  462. new_index << parm->shift);
  463. debug("%s: new parent of %ld is %ld\n",
  464. __func__, id, meson_mux_get_parent(clk, id));
  465. return 0;
  466. }
  467. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
  468. {
  469. int parent = meson_mux_get_parent(clk, id);
  470. if (IS_ERR_VALUE(parent))
  471. return parent;
  472. return meson_clk_get_rate_by_id(clk, parent);
  473. }
  474. static unsigned long meson_clk81_get_rate(struct clk *clk)
  475. {
  476. struct meson_clk *priv = dev_get_priv(clk->dev);
  477. unsigned long parent_rate;
  478. uint reg;
  479. int parents[] = {
  480. CLKID_XTAL,
  481. -1,
  482. CLKID_FCLK_DIV7,
  483. CLKID_MPLL1,
  484. CLKID_MPLL2,
  485. CLKID_FCLK_DIV4,
  486. CLKID_FCLK_DIV3,
  487. CLKID_FCLK_DIV5
  488. };
  489. /* mux */
  490. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  491. reg = (reg >> 12) & 7;
  492. switch (reg) {
  493. case 1:
  494. return -ENOENT;
  495. default:
  496. parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
  497. }
  498. /* divider */
  499. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  500. reg = reg & ((1 << 7) - 1);
  501. return parent_rate / reg;
  502. }
  503. static long mpll_rate_from_params(unsigned long parent_rate,
  504. unsigned long sdm,
  505. unsigned long n2)
  506. {
  507. unsigned long divisor = (SDM_DEN * n2) + sdm;
  508. if (n2 < N2_MIN)
  509. return -EINVAL;
  510. return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  511. }
  512. static struct parm meson_mpll0_parm[2] = {
  513. {HHI_MPLL_CNTL1, 0, 14}, /* psdm */
  514. {HHI_MPLL_CNTL1, 20, 9}, /* pn2 */
  515. };
  516. static struct parm meson_mpll1_parm[2] = {
  517. {HHI_MPLL_CNTL3, 0, 14}, /* psdm */
  518. {HHI_MPLL_CNTL3, 20, 9}, /* pn2 */
  519. };
  520. static struct parm meson_mpll2_parm[2] = {
  521. {HHI_MPLL_CNTL5, 0, 14}, /* psdm */
  522. {HHI_MPLL_CNTL5, 20, 9}, /* pn2 */
  523. };
  524. /*
  525. * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  526. * scaling capabilities. MPLL rates are calculated as:
  527. *
  528. * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  529. */
  530. static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
  531. {
  532. struct meson_clk *priv = dev_get_priv(clk->dev);
  533. struct parm *psdm, *pn2;
  534. unsigned long sdm, n2;
  535. unsigned long parent_rate;
  536. uint reg;
  537. switch (id) {
  538. case CLKID_MPLL0:
  539. psdm = &meson_mpll0_parm[0];
  540. pn2 = &meson_mpll0_parm[1];
  541. break;
  542. case CLKID_MPLL1:
  543. psdm = &meson_mpll1_parm[0];
  544. pn2 = &meson_mpll1_parm[1];
  545. break;
  546. case CLKID_MPLL2:
  547. psdm = &meson_mpll2_parm[0];
  548. pn2 = &meson_mpll2_parm[1];
  549. break;
  550. default:
  551. return -ENOENT;
  552. }
  553. parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
  554. if (IS_ERR_VALUE(parent_rate))
  555. return parent_rate;
  556. regmap_read(priv->map, psdm->reg_off, &reg);
  557. sdm = PARM_GET(psdm->width, psdm->shift, reg);
  558. regmap_read(priv->map, pn2->reg_off, &reg);
  559. n2 = PARM_GET(pn2->width, pn2->shift, reg);
  560. return mpll_rate_from_params(parent_rate, sdm, n2);
  561. }
  562. static struct parm meson_fixed_pll_parm[4] = {
  563. {HHI_FIX_PLL_CNTL0, 0, 9}, /* pm */
  564. {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
  565. {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
  566. {HHI_FIX_PLL_CNTL1, 0, 17}, /* pfrac */
  567. };
  568. static struct parm meson_sys_pll_parm[3] = {
  569. {HHI_SYS_PLL_CNTL0, 0, 9}, /* pm */
  570. {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
  571. {HHI_SYS_PLL_CNTL0, 16, 3}, /* pod */
  572. };
  573. static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
  574. {
  575. struct meson_clk *priv = dev_get_priv(clk->dev);
  576. struct parm *pm, *pn, *pod, *pfrac = NULL;
  577. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  578. u16 n, m, od, frac;
  579. ulong rate;
  580. uint reg;
  581. /*
  582. * FIXME: Between the unit conversion and the missing frac, we know
  583. * rate will be slightly off ...
  584. */
  585. switch (id) {
  586. case CLKID_FIXED_PLL:
  587. pm = &meson_fixed_pll_parm[0];
  588. pn = &meson_fixed_pll_parm[1];
  589. pod = &meson_fixed_pll_parm[2];
  590. pfrac = &meson_fixed_pll_parm[3];
  591. break;
  592. case CLKID_SYS_PLL:
  593. pm = &meson_sys_pll_parm[0];
  594. pn = &meson_sys_pll_parm[1];
  595. pod = &meson_sys_pll_parm[2];
  596. break;
  597. default:
  598. return -ENOENT;
  599. }
  600. regmap_read(priv->map, pn->reg_off, &reg);
  601. n = PARM_GET(pn->width, pn->shift, reg);
  602. regmap_read(priv->map, pm->reg_off, &reg);
  603. m = PARM_GET(pm->width, pm->shift, reg);
  604. regmap_read(priv->map, pod->reg_off, &reg);
  605. od = PARM_GET(pod->width, pod->shift, reg);
  606. rate = parent_rate_mhz * m;
  607. if (pfrac) {
  608. ulong frac_rate;
  609. regmap_read(priv->map, pfrac->reg_off, &reg);
  610. frac = PARM_GET(pfrac->width - 1, pfrac->shift, reg);
  611. frac_rate = DIV_ROUND_UP_ULL((u64)parent_rate_mhz * frac,
  612. 1 << (pfrac->width - 2));
  613. if (frac & BIT(pfrac->width - 1))
  614. rate -= frac_rate;
  615. else
  616. rate += frac_rate;
  617. }
  618. return (DIV_ROUND_UP_ULL(rate, n) >> od) * 1000000;
  619. }
  620. static struct parm meson_pcie_pll_parm[3] = {
  621. {HHI_PCIE_PLL_CNTL0, 0, 8}, /* pm */
  622. {HHI_PCIE_PLL_CNTL0, 10, 5}, /* pn */
  623. {HHI_PCIE_PLL_CNTL0, 16, 5}, /* pod */
  624. };
  625. static ulong meson_pcie_pll_get_rate(struct clk *clk)
  626. {
  627. struct meson_clk *priv = dev_get_priv(clk->dev);
  628. struct parm *pm, *pn, *pod;
  629. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  630. u16 n, m, od;
  631. uint reg;
  632. pm = &meson_pcie_pll_parm[0];
  633. pn = &meson_pcie_pll_parm[1];
  634. pod = &meson_pcie_pll_parm[2];
  635. regmap_read(priv->map, pn->reg_off, &reg);
  636. n = PARM_GET(pn->width, pn->shift, reg);
  637. regmap_read(priv->map, pm->reg_off, &reg);
  638. m = PARM_GET(pm->width, pm->shift, reg);
  639. regmap_read(priv->map, pod->reg_off, &reg);
  640. od = PARM_GET(pod->width, pod->shift, reg);
  641. return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
  642. }
  643. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
  644. {
  645. ulong rate;
  646. switch (id) {
  647. case CLKID_XTAL:
  648. rate = XTAL_RATE;
  649. break;
  650. case CLKID_FIXED_PLL:
  651. case CLKID_SYS_PLL:
  652. rate = meson_pll_get_rate(clk, id);
  653. break;
  654. case CLKID_FCLK_DIV2:
  655. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
  656. break;
  657. case CLKID_FCLK_DIV3:
  658. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
  659. break;
  660. case CLKID_FCLK_DIV4:
  661. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
  662. break;
  663. case CLKID_FCLK_DIV5:
  664. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
  665. break;
  666. case CLKID_FCLK_DIV7:
  667. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
  668. break;
  669. case CLKID_MPLL0:
  670. case CLKID_MPLL1:
  671. case CLKID_MPLL2:
  672. rate = meson_mpll_get_rate(clk, id);
  673. break;
  674. case CLKID_CLK81:
  675. rate = meson_clk81_get_rate(clk);
  676. break;
  677. case CLKID_PCIE_PLL:
  678. rate = meson_pcie_pll_get_rate(clk);
  679. break;
  680. case CLKID_VPU_0:
  681. rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
  682. break;
  683. case CLKID_VPU_1:
  684. rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
  685. break;
  686. case CLKID_VAPB:
  687. rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
  688. break;
  689. case CLKID_VAPB_0:
  690. rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
  691. break;
  692. case CLKID_VAPB_1:
  693. rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
  694. break;
  695. case CLKID_HDMI:
  696. rate = meson_div_get_rate(clk, CLKID_HDMI_DIV);
  697. break;
  698. case CLKID_VPU_0_DIV:
  699. case CLKID_VPU_1_DIV:
  700. case CLKID_VAPB_0_DIV:
  701. case CLKID_VAPB_1_DIV:
  702. case CLKID_HDMI_DIV:
  703. rate = meson_div_get_rate(clk, id);
  704. break;
  705. case CLKID_VPU:
  706. case CLKID_VPU_0_SEL:
  707. case CLKID_VPU_1_SEL:
  708. case CLKID_VAPB_SEL:
  709. case CLKID_VAPB_0_SEL:
  710. case CLKID_VAPB_1_SEL:
  711. case CLKID_HDMI_SEL:
  712. rate = meson_mux_get_rate(clk, id);
  713. break;
  714. default:
  715. if (gates[id].reg != 0) {
  716. /* a clock gate */
  717. rate = meson_clk81_get_rate(clk);
  718. break;
  719. }
  720. return -ENOENT;
  721. }
  722. debug("clock %lu has rate %lu\n", id, rate);
  723. return rate;
  724. }
  725. static ulong meson_clk_get_rate(struct clk *clk)
  726. {
  727. return meson_clk_get_rate_by_id(clk, clk->id);
  728. }
  729. static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)
  730. {
  731. struct meson_clk *priv = dev_get_priv(clk->dev);
  732. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
  733. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
  734. regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
  735. regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
  736. regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
  737. regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
  738. regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
  739. regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
  740. udelay(20);
  741. regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
  742. udelay(10);
  743. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
  744. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
  745. udelay(10);
  746. regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
  747. regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
  748. 0x1f << 16, 9 << 16);
  749. return 100000000;
  750. }
  751. static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
  752. {
  753. return meson_mux_set_parent(clk, clk->id, parent->id);
  754. }
  755. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  756. ulong rate, ulong current_rate)
  757. {
  758. if (current_rate == rate)
  759. return 0;
  760. switch (id) {
  761. /* Fixed clocks */
  762. case CLKID_FIXED_PLL:
  763. case CLKID_SYS_PLL:
  764. case CLKID_FCLK_DIV2:
  765. case CLKID_FCLK_DIV3:
  766. case CLKID_FCLK_DIV4:
  767. case CLKID_FCLK_DIV5:
  768. case CLKID_FCLK_DIV7:
  769. case CLKID_MPLL0:
  770. case CLKID_MPLL1:
  771. case CLKID_MPLL2:
  772. case CLKID_CLK81:
  773. if (current_rate != rate)
  774. return -EINVAL;
  775. case CLKID_PCIE_PLL:
  776. return meson_pcie_pll_set_rate(clk, rate);
  777. return 0;
  778. case CLKID_VPU:
  779. return meson_clk_set_rate_by_id(clk,
  780. meson_mux_get_parent(clk, CLKID_VPU), rate,
  781. current_rate);
  782. case CLKID_VAPB:
  783. case CLKID_VAPB_SEL:
  784. return meson_clk_set_rate_by_id(clk,
  785. meson_mux_get_parent(clk, CLKID_VAPB_SEL),
  786. rate, current_rate);
  787. case CLKID_VPU_0:
  788. return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
  789. current_rate);
  790. case CLKID_VPU_1:
  791. return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
  792. current_rate);
  793. case CLKID_VAPB_0:
  794. return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
  795. current_rate);
  796. case CLKID_VAPB_1:
  797. return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
  798. current_rate);
  799. case CLKID_VPU_0_DIV:
  800. case CLKID_VPU_1_DIV:
  801. case CLKID_VAPB_0_DIV:
  802. case CLKID_VAPB_1_DIV:
  803. case CLKID_HDMI_DIV:
  804. return meson_div_set_rate(clk, id, rate, current_rate);
  805. case CLKID_HDMI:
  806. return meson_clk_set_rate_by_id(clk, CLKID_HDMI_DIV,
  807. rate, current_rate);
  808. default:
  809. return -ENOENT;
  810. }
  811. return -EINVAL;
  812. }
  813. static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
  814. {
  815. ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
  816. int ret;
  817. if (IS_ERR_VALUE(current_rate))
  818. return current_rate;
  819. debug("%s: setting rate of %ld from %ld to %ld\n",
  820. __func__, clk->id, current_rate, rate);
  821. ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
  822. if (IS_ERR_VALUE(ret))
  823. return ret;
  824. debug("clock %lu has new rate %lu\n", clk->id,
  825. meson_clk_get_rate_by_id(clk, clk->id));
  826. return 0;
  827. }
  828. static int meson_clk_probe(struct udevice *dev)
  829. {
  830. struct meson_clk *priv = dev_get_priv(dev);
  831. priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
  832. if (IS_ERR(priv->map))
  833. return PTR_ERR(priv->map);
  834. /*
  835. * Depending on the boot src, the state of the MMC clock might
  836. * be different. Reset it to make sure we won't get stuck
  837. */
  838. regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
  839. regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
  840. debug("meson-clk-g12a: probed\n");
  841. return 0;
  842. }
  843. static struct clk_ops meson_clk_ops = {
  844. .disable = meson_clk_disable,
  845. .enable = meson_clk_enable,
  846. .get_rate = meson_clk_get_rate,
  847. .set_parent = meson_clk_set_parent,
  848. .set_rate = meson_clk_set_rate,
  849. };
  850. static const struct udevice_id meson_clk_ids[] = {
  851. { .compatible = "amlogic,g12a-clkc" },
  852. { .compatible = "amlogic,g12b-clkc" },
  853. { .compatible = "amlogic,sm1-clkc" },
  854. { }
  855. };
  856. U_BOOT_DRIVER(meson_clk_g12a) = {
  857. .name = "meson_clk_g12a",
  858. .id = UCLASS_CLK,
  859. .of_match = meson_clk_ids,
  860. .priv_auto_alloc_size = sizeof(struct meson_clk),
  861. .ops = &meson_clk_ops,
  862. .probe = meson_clk_probe,
  863. };