meson-sm1-khadas-vim3l.dts 2.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2019 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. /dts-v1/;
  7. #include "meson-sm1.dtsi"
  8. #include "meson-khadas-vim3.dtsi"
  9. / {
  10. compatible = "khadas,vim3l", "amlogic,sm1";
  11. model = "Khadas VIM3L";
  12. vddcpu: regulator-vddcpu {
  13. /*
  14. * Silergy SY8030DEC Regulator.
  15. */
  16. compatible = "pwm-regulator";
  17. regulator-name = "VDDCPU";
  18. regulator-min-microvolt = <690000>;
  19. regulator-max-microvolt = <1050000>;
  20. vin-supply = <&vsys_3v3>;
  21. pwms = <&pwm_AO_cd 1 1250 0>;
  22. pwm-dutycycle-range = <100 0>;
  23. regulator-boot-on;
  24. regulator-always-on;
  25. };
  26. };
  27. &cpu0 {
  28. cpu-supply = <&vddcpu>;
  29. operating-points-v2 = <&cpu_opp_table>;
  30. clocks = <&clkc CLKID_CPU_CLK>;
  31. clock-latency = <50000>;
  32. };
  33. &cpu1 {
  34. cpu-supply = <&vddcpu>;
  35. operating-points-v2 = <&cpu_opp_table>;
  36. clocks = <&clkc CLKID_CPU1_CLK>;
  37. clock-latency = <50000>;
  38. };
  39. &cpu2 {
  40. cpu-supply = <&vddcpu>;
  41. operating-points-v2 = <&cpu_opp_table>;
  42. clocks = <&clkc CLKID_CPU2_CLK>;
  43. clock-latency = <50000>;
  44. };
  45. &cpu3 {
  46. cpu-supply = <&vddcpu>;
  47. operating-points-v2 = <&cpu_opp_table>;
  48. clocks = <&clkc CLKID_CPU3_CLK>;
  49. clock-latency = <50000>;
  50. };
  51. &pwm_AO_cd {
  52. pinctrl-0 = <&pwm_ao_d_e_pins>;
  53. pinctrl-names = "default";
  54. clocks = <&xtal>;
  55. clock-names = "clkin1";
  56. status = "okay";
  57. };
  58. /*
  59. * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
  60. * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
  61. * an USB3.0 Type A connector and a M.2 Key M slot.
  62. * The PHY driving these differential lines is shared between
  63. * the USB3.0 controller and the PCIe Controller, thus only
  64. * a single controller can use it.
  65. * If the MCU is configured to mux the PCIe/USB3.0 differential lines
  66. * to the M.2 Key M slot, uncomment the following block to disable
  67. * USB3.0 from the USB Complex and enable the PCIe controller.
  68. * The End User is not expected to uncomment the following except for
  69. * testing purposes, but instead rely on the firmware/bootloader to
  70. * update these nodes accordingly if PCIe mode is selected by the MCU.
  71. */
  72. /*
  73. &pcie {
  74. status = "okay";
  75. };
  76. &usb {
  77. phys = <&usb2_phy0>, <&usb2_phy1>;
  78. phy-names = "usb2-phy0", "usb2-phy1";
  79. };
  80. */