meson-gx.dtsi 15 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2016 Andreas Färber
  4. *
  5. * Copyright (c) 2016 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. *
  8. * Copyright (c) 2016 Endless Computers, Inc.
  9. * Author: Carlo Caione <carlo@endlessm.com>
  10. */
  11. #include <dt-bindings/gpio/gpio.h>
  12. #include <dt-bindings/interrupt-controller/irq.h>
  13. #include <dt-bindings/interrupt-controller/arm-gic.h>
  14. #include <dt-bindings/thermal/thermal.h>
  15. / {
  16. interrupt-parent = <&gic>;
  17. #address-cells = <2>;
  18. #size-cells = <2>;
  19. reserved-memory {
  20. #address-cells = <2>;
  21. #size-cells = <2>;
  22. ranges;
  23. /* 16 MiB reserved for Hardware ROM Firmware */
  24. hwrom_reserved: hwrom@0 {
  25. reg = <0x0 0x0 0x0 0x1000000>;
  26. no-map;
  27. };
  28. /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
  29. secmon_reserved: secmon@10000000 {
  30. reg = <0x0 0x10000000 0x0 0x200000>;
  31. no-map;
  32. };
  33. /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  34. secmon_reserved_alt: secmon@5000000 {
  35. reg = <0x0 0x05000000 0x0 0x300000>;
  36. no-map;
  37. };
  38. linux,cma {
  39. compatible = "shared-dma-pool";
  40. reusable;
  41. size = <0x0 0x10000000>;
  42. alignment = <0x0 0x400000>;
  43. linux,cma-default;
  44. };
  45. };
  46. chosen {
  47. #address-cells = <2>;
  48. #size-cells = <2>;
  49. ranges;
  50. simplefb_cvbs: framebuffer-cvbs {
  51. compatible = "amlogic,simple-framebuffer",
  52. "simple-framebuffer";
  53. amlogic,pipeline = "vpu-cvbs";
  54. power-domains = <&pwrc_vpu>;
  55. status = "disabled";
  56. };
  57. simplefb_hdmi: framebuffer-hdmi {
  58. compatible = "amlogic,simple-framebuffer",
  59. "simple-framebuffer";
  60. amlogic,pipeline = "vpu-hdmi";
  61. power-domains = <&pwrc_vpu>;
  62. status = "disabled";
  63. };
  64. };
  65. cpus {
  66. #address-cells = <0x2>;
  67. #size-cells = <0x0>;
  68. cpu0: cpu@0 {
  69. device_type = "cpu";
  70. compatible = "arm,cortex-a53";
  71. reg = <0x0 0x0>;
  72. enable-method = "psci";
  73. next-level-cache = <&l2>;
  74. clocks = <&scpi_dvfs 0>;
  75. #cooling-cells = <2>;
  76. };
  77. cpu1: cpu@1 {
  78. device_type = "cpu";
  79. compatible = "arm,cortex-a53";
  80. reg = <0x0 0x1>;
  81. enable-method = "psci";
  82. next-level-cache = <&l2>;
  83. clocks = <&scpi_dvfs 0>;
  84. #cooling-cells = <2>;
  85. };
  86. cpu2: cpu@2 {
  87. device_type = "cpu";
  88. compatible = "arm,cortex-a53";
  89. reg = <0x0 0x2>;
  90. enable-method = "psci";
  91. next-level-cache = <&l2>;
  92. clocks = <&scpi_dvfs 0>;
  93. #cooling-cells = <2>;
  94. };
  95. cpu3: cpu@3 {
  96. device_type = "cpu";
  97. compatible = "arm,cortex-a53";
  98. reg = <0x0 0x3>;
  99. enable-method = "psci";
  100. next-level-cache = <&l2>;
  101. clocks = <&scpi_dvfs 0>;
  102. #cooling-cells = <2>;
  103. };
  104. l2: l2-cache0 {
  105. compatible = "cache";
  106. };
  107. };
  108. thermal-zones {
  109. cpu-thermal {
  110. polling-delay-passive = <250>; /* milliseconds */
  111. polling-delay = <1000>; /* milliseconds */
  112. thermal-sensors = <&scpi_sensors 0>;
  113. trips {
  114. cpu_passive: cpu-passive {
  115. temperature = <80000>; /* millicelsius */
  116. hysteresis = <2000>; /* millicelsius */
  117. type = "passive";
  118. };
  119. cpu_hot: cpu-hot {
  120. temperature = <90000>; /* millicelsius */
  121. hysteresis = <2000>; /* millicelsius */
  122. type = "hot";
  123. };
  124. cpu_critical: cpu-critical {
  125. temperature = <110000>; /* millicelsius */
  126. hysteresis = <2000>; /* millicelsius */
  127. type = "critical";
  128. };
  129. };
  130. cpu_cooling_maps: cooling-maps {
  131. map0 {
  132. trip = <&cpu_passive>;
  133. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  134. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  135. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  136. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  137. };
  138. map1 {
  139. trip = <&cpu_hot>;
  140. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  141. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  142. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  143. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  144. };
  145. };
  146. };
  147. };
  148. arm-pmu {
  149. compatible = "arm,cortex-a53-pmu";
  150. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  151. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  152. <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  153. <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  154. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  155. };
  156. psci {
  157. compatible = "arm,psci-0.2";
  158. method = "smc";
  159. };
  160. timer {
  161. compatible = "arm,armv8-timer";
  162. interrupts = <GIC_PPI 13
  163. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  164. <GIC_PPI 14
  165. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  166. <GIC_PPI 11
  167. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  168. <GIC_PPI 10
  169. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  170. };
  171. xtal: xtal-clk {
  172. compatible = "fixed-clock";
  173. clock-frequency = <24000000>;
  174. clock-output-names = "xtal";
  175. #clock-cells = <0>;
  176. };
  177. firmware {
  178. sm: secure-monitor {
  179. compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
  180. };
  181. };
  182. efuse: efuse {
  183. compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. read-only;
  187. secure-monitor = <&sm>;
  188. sn: sn@14 {
  189. reg = <0x14 0x10>;
  190. };
  191. eth_mac: eth_mac@34 {
  192. reg = <0x34 0x10>;
  193. };
  194. bid: bid@46 {
  195. reg = <0x46 0x30>;
  196. };
  197. };
  198. scpi {
  199. compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
  200. mboxes = <&mailbox 1 &mailbox 2>;
  201. shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
  202. scpi_clocks: clocks {
  203. compatible = "arm,scpi-clocks";
  204. scpi_dvfs: scpi_clocks@0 {
  205. compatible = "arm,scpi-dvfs-clocks";
  206. #clock-cells = <1>;
  207. clock-indices = <0>;
  208. clock-output-names = "vcpu";
  209. };
  210. };
  211. scpi_sensors: sensors {
  212. compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
  213. #thermal-sensor-cells = <1>;
  214. };
  215. };
  216. soc {
  217. compatible = "simple-bus";
  218. #address-cells = <2>;
  219. #size-cells = <2>;
  220. ranges;
  221. cbus: bus@c1100000 {
  222. compatible = "simple-bus";
  223. reg = <0x0 0xc1100000 0x0 0x100000>;
  224. #address-cells = <2>;
  225. #size-cells = <2>;
  226. ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
  227. gpio_intc: interrupt-controller@9880 {
  228. compatible = "amlogic,meson-gpio-intc";
  229. reg = <0x0 0x9880 0x0 0x10>;
  230. interrupt-controller;
  231. #interrupt-cells = <2>;
  232. amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
  233. status = "disabled";
  234. };
  235. reset: reset-controller@4404 {
  236. compatible = "amlogic,meson-gxbb-reset";
  237. reg = <0x0 0x04404 0x0 0x9c>;
  238. #reset-cells = <1>;
  239. };
  240. uart_A: serial@84c0 {
  241. compatible = "amlogic,meson-gx-uart";
  242. reg = <0x0 0x84c0 0x0 0x18>;
  243. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  244. status = "disabled";
  245. };
  246. uart_B: serial@84dc {
  247. compatible = "amlogic,meson-gx-uart";
  248. reg = <0x0 0x84dc 0x0 0x18>;
  249. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  250. status = "disabled";
  251. };
  252. i2c_A: i2c@8500 {
  253. compatible = "amlogic,meson-gxbb-i2c";
  254. reg = <0x0 0x08500 0x0 0x20>;
  255. interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
  256. #address-cells = <1>;
  257. #size-cells = <0>;
  258. status = "disabled";
  259. };
  260. pwm_ab: pwm@8550 {
  261. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  262. reg = <0x0 0x08550 0x0 0x10>;
  263. #pwm-cells = <3>;
  264. status = "disabled";
  265. };
  266. pwm_cd: pwm@8650 {
  267. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  268. reg = <0x0 0x08650 0x0 0x10>;
  269. #pwm-cells = <3>;
  270. status = "disabled";
  271. };
  272. saradc: adc@8680 {
  273. compatible = "amlogic,meson-saradc";
  274. reg = <0x0 0x8680 0x0 0x34>;
  275. #io-channel-cells = <1>;
  276. interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
  277. status = "disabled";
  278. };
  279. pwm_ef: pwm@86c0 {
  280. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  281. reg = <0x0 0x086c0 0x0 0x10>;
  282. #pwm-cells = <3>;
  283. status = "disabled";
  284. };
  285. uart_C: serial@8700 {
  286. compatible = "amlogic,meson-gx-uart";
  287. reg = <0x0 0x8700 0x0 0x18>;
  288. interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
  289. status = "disabled";
  290. };
  291. clock-measure@8758 {
  292. compatible = "amlogic,meson-gx-clk-measure";
  293. reg = <0x0 0x8758 0x0 0x10>;
  294. };
  295. i2c_B: i2c@87c0 {
  296. compatible = "amlogic,meson-gxbb-i2c";
  297. reg = <0x0 0x087c0 0x0 0x20>;
  298. interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
  299. #address-cells = <1>;
  300. #size-cells = <0>;
  301. status = "disabled";
  302. };
  303. i2c_C: i2c@87e0 {
  304. compatible = "amlogic,meson-gxbb-i2c";
  305. reg = <0x0 0x087e0 0x0 0x20>;
  306. interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
  307. #address-cells = <1>;
  308. #size-cells = <0>;
  309. status = "disabled";
  310. };
  311. spicc: spi@8d80 {
  312. compatible = "amlogic,meson-gx-spicc";
  313. reg = <0x0 0x08d80 0x0 0x80>;
  314. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  315. #address-cells = <1>;
  316. #size-cells = <0>;
  317. status = "disabled";
  318. };
  319. spifc: spi@8c80 {
  320. compatible = "amlogic,meson-gxbb-spifc";
  321. reg = <0x0 0x08c80 0x0 0x80>;
  322. #address-cells = <1>;
  323. #size-cells = <0>;
  324. status = "disabled";
  325. };
  326. watchdog@98d0 {
  327. compatible = "amlogic,meson-gxbb-wdt";
  328. reg = <0x0 0x098d0 0x0 0x10>;
  329. clocks = <&xtal>;
  330. };
  331. };
  332. gic: interrupt-controller@c4301000 {
  333. compatible = "arm,gic-400";
  334. reg = <0x0 0xc4301000 0 0x1000>,
  335. <0x0 0xc4302000 0 0x2000>,
  336. <0x0 0xc4304000 0 0x2000>,
  337. <0x0 0xc4306000 0 0x2000>;
  338. interrupt-controller;
  339. interrupts = <GIC_PPI 9
  340. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  341. #interrupt-cells = <3>;
  342. #address-cells = <0>;
  343. };
  344. sram: sram@c8000000 {
  345. compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
  346. reg = <0x0 0xc8000000 0x0 0x14000>;
  347. #address-cells = <1>;
  348. #size-cells = <1>;
  349. ranges = <0 0x0 0xc8000000 0x14000>;
  350. cpu_scp_lpri: scp-shmem@0 {
  351. compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
  352. reg = <0x13000 0x400>;
  353. };
  354. cpu_scp_hpri: scp-shmem@200 {
  355. compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
  356. reg = <0x13400 0x400>;
  357. };
  358. };
  359. aobus: bus@c8100000 {
  360. compatible = "simple-bus";
  361. reg = <0x0 0xc8100000 0x0 0x100000>;
  362. #address-cells = <2>;
  363. #size-cells = <2>;
  364. ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
  365. sysctrl_AO: sys-ctrl@0 {
  366. compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
  367. reg = <0x0 0x0 0x0 0x100>;
  368. pwrc_vpu: power-controller-vpu {
  369. compatible = "amlogic,meson-gx-pwrc-vpu";
  370. #power-domain-cells = <0>;
  371. amlogic,hhi-sysctrl = <&sysctrl>;
  372. };
  373. clkc_AO: clock-controller {
  374. compatible = "amlogic,meson-gx-aoclkc";
  375. #clock-cells = <1>;
  376. #reset-cells = <1>;
  377. };
  378. };
  379. cec_AO: cec@100 {
  380. compatible = "amlogic,meson-gx-ao-cec";
  381. reg = <0x0 0x00100 0x0 0x14>;
  382. interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
  383. status = "disabled";
  384. };
  385. sec_AO: ao-secure@140 {
  386. compatible = "amlogic,meson-gx-ao-secure", "syscon";
  387. reg = <0x0 0x140 0x0 0x140>;
  388. amlogic,has-chip-id;
  389. };
  390. uart_AO: serial@4c0 {
  391. compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
  392. reg = <0x0 0x004c0 0x0 0x18>;
  393. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  394. status = "disabled";
  395. };
  396. uart_AO_B: serial@4e0 {
  397. compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
  398. reg = <0x0 0x004e0 0x0 0x18>;
  399. interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
  400. status = "disabled";
  401. };
  402. i2c_AO: i2c@500 {
  403. compatible = "amlogic,meson-gxbb-i2c";
  404. reg = <0x0 0x500 0x0 0x20>;
  405. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  406. #address-cells = <1>;
  407. #size-cells = <0>;
  408. status = "disabled";
  409. };
  410. pwm_AO_ab: pwm@550 {
  411. compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
  412. reg = <0x0 0x00550 0x0 0x10>;
  413. #pwm-cells = <3>;
  414. status = "disabled";
  415. };
  416. ir: ir@580 {
  417. compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
  418. reg = <0x0 0x00580 0x0 0x40>;
  419. interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
  420. status = "disabled";
  421. };
  422. };
  423. vdec: video-codec@c8820000 {
  424. compatible = "amlogic,gx-vdec";
  425. reg = <0x0 0xc8820000 0x0 0x10000>,
  426. <0x0 0xc110a580 0x0 0xe4>;
  427. reg-names = "dos", "esparser";
  428. interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
  429. <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
  430. interrupt-names = "vdec", "esparser";
  431. amlogic,ao-sysctrl = <&sysctrl_AO>;
  432. amlogic,canvas = <&canvas>;
  433. };
  434. periphs: bus@c8834000 {
  435. compatible = "simple-bus";
  436. reg = <0x0 0xc8834000 0x0 0x2000>;
  437. #address-cells = <2>;
  438. #size-cells = <2>;
  439. ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
  440. hwrng: rng {
  441. compatible = "amlogic,meson-rng";
  442. reg = <0x0 0x0 0x0 0x4>;
  443. };
  444. };
  445. dmcbus: bus@c8838000 {
  446. compatible = "simple-bus";
  447. reg = <0x0 0xc8838000 0x0 0x400>;
  448. #address-cells = <2>;
  449. #size-cells = <2>;
  450. ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
  451. canvas: video-lut@48 {
  452. compatible = "amlogic,canvas";
  453. reg = <0x0 0x48 0x0 0x14>;
  454. };
  455. };
  456. hiubus: bus@c883c000 {
  457. compatible = "simple-bus";
  458. reg = <0x0 0xc883c000 0x0 0x2000>;
  459. #address-cells = <2>;
  460. #size-cells = <2>;
  461. ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
  462. sysctrl: system-controller@0 {
  463. compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
  464. reg = <0 0 0 0x400>;
  465. };
  466. mailbox: mailbox@404 {
  467. compatible = "amlogic,meson-gxbb-mhu";
  468. reg = <0 0x404 0 0x4c>;
  469. interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
  470. <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
  471. <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
  472. #mbox-cells = <1>;
  473. };
  474. };
  475. ethmac: ethernet@c9410000 {
  476. compatible = "amlogic,meson-gxbb-dwmac",
  477. "snps,dwmac-3.70a",
  478. "snps,dwmac";
  479. reg = <0x0 0xc9410000 0x0 0x10000>,
  480. <0x0 0xc8834540 0x0 0x4>;
  481. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  482. interrupt-names = "macirq";
  483. rx-fifo-depth = <4096>;
  484. tx-fifo-depth = <2048>;
  485. status = "disabled";
  486. };
  487. apb: apb@d0000000 {
  488. compatible = "simple-bus";
  489. reg = <0x0 0xd0000000 0x0 0x200000>;
  490. #address-cells = <2>;
  491. #size-cells = <2>;
  492. ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
  493. sd_emmc_a: mmc@70000 {
  494. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  495. reg = <0x0 0x70000 0x0 0x800>;
  496. interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
  497. status = "disabled";
  498. };
  499. sd_emmc_b: mmc@72000 {
  500. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  501. reg = <0x0 0x72000 0x0 0x800>;
  502. interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
  503. status = "disabled";
  504. };
  505. sd_emmc_c: mmc@74000 {
  506. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  507. reg = <0x0 0x74000 0x0 0x800>;
  508. interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
  509. status = "disabled";
  510. };
  511. };
  512. vpu: vpu@d0100000 {
  513. compatible = "amlogic,meson-gx-vpu";
  514. reg = <0x0 0xd0100000 0x0 0x100000>,
  515. <0x0 0xc883c000 0x0 0x1000>;
  516. reg-names = "vpu", "hhi";
  517. interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
  518. #address-cells = <1>;
  519. #size-cells = <0>;
  520. amlogic,canvas = <&canvas>;
  521. /* CVBS VDAC output port */
  522. cvbs_vdac_port: port@0 {
  523. reg = <0>;
  524. };
  525. /* HDMI-TX output port */
  526. hdmi_tx_port: port@1 {
  527. reg = <1>;
  528. hdmi_tx_out: endpoint {
  529. remote-endpoint = <&hdmi_tx_in>;
  530. };
  531. };
  532. };
  533. hdmi_tx: hdmi-tx@c883a000 {
  534. compatible = "amlogic,meson-gx-dw-hdmi";
  535. reg = <0x0 0xc883a000 0x0 0x1c>;
  536. interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
  537. #address-cells = <1>;
  538. #size-cells = <0>;
  539. status = "disabled";
  540. /* VPU VENC Input */
  541. hdmi_tx_venc_port: port@0 {
  542. reg = <0>;
  543. hdmi_tx_in: endpoint {
  544. remote-endpoint = <&hdmi_tx_out>;
  545. };
  546. };
  547. /* TMDS Output */
  548. hdmi_tx_tmds_port: port@1 {
  549. reg = <1>;
  550. };
  551. };
  552. };
  553. };