meson-g12-common.dtsi 52 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
  4. */
  5. #include <dt-bindings/phy/phy.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/clock/g12a-clkc.h>
  8. #include <dt-bindings/clock/g12a-aoclkc.h>
  9. #include <dt-bindings/interrupt-controller/irq.h>
  10. #include <dt-bindings/interrupt-controller/arm-gic.h>
  11. #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
  12. #include <dt-bindings/thermal/thermal.h>
  13. / {
  14. interrupt-parent = <&gic>;
  15. #address-cells = <2>;
  16. #size-cells = <2>;
  17. chosen {
  18. #address-cells = <2>;
  19. #size-cells = <2>;
  20. ranges;
  21. simplefb_cvbs: framebuffer-cvbs {
  22. compatible = "amlogic,simple-framebuffer",
  23. "simple-framebuffer";
  24. amlogic,pipeline = "vpu-cvbs";
  25. clocks = <&clkc CLKID_HDMI>,
  26. <&clkc CLKID_HTX_PCLK>,
  27. <&clkc CLKID_VPU_INTR>;
  28. status = "disabled";
  29. };
  30. simplefb_hdmi: framebuffer-hdmi {
  31. compatible = "amlogic,simple-framebuffer",
  32. "simple-framebuffer";
  33. amlogic,pipeline = "vpu-hdmi";
  34. clocks = <&clkc CLKID_HDMI>,
  35. <&clkc CLKID_HTX_PCLK>,
  36. <&clkc CLKID_VPU_INTR>;
  37. status = "disabled";
  38. };
  39. };
  40. efuse: efuse {
  41. compatible = "amlogic,meson-gxbb-efuse";
  42. clocks = <&clkc CLKID_EFUSE>;
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. read-only;
  46. secure-monitor = <&sm>;
  47. };
  48. psci {
  49. compatible = "arm,psci-1.0";
  50. method = "smc";
  51. };
  52. reserved-memory {
  53. #address-cells = <2>;
  54. #size-cells = <2>;
  55. ranges;
  56. /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
  57. secmon_reserved: secmon@5000000 {
  58. reg = <0x0 0x05000000 0x0 0x300000>;
  59. no-map;
  60. };
  61. linux,cma {
  62. compatible = "shared-dma-pool";
  63. reusable;
  64. size = <0x0 0x10000000>;
  65. alignment = <0x0 0x400000>;
  66. linux,cma-default;
  67. };
  68. };
  69. sm: secure-monitor {
  70. compatible = "amlogic,meson-gxbb-sm";
  71. };
  72. soc {
  73. compatible = "simple-bus";
  74. #address-cells = <2>;
  75. #size-cells = <2>;
  76. ranges;
  77. pcie: pcie@fc000000 {
  78. compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
  79. reg = <0x0 0xfc000000 0x0 0x400000
  80. 0x0 0xff648000 0x0 0x2000
  81. 0x0 0xfc400000 0x0 0x200000>;
  82. reg-names = "elbi", "cfg", "config";
  83. interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
  84. #interrupt-cells = <1>;
  85. interrupt-map-mask = <0 0 0 0>;
  86. interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
  87. bus-range = <0x0 0xff>;
  88. #address-cells = <3>;
  89. #size-cells = <2>;
  90. device_type = "pci";
  91. ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
  92. 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
  93. clocks = <&clkc CLKID_PCIE_PHY
  94. &clkc CLKID_PCIE_COMB
  95. &clkc CLKID_PCIE_PLL>;
  96. clock-names = "general",
  97. "pclk",
  98. "port";
  99. resets = <&reset RESET_PCIE_CTRL_A>,
  100. <&reset RESET_PCIE_APB>;
  101. reset-names = "port",
  102. "apb";
  103. num-lanes = <1>;
  104. phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
  105. phy-names = "pcie";
  106. status = "disabled";
  107. };
  108. thermal-zones {
  109. cpu_thermal: cpu-thermal {
  110. polling-delay = <1000>;
  111. polling-delay-passive = <100>;
  112. thermal-sensors = <&cpu_temp>;
  113. trips {
  114. cpu_passive: cpu-passive {
  115. temperature = <85000>; /* millicelsius */
  116. hysteresis = <2000>; /* millicelsius */
  117. type = "passive";
  118. };
  119. cpu_hot: cpu-hot {
  120. temperature = <95000>; /* millicelsius */
  121. hysteresis = <2000>; /* millicelsius */
  122. type = "hot";
  123. };
  124. cpu_critical: cpu-critical {
  125. temperature = <110000>; /* millicelsius */
  126. hysteresis = <2000>; /* millicelsius */
  127. type = "critical";
  128. };
  129. };
  130. };
  131. ddr_thermal: ddr-thermal {
  132. polling-delay = <1000>;
  133. polling-delay-passive = <100>;
  134. thermal-sensors = <&ddr_temp>;
  135. trips {
  136. ddr_passive: ddr-passive {
  137. temperature = <85000>; /* millicelsius */
  138. hysteresis = <2000>; /* millicelsius */
  139. type = "passive";
  140. };
  141. ddr_critical: ddr-critical {
  142. temperature = <110000>; /* millicelsius */
  143. hysteresis = <2000>; /* millicelsius */
  144. type = "critical";
  145. };
  146. };
  147. cooling-maps {
  148. map {
  149. trip = <&ddr_passive>;
  150. cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  151. };
  152. };
  153. };
  154. };
  155. ethmac: ethernet@ff3f0000 {
  156. compatible = "amlogic,meson-axg-dwmac",
  157. "snps,dwmac-3.70a",
  158. "snps,dwmac";
  159. reg = <0x0 0xff3f0000 0x0 0x10000>,
  160. <0x0 0xff634540 0x0 0x8>;
  161. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  162. interrupt-names = "macirq";
  163. clocks = <&clkc CLKID_ETH>,
  164. <&clkc CLKID_FCLK_DIV2>,
  165. <&clkc CLKID_MPLL2>;
  166. clock-names = "stmmaceth", "clkin0", "clkin1";
  167. rx-fifo-depth = <4096>;
  168. tx-fifo-depth = <2048>;
  169. status = "disabled";
  170. mdio0: mdio {
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. compatible = "snps,dwmac-mdio";
  174. };
  175. };
  176. apb: bus@ff600000 {
  177. compatible = "simple-bus";
  178. reg = <0x0 0xff600000 0x0 0x200000>;
  179. #address-cells = <2>;
  180. #size-cells = <2>;
  181. ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
  182. hdmi_tx: hdmi-tx@0 {
  183. compatible = "amlogic,meson-g12a-dw-hdmi";
  184. reg = <0x0 0x0 0x0 0x10000>;
  185. interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
  186. resets = <&reset RESET_HDMITX_CAPB3>,
  187. <&reset RESET_HDMITX_PHY>,
  188. <&reset RESET_HDMITX>;
  189. reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
  190. clocks = <&clkc CLKID_HDMI>,
  191. <&clkc CLKID_HTX_PCLK>,
  192. <&clkc CLKID_VPU_INTR>;
  193. clock-names = "isfr", "iahb", "venci";
  194. #address-cells = <1>;
  195. #size-cells = <0>;
  196. #sound-dai-cells = <0>;
  197. status = "disabled";
  198. /* VPU VENC Input */
  199. hdmi_tx_venc_port: port@0 {
  200. reg = <0>;
  201. hdmi_tx_in: endpoint {
  202. remote-endpoint = <&hdmi_tx_out>;
  203. };
  204. };
  205. /* TMDS Output */
  206. hdmi_tx_tmds_port: port@1 {
  207. reg = <1>;
  208. };
  209. };
  210. apb_efuse: bus@30000 {
  211. compatible = "simple-bus";
  212. reg = <0x0 0x30000 0x0 0x2000>;
  213. #address-cells = <2>;
  214. #size-cells = <2>;
  215. ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
  216. hwrng: rng@218 {
  217. compatible = "amlogic,meson-rng";
  218. reg = <0x0 0x218 0x0 0x4>;
  219. };
  220. };
  221. periphs: bus@34400 {
  222. compatible = "simple-bus";
  223. reg = <0x0 0x34400 0x0 0x400>;
  224. #address-cells = <2>;
  225. #size-cells = <2>;
  226. ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
  227. periphs_pinctrl: pinctrl@40 {
  228. compatible = "amlogic,meson-g12a-periphs-pinctrl";
  229. #address-cells = <2>;
  230. #size-cells = <2>;
  231. ranges;
  232. gpio: bank@40 {
  233. reg = <0x0 0x40 0x0 0x4c>,
  234. <0x0 0xe8 0x0 0x18>,
  235. <0x0 0x120 0x0 0x18>,
  236. <0x0 0x2c0 0x0 0x40>,
  237. <0x0 0x340 0x0 0x1c>;
  238. reg-names = "gpio",
  239. "pull",
  240. "pull-enable",
  241. "mux",
  242. "ds";
  243. gpio-controller;
  244. #gpio-cells = <2>;
  245. gpio-ranges = <&periphs_pinctrl 0 0 86>;
  246. };
  247. cec_ao_a_h_pins: cec_ao_a_h {
  248. mux {
  249. groups = "cec_ao_a_h";
  250. function = "cec_ao_a_h";
  251. bias-disable;
  252. };
  253. };
  254. cec_ao_b_h_pins: cec_ao_b_h {
  255. mux {
  256. groups = "cec_ao_b_h";
  257. function = "cec_ao_b_h";
  258. bias-disable;
  259. };
  260. };
  261. emmc_ctrl_pins: emmc-ctrl {
  262. mux-0 {
  263. groups = "emmc_cmd";
  264. function = "emmc";
  265. bias-pull-up;
  266. drive-strength-microamp = <4000>;
  267. };
  268. mux-1 {
  269. groups = "emmc_clk";
  270. function = "emmc";
  271. bias-disable;
  272. drive-strength-microamp = <4000>;
  273. };
  274. };
  275. emmc_data_4b_pins: emmc-data-4b {
  276. mux-0 {
  277. groups = "emmc_nand_d0",
  278. "emmc_nand_d1",
  279. "emmc_nand_d2",
  280. "emmc_nand_d3";
  281. function = "emmc";
  282. bias-pull-up;
  283. drive-strength-microamp = <4000>;
  284. };
  285. };
  286. emmc_data_8b_pins: emmc-data-8b {
  287. mux-0 {
  288. groups = "emmc_nand_d0",
  289. "emmc_nand_d1",
  290. "emmc_nand_d2",
  291. "emmc_nand_d3",
  292. "emmc_nand_d4",
  293. "emmc_nand_d5",
  294. "emmc_nand_d6",
  295. "emmc_nand_d7";
  296. function = "emmc";
  297. bias-pull-up;
  298. drive-strength-microamp = <4000>;
  299. };
  300. };
  301. emmc_ds_pins: emmc-ds {
  302. mux {
  303. groups = "emmc_nand_ds";
  304. function = "emmc";
  305. bias-pull-down;
  306. drive-strength-microamp = <4000>;
  307. };
  308. };
  309. emmc_clk_gate_pins: emmc_clk_gate {
  310. mux {
  311. groups = "BOOT_8";
  312. function = "gpio_periphs";
  313. bias-pull-down;
  314. drive-strength-microamp = <4000>;
  315. };
  316. };
  317. hdmitx_ddc_pins: hdmitx_ddc {
  318. mux {
  319. groups = "hdmitx_sda",
  320. "hdmitx_sck";
  321. function = "hdmitx";
  322. bias-disable;
  323. drive-strength-microamp = <4000>;
  324. };
  325. };
  326. hdmitx_hpd_pins: hdmitx_hpd {
  327. mux {
  328. groups = "hdmitx_hpd_in";
  329. function = "hdmitx";
  330. bias-disable;
  331. };
  332. };
  333. i2c0_sda_c_pins: i2c0-sda-c {
  334. mux {
  335. groups = "i2c0_sda_c";
  336. function = "i2c0";
  337. bias-disable;
  338. drive-strength-microamp = <3000>;
  339. };
  340. };
  341. i2c0_sck_c_pins: i2c0-sck-c {
  342. mux {
  343. groups = "i2c0_sck_c";
  344. function = "i2c0";
  345. bias-disable;
  346. drive-strength-microamp = <3000>;
  347. };
  348. };
  349. i2c0_sda_z0_pins: i2c0-sda-z0 {
  350. mux {
  351. groups = "i2c0_sda_z0";
  352. function = "i2c0";
  353. bias-disable;
  354. drive-strength-microamp = <3000>;
  355. };
  356. };
  357. i2c0_sck_z1_pins: i2c0-sck-z1 {
  358. mux {
  359. groups = "i2c0_sck_z1";
  360. function = "i2c0";
  361. bias-disable;
  362. drive-strength-microamp = <3000>;
  363. };
  364. };
  365. i2c0_sda_z7_pins: i2c0-sda-z7 {
  366. mux {
  367. groups = "i2c0_sda_z7";
  368. function = "i2c0";
  369. bias-disable;
  370. drive-strength-microamp = <3000>;
  371. };
  372. };
  373. i2c0_sda_z8_pins: i2c0-sda-z8 {
  374. mux {
  375. groups = "i2c0_sda_z8";
  376. function = "i2c0";
  377. bias-disable;
  378. drive-strength-microamp = <3000>;
  379. };
  380. };
  381. i2c1_sda_x_pins: i2c1-sda-x {
  382. mux {
  383. groups = "i2c1_sda_x";
  384. function = "i2c1";
  385. bias-disable;
  386. drive-strength-microamp = <3000>;
  387. };
  388. };
  389. i2c1_sck_x_pins: i2c1-sck-x {
  390. mux {
  391. groups = "i2c1_sck_x";
  392. function = "i2c1";
  393. bias-disable;
  394. drive-strength-microamp = <3000>;
  395. };
  396. };
  397. i2c1_sda_h2_pins: i2c1-sda-h2 {
  398. mux {
  399. groups = "i2c1_sda_h2";
  400. function = "i2c1";
  401. bias-disable;
  402. drive-strength-microamp = <3000>;
  403. };
  404. };
  405. i2c1_sck_h3_pins: i2c1-sck-h3 {
  406. mux {
  407. groups = "i2c1_sck_h3";
  408. function = "i2c1";
  409. bias-disable;
  410. drive-strength-microamp = <3000>;
  411. };
  412. };
  413. i2c1_sda_h6_pins: i2c1-sda-h6 {
  414. mux {
  415. groups = "i2c1_sda_h6";
  416. function = "i2c1";
  417. bias-disable;
  418. drive-strength-microamp = <3000>;
  419. };
  420. };
  421. i2c1_sck_h7_pins: i2c1-sck-h7 {
  422. mux {
  423. groups = "i2c1_sck_h7";
  424. function = "i2c1";
  425. bias-disable;
  426. drive-strength-microamp = <3000>;
  427. };
  428. };
  429. i2c2_sda_x_pins: i2c2-sda-x {
  430. mux {
  431. groups = "i2c2_sda_x";
  432. function = "i2c2";
  433. bias-disable;
  434. drive-strength-microamp = <3000>;
  435. };
  436. };
  437. i2c2_sck_x_pins: i2c2-sck-x {
  438. mux {
  439. groups = "i2c2_sck_x";
  440. function = "i2c2";
  441. bias-disable;
  442. drive-strength-microamp = <3000>;
  443. };
  444. };
  445. i2c2_sda_z_pins: i2c2-sda-z {
  446. mux {
  447. groups = "i2c2_sda_z";
  448. function = "i2c2";
  449. bias-disable;
  450. drive-strength-microamp = <3000>;
  451. };
  452. };
  453. i2c2_sck_z_pins: i2c2-sck-z {
  454. mux {
  455. groups = "i2c2_sck_z";
  456. function = "i2c2";
  457. bias-disable;
  458. drive-strength-microamp = <3000>;
  459. };
  460. };
  461. i2c3_sda_h_pins: i2c3-sda-h {
  462. mux {
  463. groups = "i2c3_sda_h";
  464. function = "i2c3";
  465. bias-disable;
  466. drive-strength-microamp = <3000>;
  467. };
  468. };
  469. i2c3_sck_h_pins: i2c3-sck-h {
  470. mux {
  471. groups = "i2c3_sck_h";
  472. function = "i2c3";
  473. bias-disable;
  474. drive-strength-microamp = <3000>;
  475. };
  476. };
  477. i2c3_sda_a_pins: i2c3-sda-a {
  478. mux {
  479. groups = "i2c3_sda_a";
  480. function = "i2c3";
  481. bias-disable;
  482. drive-strength-microamp = <3000>;
  483. };
  484. };
  485. i2c3_sck_a_pins: i2c3-sck-a {
  486. mux {
  487. groups = "i2c3_sck_a";
  488. function = "i2c3";
  489. bias-disable;
  490. drive-strength-microamp = <3000>;
  491. };
  492. };
  493. mclk0_a_pins: mclk0-a {
  494. mux {
  495. groups = "mclk0_a";
  496. function = "mclk0";
  497. bias-disable;
  498. drive-strength-microamp = <3000>;
  499. };
  500. };
  501. mclk1_a_pins: mclk1-a {
  502. mux {
  503. groups = "mclk1_a";
  504. function = "mclk1";
  505. bias-disable;
  506. drive-strength-microamp = <3000>;
  507. };
  508. };
  509. mclk1_x_pins: mclk1-x {
  510. mux {
  511. groups = "mclk1_x";
  512. function = "mclk1";
  513. bias-disable;
  514. drive-strength-microamp = <3000>;
  515. };
  516. };
  517. mclk1_z_pins: mclk1-z {
  518. mux {
  519. groups = "mclk1_z";
  520. function = "mclk1";
  521. bias-disable;
  522. drive-strength-microamp = <3000>;
  523. };
  524. };
  525. nor_pins: nor {
  526. mux {
  527. groups = "nor_d",
  528. "nor_q",
  529. "nor_c",
  530. "nor_cs";
  531. function = "nor";
  532. bias-disable;
  533. };
  534. };
  535. pdm_din0_a_pins: pdm-din0-a {
  536. mux {
  537. groups = "pdm_din0_a";
  538. function = "pdm";
  539. bias-disable;
  540. };
  541. };
  542. pdm_din0_c_pins: pdm-din0-c {
  543. mux {
  544. groups = "pdm_din0_c";
  545. function = "pdm";
  546. bias-disable;
  547. };
  548. };
  549. pdm_din0_x_pins: pdm-din0-x {
  550. mux {
  551. groups = "pdm_din0_x";
  552. function = "pdm";
  553. bias-disable;
  554. };
  555. };
  556. pdm_din0_z_pins: pdm-din0-z {
  557. mux {
  558. groups = "pdm_din0_z";
  559. function = "pdm";
  560. bias-disable;
  561. };
  562. };
  563. pdm_din1_a_pins: pdm-din1-a {
  564. mux {
  565. groups = "pdm_din1_a";
  566. function = "pdm";
  567. bias-disable;
  568. };
  569. };
  570. pdm_din1_c_pins: pdm-din1-c {
  571. mux {
  572. groups = "pdm_din1_c";
  573. function = "pdm";
  574. bias-disable;
  575. };
  576. };
  577. pdm_din1_x_pins: pdm-din1-x {
  578. mux {
  579. groups = "pdm_din1_x";
  580. function = "pdm";
  581. bias-disable;
  582. };
  583. };
  584. pdm_din1_z_pins: pdm-din1-z {
  585. mux {
  586. groups = "pdm_din1_z";
  587. function = "pdm";
  588. bias-disable;
  589. };
  590. };
  591. pdm_din2_a_pins: pdm-din2-a {
  592. mux {
  593. groups = "pdm_din2_a";
  594. function = "pdm";
  595. bias-disable;
  596. };
  597. };
  598. pdm_din2_c_pins: pdm-din2-c {
  599. mux {
  600. groups = "pdm_din2_c";
  601. function = "pdm";
  602. bias-disable;
  603. };
  604. };
  605. pdm_din2_x_pins: pdm-din2-x {
  606. mux {
  607. groups = "pdm_din2_x";
  608. function = "pdm";
  609. bias-disable;
  610. };
  611. };
  612. pdm_din2_z_pins: pdm-din2-z {
  613. mux {
  614. groups = "pdm_din2_z";
  615. function = "pdm";
  616. bias-disable;
  617. };
  618. };
  619. pdm_din3_a_pins: pdm-din3-a {
  620. mux {
  621. groups = "pdm_din3_a";
  622. function = "pdm";
  623. bias-disable;
  624. };
  625. };
  626. pdm_din3_c_pins: pdm-din3-c {
  627. mux {
  628. groups = "pdm_din3_c";
  629. function = "pdm";
  630. bias-disable;
  631. };
  632. };
  633. pdm_din3_x_pins: pdm-din3-x {
  634. mux {
  635. groups = "pdm_din3_x";
  636. function = "pdm";
  637. bias-disable;
  638. };
  639. };
  640. pdm_din3_z_pins: pdm-din3-z {
  641. mux {
  642. groups = "pdm_din3_z";
  643. function = "pdm";
  644. bias-disable;
  645. };
  646. };
  647. pdm_dclk_a_pins: pdm-dclk-a {
  648. mux {
  649. groups = "pdm_dclk_a";
  650. function = "pdm";
  651. bias-disable;
  652. drive-strength-microamp = <500>;
  653. };
  654. };
  655. pdm_dclk_c_pins: pdm-dclk-c {
  656. mux {
  657. groups = "pdm_dclk_c";
  658. function = "pdm";
  659. bias-disable;
  660. drive-strength-microamp = <500>;
  661. };
  662. };
  663. pdm_dclk_x_pins: pdm-dclk-x {
  664. mux {
  665. groups = "pdm_dclk_x";
  666. function = "pdm";
  667. bias-disable;
  668. drive-strength-microamp = <500>;
  669. };
  670. };
  671. pdm_dclk_z_pins: pdm-dclk-z {
  672. mux {
  673. groups = "pdm_dclk_z";
  674. function = "pdm";
  675. bias-disable;
  676. drive-strength-microamp = <500>;
  677. };
  678. };
  679. pwm_a_pins: pwm-a {
  680. mux {
  681. groups = "pwm_a";
  682. function = "pwm_a";
  683. bias-disable;
  684. };
  685. };
  686. pwm_b_x7_pins: pwm-b-x7 {
  687. mux {
  688. groups = "pwm_b_x7";
  689. function = "pwm_b";
  690. bias-disable;
  691. };
  692. };
  693. pwm_b_x19_pins: pwm-b-x19 {
  694. mux {
  695. groups = "pwm_b_x19";
  696. function = "pwm_b";
  697. bias-disable;
  698. };
  699. };
  700. pwm_c_c_pins: pwm-c-c {
  701. mux {
  702. groups = "pwm_c_c";
  703. function = "pwm_c";
  704. bias-disable;
  705. };
  706. };
  707. pwm_c_x5_pins: pwm-c-x5 {
  708. mux {
  709. groups = "pwm_c_x5";
  710. function = "pwm_c";
  711. bias-disable;
  712. };
  713. };
  714. pwm_c_x8_pins: pwm-c-x8 {
  715. mux {
  716. groups = "pwm_c_x8";
  717. function = "pwm_c";
  718. bias-disable;
  719. };
  720. };
  721. pwm_d_x3_pins: pwm-d-x3 {
  722. mux {
  723. groups = "pwm_d_x3";
  724. function = "pwm_d";
  725. bias-disable;
  726. };
  727. };
  728. pwm_d_x6_pins: pwm-d-x6 {
  729. mux {
  730. groups = "pwm_d_x6";
  731. function = "pwm_d";
  732. bias-disable;
  733. };
  734. };
  735. pwm_e_pins: pwm-e {
  736. mux {
  737. groups = "pwm_e";
  738. function = "pwm_e";
  739. bias-disable;
  740. };
  741. };
  742. pwm_f_x_pins: pwm-f-x {
  743. mux {
  744. groups = "pwm_f_x";
  745. function = "pwm_f";
  746. bias-disable;
  747. };
  748. };
  749. pwm_f_h_pins: pwm-f-h {
  750. mux {
  751. groups = "pwm_f_h";
  752. function = "pwm_f";
  753. bias-disable;
  754. };
  755. };
  756. sdcard_c_pins: sdcard_c {
  757. mux-0 {
  758. groups = "sdcard_d0_c",
  759. "sdcard_d1_c",
  760. "sdcard_d2_c",
  761. "sdcard_d3_c",
  762. "sdcard_cmd_c";
  763. function = "sdcard";
  764. bias-pull-up;
  765. drive-strength-microamp = <4000>;
  766. };
  767. mux-1 {
  768. groups = "sdcard_clk_c";
  769. function = "sdcard";
  770. bias-disable;
  771. drive-strength-microamp = <4000>;
  772. };
  773. };
  774. sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
  775. mux {
  776. groups = "GPIOC_4";
  777. function = "gpio_periphs";
  778. bias-pull-down;
  779. drive-strength-microamp = <4000>;
  780. };
  781. };
  782. sdcard_z_pins: sdcard_z {
  783. mux-0 {
  784. groups = "sdcard_d0_z",
  785. "sdcard_d1_z",
  786. "sdcard_d2_z",
  787. "sdcard_d3_z",
  788. "sdcard_cmd_z";
  789. function = "sdcard";
  790. bias-pull-up;
  791. drive-strength-microamp = <4000>;
  792. };
  793. mux-1 {
  794. groups = "sdcard_clk_z";
  795. function = "sdcard";
  796. bias-disable;
  797. drive-strength-microamp = <4000>;
  798. };
  799. };
  800. sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
  801. mux {
  802. groups = "GPIOZ_6";
  803. function = "gpio_periphs";
  804. bias-pull-down;
  805. drive-strength-microamp = <4000>;
  806. };
  807. };
  808. sdio_pins: sdio {
  809. mux {
  810. groups = "sdio_d0",
  811. "sdio_d1",
  812. "sdio_d2",
  813. "sdio_d3",
  814. "sdio_clk",
  815. "sdio_cmd";
  816. function = "sdio";
  817. bias-disable;
  818. drive-strength-microamp = <4000>;
  819. };
  820. };
  821. sdio_clk_gate_pins: sdio_clk_gate {
  822. mux {
  823. groups = "GPIOX_4";
  824. function = "gpio_periphs";
  825. bias-pull-down;
  826. drive-strength-microamp = <4000>;
  827. };
  828. };
  829. spdif_in_a10_pins: spdif-in-a10 {
  830. mux {
  831. groups = "spdif_in_a10";
  832. function = "spdif_in";
  833. bias-disable;
  834. };
  835. };
  836. spdif_in_a12_pins: spdif-in-a12 {
  837. mux {
  838. groups = "spdif_in_a12";
  839. function = "spdif_in";
  840. bias-disable;
  841. };
  842. };
  843. spdif_in_h_pins: spdif-in-h {
  844. mux {
  845. groups = "spdif_in_h";
  846. function = "spdif_in";
  847. bias-disable;
  848. };
  849. };
  850. spdif_out_h_pins: spdif-out-h {
  851. mux {
  852. groups = "spdif_out_h";
  853. function = "spdif_out";
  854. drive-strength-microamp = <500>;
  855. bias-disable;
  856. };
  857. };
  858. spdif_out_a11_pins: spdif-out-a11 {
  859. mux {
  860. groups = "spdif_out_a11";
  861. function = "spdif_out";
  862. drive-strength-microamp = <500>;
  863. bias-disable;
  864. };
  865. };
  866. spdif_out_a13_pins: spdif-out-a13 {
  867. mux {
  868. groups = "spdif_out_a13";
  869. function = "spdif_out";
  870. drive-strength-microamp = <500>;
  871. bias-disable;
  872. };
  873. };
  874. spicc0_x_pins: spicc0-x {
  875. mux {
  876. groups = "spi0_mosi_x",
  877. "spi0_miso_x",
  878. "spi0_clk_x";
  879. function = "spi0";
  880. drive-strength-microamp = <4000>;
  881. bias-disable;
  882. };
  883. };
  884. spicc0_ss0_x_pins: spicc0-ss0-x {
  885. mux {
  886. groups = "spi0_ss0_x";
  887. function = "spi0";
  888. drive-strength-microamp = <4000>;
  889. bias-disable;
  890. };
  891. };
  892. spicc0_c_pins: spicc0-c {
  893. mux {
  894. groups = "spi0_mosi_c",
  895. "spi0_miso_c",
  896. "spi0_ss0_c",
  897. "spi0_clk_c";
  898. function = "spi0";
  899. drive-strength-microamp = <4000>;
  900. bias-disable;
  901. };
  902. };
  903. spicc1_pins: spicc1 {
  904. mux {
  905. groups = "spi1_mosi",
  906. "spi1_miso",
  907. "spi1_clk";
  908. function = "spi1";
  909. drive-strength-microamp = <4000>;
  910. };
  911. };
  912. spicc1_ss0_pins: spicc1-ss0 {
  913. mux {
  914. groups = "spi1_ss0";
  915. function = "spi1";
  916. drive-strength-microamp = <4000>;
  917. bias-disable;
  918. };
  919. };
  920. tdm_a_din0_pins: tdm-a-din0 {
  921. mux {
  922. groups = "tdm_a_din0";
  923. function = "tdm_a";
  924. bias-disable;
  925. };
  926. };
  927. tdm_a_din1_pins: tdm-a-din1 {
  928. mux {
  929. groups = "tdm_a_din1";
  930. function = "tdm_a";
  931. bias-disable;
  932. };
  933. };
  934. tdm_a_dout0_pins: tdm-a-dout0 {
  935. mux {
  936. groups = "tdm_a_dout0";
  937. function = "tdm_a";
  938. bias-disable;
  939. drive-strength-microamp = <3000>;
  940. };
  941. };
  942. tdm_a_dout1_pins: tdm-a-dout1 {
  943. mux {
  944. groups = "tdm_a_dout1";
  945. function = "tdm_a";
  946. bias-disable;
  947. drive-strength-microamp = <3000>;
  948. };
  949. };
  950. tdm_a_fs_pins: tdm-a-fs {
  951. mux {
  952. groups = "tdm_a_fs";
  953. function = "tdm_a";
  954. bias-disable;
  955. drive-strength-microamp = <3000>;
  956. };
  957. };
  958. tdm_a_sclk_pins: tdm-a-sclk {
  959. mux {
  960. groups = "tdm_a_sclk";
  961. function = "tdm_a";
  962. bias-disable;
  963. drive-strength-microamp = <3000>;
  964. };
  965. };
  966. tdm_a_slv_fs_pins: tdm-a-slv-fs {
  967. mux {
  968. groups = "tdm_a_slv_fs";
  969. function = "tdm_a";
  970. bias-disable;
  971. };
  972. };
  973. tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
  974. mux {
  975. groups = "tdm_a_slv_sclk";
  976. function = "tdm_a";
  977. bias-disable;
  978. };
  979. };
  980. tdm_b_din0_pins: tdm-b-din0 {
  981. mux {
  982. groups = "tdm_b_din0";
  983. function = "tdm_b";
  984. bias-disable;
  985. };
  986. };
  987. tdm_b_din1_pins: tdm-b-din1 {
  988. mux {
  989. groups = "tdm_b_din1";
  990. function = "tdm_b";
  991. bias-disable;
  992. };
  993. };
  994. tdm_b_din2_pins: tdm-b-din2 {
  995. mux {
  996. groups = "tdm_b_din2";
  997. function = "tdm_b";
  998. bias-disable;
  999. };
  1000. };
  1001. tdm_b_din3_a_pins: tdm-b-din3-a {
  1002. mux {
  1003. groups = "tdm_b_din3_a";
  1004. function = "tdm_b";
  1005. bias-disable;
  1006. };
  1007. };
  1008. tdm_b_din3_h_pins: tdm-b-din3-h {
  1009. mux {
  1010. groups = "tdm_b_din3_h";
  1011. function = "tdm_b";
  1012. bias-disable;
  1013. };
  1014. };
  1015. tdm_b_dout0_pins: tdm-b-dout0 {
  1016. mux {
  1017. groups = "tdm_b_dout0";
  1018. function = "tdm_b";
  1019. bias-disable;
  1020. drive-strength-microamp = <3000>;
  1021. };
  1022. };
  1023. tdm_b_dout1_pins: tdm-b-dout1 {
  1024. mux {
  1025. groups = "tdm_b_dout1";
  1026. function = "tdm_b";
  1027. bias-disable;
  1028. drive-strength-microamp = <3000>;
  1029. };
  1030. };
  1031. tdm_b_dout2_pins: tdm-b-dout2 {
  1032. mux {
  1033. groups = "tdm_b_dout2";
  1034. function = "tdm_b";
  1035. bias-disable;
  1036. drive-strength-microamp = <3000>;
  1037. };
  1038. };
  1039. tdm_b_dout3_a_pins: tdm-b-dout3-a {
  1040. mux {
  1041. groups = "tdm_b_dout3_a";
  1042. function = "tdm_b";
  1043. bias-disable;
  1044. drive-strength-microamp = <3000>;
  1045. };
  1046. };
  1047. tdm_b_dout3_h_pins: tdm-b-dout3-h {
  1048. mux {
  1049. groups = "tdm_b_dout3_h";
  1050. function = "tdm_b";
  1051. bias-disable;
  1052. drive-strength-microamp = <3000>;
  1053. };
  1054. };
  1055. tdm_b_fs_pins: tdm-b-fs {
  1056. mux {
  1057. groups = "tdm_b_fs";
  1058. function = "tdm_b";
  1059. bias-disable;
  1060. drive-strength-microamp = <3000>;
  1061. };
  1062. };
  1063. tdm_b_sclk_pins: tdm-b-sclk {
  1064. mux {
  1065. groups = "tdm_b_sclk";
  1066. function = "tdm_b";
  1067. bias-disable;
  1068. drive-strength-microamp = <3000>;
  1069. };
  1070. };
  1071. tdm_b_slv_fs_pins: tdm-b-slv-fs {
  1072. mux {
  1073. groups = "tdm_b_slv_fs";
  1074. function = "tdm_b";
  1075. bias-disable;
  1076. };
  1077. };
  1078. tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
  1079. mux {
  1080. groups = "tdm_b_slv_sclk";
  1081. function = "tdm_b";
  1082. bias-disable;
  1083. };
  1084. };
  1085. tdm_c_din0_a_pins: tdm-c-din0-a {
  1086. mux {
  1087. groups = "tdm_c_din0_a";
  1088. function = "tdm_c";
  1089. bias-disable;
  1090. };
  1091. };
  1092. tdm_c_din0_z_pins: tdm-c-din0-z {
  1093. mux {
  1094. groups = "tdm_c_din0_z";
  1095. function = "tdm_c";
  1096. bias-disable;
  1097. };
  1098. };
  1099. tdm_c_din1_a_pins: tdm-c-din1-a {
  1100. mux {
  1101. groups = "tdm_c_din1_a";
  1102. function = "tdm_c";
  1103. bias-disable;
  1104. };
  1105. };
  1106. tdm_c_din1_z_pins: tdm-c-din1-z {
  1107. mux {
  1108. groups = "tdm_c_din1_z";
  1109. function = "tdm_c";
  1110. bias-disable;
  1111. };
  1112. };
  1113. tdm_c_din2_a_pins: tdm-c-din2-a {
  1114. mux {
  1115. groups = "tdm_c_din2_a";
  1116. function = "tdm_c";
  1117. bias-disable;
  1118. };
  1119. };
  1120. eth_leds_pins: eth-leds {
  1121. mux {
  1122. groups = "eth_link_led",
  1123. "eth_act_led";
  1124. function = "eth";
  1125. bias-disable;
  1126. };
  1127. };
  1128. eth_pins: eth {
  1129. mux {
  1130. groups = "eth_mdio",
  1131. "eth_mdc",
  1132. "eth_rgmii_rx_clk",
  1133. "eth_rx_dv",
  1134. "eth_rxd0",
  1135. "eth_rxd1",
  1136. "eth_txen",
  1137. "eth_txd0",
  1138. "eth_txd1";
  1139. function = "eth";
  1140. drive-strength-microamp = <4000>;
  1141. bias-disable;
  1142. };
  1143. };
  1144. eth_rgmii_pins: eth-rgmii {
  1145. mux {
  1146. groups = "eth_rxd2_rgmii",
  1147. "eth_rxd3_rgmii",
  1148. "eth_rgmii_tx_clk",
  1149. "eth_txd2_rgmii",
  1150. "eth_txd3_rgmii";
  1151. function = "eth";
  1152. drive-strength-microamp = <4000>;
  1153. bias-disable;
  1154. };
  1155. };
  1156. tdm_c_din2_z_pins: tdm-c-din2-z {
  1157. mux {
  1158. groups = "tdm_c_din2_z";
  1159. function = "tdm_c";
  1160. bias-disable;
  1161. };
  1162. };
  1163. tdm_c_din3_a_pins: tdm-c-din3-a {
  1164. mux {
  1165. groups = "tdm_c_din3_a";
  1166. function = "tdm_c";
  1167. bias-disable;
  1168. };
  1169. };
  1170. tdm_c_din3_z_pins: tdm-c-din3-z {
  1171. mux {
  1172. groups = "tdm_c_din3_z";
  1173. function = "tdm_c";
  1174. bias-disable;
  1175. };
  1176. };
  1177. tdm_c_dout0_a_pins: tdm-c-dout0-a {
  1178. mux {
  1179. groups = "tdm_c_dout0_a";
  1180. function = "tdm_c";
  1181. bias-disable;
  1182. drive-strength-microamp = <3000>;
  1183. };
  1184. };
  1185. tdm_c_dout0_z_pins: tdm-c-dout0-z {
  1186. mux {
  1187. groups = "tdm_c_dout0_z";
  1188. function = "tdm_c";
  1189. bias-disable;
  1190. drive-strength-microamp = <3000>;
  1191. };
  1192. };
  1193. tdm_c_dout1_a_pins: tdm-c-dout1-a {
  1194. mux {
  1195. groups = "tdm_c_dout1_a";
  1196. function = "tdm_c";
  1197. bias-disable;
  1198. drive-strength-microamp = <3000>;
  1199. };
  1200. };
  1201. tdm_c_dout1_z_pins: tdm-c-dout1-z {
  1202. mux {
  1203. groups = "tdm_c_dout1_z";
  1204. function = "tdm_c";
  1205. bias-disable;
  1206. drive-strength-microamp = <3000>;
  1207. };
  1208. };
  1209. tdm_c_dout2_a_pins: tdm-c-dout2-a {
  1210. mux {
  1211. groups = "tdm_c_dout2_a";
  1212. function = "tdm_c";
  1213. bias-disable;
  1214. drive-strength-microamp = <3000>;
  1215. };
  1216. };
  1217. tdm_c_dout2_z_pins: tdm-c-dout2-z {
  1218. mux {
  1219. groups = "tdm_c_dout2_z";
  1220. function = "tdm_c";
  1221. bias-disable;
  1222. drive-strength-microamp = <3000>;
  1223. };
  1224. };
  1225. tdm_c_dout3_a_pins: tdm-c-dout3-a {
  1226. mux {
  1227. groups = "tdm_c_dout3_a";
  1228. function = "tdm_c";
  1229. bias-disable;
  1230. drive-strength-microamp = <3000>;
  1231. };
  1232. };
  1233. tdm_c_dout3_z_pins: tdm-c-dout3-z {
  1234. mux {
  1235. groups = "tdm_c_dout3_z";
  1236. function = "tdm_c";
  1237. bias-disable;
  1238. drive-strength-microamp = <3000>;
  1239. };
  1240. };
  1241. tdm_c_fs_a_pins: tdm-c-fs-a {
  1242. mux {
  1243. groups = "tdm_c_fs_a";
  1244. function = "tdm_c";
  1245. bias-disable;
  1246. drive-strength-microamp = <3000>;
  1247. };
  1248. };
  1249. tdm_c_fs_z_pins: tdm-c-fs-z {
  1250. mux {
  1251. groups = "tdm_c_fs_z";
  1252. function = "tdm_c";
  1253. bias-disable;
  1254. drive-strength-microamp = <3000>;
  1255. };
  1256. };
  1257. tdm_c_sclk_a_pins: tdm-c-sclk-a {
  1258. mux {
  1259. groups = "tdm_c_sclk_a";
  1260. function = "tdm_c";
  1261. bias-disable;
  1262. drive-strength-microamp = <3000>;
  1263. };
  1264. };
  1265. tdm_c_sclk_z_pins: tdm-c-sclk-z {
  1266. mux {
  1267. groups = "tdm_c_sclk_z";
  1268. function = "tdm_c";
  1269. bias-disable;
  1270. drive-strength-microamp = <3000>;
  1271. };
  1272. };
  1273. tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
  1274. mux {
  1275. groups = "tdm_c_slv_fs_a";
  1276. function = "tdm_c";
  1277. bias-disable;
  1278. };
  1279. };
  1280. tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
  1281. mux {
  1282. groups = "tdm_c_slv_fs_z";
  1283. function = "tdm_c";
  1284. bias-disable;
  1285. };
  1286. };
  1287. tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
  1288. mux {
  1289. groups = "tdm_c_slv_sclk_a";
  1290. function = "tdm_c";
  1291. bias-disable;
  1292. };
  1293. };
  1294. tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
  1295. mux {
  1296. groups = "tdm_c_slv_sclk_z";
  1297. function = "tdm_c";
  1298. bias-disable;
  1299. };
  1300. };
  1301. uart_a_pins: uart-a {
  1302. mux {
  1303. groups = "uart_a_tx",
  1304. "uart_a_rx";
  1305. function = "uart_a";
  1306. bias-disable;
  1307. };
  1308. };
  1309. uart_a_cts_rts_pins: uart-a-cts-rts {
  1310. mux {
  1311. groups = "uart_a_cts",
  1312. "uart_a_rts";
  1313. function = "uart_a";
  1314. bias-disable;
  1315. };
  1316. };
  1317. uart_b_pins: uart-b {
  1318. mux {
  1319. groups = "uart_b_tx",
  1320. "uart_b_rx";
  1321. function = "uart_b";
  1322. bias-disable;
  1323. };
  1324. };
  1325. uart_c_pins: uart-c {
  1326. mux {
  1327. groups = "uart_c_tx",
  1328. "uart_c_rx";
  1329. function = "uart_c";
  1330. bias-disable;
  1331. };
  1332. };
  1333. uart_c_cts_rts_pins: uart-c-cts-rts {
  1334. mux {
  1335. groups = "uart_c_cts",
  1336. "uart_c_rts";
  1337. function = "uart_c";
  1338. bias-disable;
  1339. };
  1340. };
  1341. };
  1342. };
  1343. cpu_temp: temperature-sensor@34800 {
  1344. compatible = "amlogic,g12a-cpu-thermal",
  1345. "amlogic,g12a-thermal";
  1346. reg = <0x0 0x34800 0x0 0x50>;
  1347. interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
  1348. clocks = <&clkc CLKID_TS>;
  1349. #thermal-sensor-cells = <0>;
  1350. amlogic,ao-secure = <&sec_AO>;
  1351. };
  1352. ddr_temp: temperature-sensor@34c00 {
  1353. compatible = "amlogic,g12a-ddr-thermal",
  1354. "amlogic,g12a-thermal";
  1355. reg = <0x0 0x34c00 0x0 0x50>;
  1356. interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
  1357. clocks = <&clkc CLKID_TS>;
  1358. #thermal-sensor-cells = <0>;
  1359. amlogic,ao-secure = <&sec_AO>;
  1360. };
  1361. usb2_phy0: phy@36000 {
  1362. compatible = "amlogic,g12a-usb2-phy";
  1363. reg = <0x0 0x36000 0x0 0x2000>;
  1364. clocks = <&xtal>;
  1365. clock-names = "xtal";
  1366. resets = <&reset RESET_USB_PHY20>;
  1367. reset-names = "phy";
  1368. #phy-cells = <0>;
  1369. };
  1370. dmc: bus@38000 {
  1371. compatible = "simple-bus";
  1372. reg = <0x0 0x38000 0x0 0x400>;
  1373. #address-cells = <2>;
  1374. #size-cells = <2>;
  1375. ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
  1376. canvas: video-lut@48 {
  1377. compatible = "amlogic,canvas";
  1378. reg = <0x0 0x48 0x0 0x14>;
  1379. };
  1380. };
  1381. usb2_phy1: phy@3a000 {
  1382. compatible = "amlogic,g12a-usb2-phy";
  1383. reg = <0x0 0x3a000 0x0 0x2000>;
  1384. clocks = <&xtal>;
  1385. clock-names = "xtal";
  1386. resets = <&reset RESET_USB_PHY21>;
  1387. reset-names = "phy";
  1388. #phy-cells = <0>;
  1389. };
  1390. hiu: bus@3c000 {
  1391. compatible = "simple-bus";
  1392. reg = <0x0 0x3c000 0x0 0x1400>;
  1393. #address-cells = <2>;
  1394. #size-cells = <2>;
  1395. ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
  1396. hhi: system-controller@0 {
  1397. compatible = "amlogic,meson-gx-hhi-sysctrl",
  1398. "simple-mfd", "syscon";
  1399. reg = <0 0 0 0x400>;
  1400. clkc: clock-controller {
  1401. compatible = "amlogic,g12a-clkc";
  1402. #clock-cells = <1>;
  1403. clocks = <&xtal>;
  1404. clock-names = "xtal";
  1405. };
  1406. pwrc: power-controller {
  1407. compatible = "amlogic,meson-g12a-pwrc";
  1408. #power-domain-cells = <1>;
  1409. amlogic,ao-sysctrl = <&rti>;
  1410. resets = <&reset RESET_VIU>,
  1411. <&reset RESET_VENC>,
  1412. <&reset RESET_VCBUS>,
  1413. <&reset RESET_BT656>,
  1414. <&reset RESET_RDMA>,
  1415. <&reset RESET_VENCI>,
  1416. <&reset RESET_VENCP>,
  1417. <&reset RESET_VDAC>,
  1418. <&reset RESET_VDI6>,
  1419. <&reset RESET_VENCL>,
  1420. <&reset RESET_VID_LOCK>;
  1421. reset-names = "viu", "venc", "vcbus", "bt656",
  1422. "rdma", "venci", "vencp", "vdac",
  1423. "vdi6", "vencl", "vid_lock";
  1424. clocks = <&clkc CLKID_VPU>,
  1425. <&clkc CLKID_VAPB>;
  1426. clock-names = "vpu", "vapb";
  1427. /*
  1428. * VPU clocking is provided by two identical clock paths
  1429. * VPU_0 and VPU_1 muxed to a single clock by a glitch
  1430. * free mux to safely change frequency while running.
  1431. * Same for VAPB but with a final gate after the glitch free mux.
  1432. */
  1433. assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
  1434. <&clkc CLKID_VPU_0>,
  1435. <&clkc CLKID_VPU>, /* Glitch free mux */
  1436. <&clkc CLKID_VAPB_0_SEL>,
  1437. <&clkc CLKID_VAPB_0>,
  1438. <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
  1439. assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  1440. <0>, /* Do Nothing */
  1441. <&clkc CLKID_VPU_0>,
  1442. <&clkc CLKID_FCLK_DIV4>,
  1443. <0>, /* Do Nothing */
  1444. <&clkc CLKID_VAPB_0>;
  1445. assigned-clock-rates = <0>, /* Do Nothing */
  1446. <666666666>,
  1447. <0>, /* Do Nothing */
  1448. <0>, /* Do Nothing */
  1449. <250000000>,
  1450. <0>; /* Do Nothing */
  1451. };
  1452. };
  1453. };
  1454. usb3_pcie_phy: phy@46000 {
  1455. compatible = "amlogic,g12a-usb3-pcie-phy";
  1456. reg = <0x0 0x46000 0x0 0x2000>;
  1457. clocks = <&clkc CLKID_PCIE_PLL>;
  1458. clock-names = "ref_clk";
  1459. resets = <&reset RESET_PCIE_PHY>;
  1460. reset-names = "phy";
  1461. assigned-clocks = <&clkc CLKID_PCIE_PLL>;
  1462. assigned-clock-rates = <100000000>;
  1463. #phy-cells = <1>;
  1464. };
  1465. eth_phy: mdio-multiplexer@4c000 {
  1466. compatible = "amlogic,g12a-mdio-mux";
  1467. reg = <0x0 0x4c000 0x0 0xa4>;
  1468. clocks = <&clkc CLKID_ETH_PHY>,
  1469. <&xtal>,
  1470. <&clkc CLKID_MPLL_50M>;
  1471. clock-names = "pclk", "clkin0", "clkin1";
  1472. mdio-parent-bus = <&mdio0>;
  1473. #address-cells = <1>;
  1474. #size-cells = <0>;
  1475. ext_mdio: mdio@0 {
  1476. reg = <0>;
  1477. #address-cells = <1>;
  1478. #size-cells = <0>;
  1479. };
  1480. int_mdio: mdio@1 {
  1481. reg = <1>;
  1482. #address-cells = <1>;
  1483. #size-cells = <0>;
  1484. internal_ephy: ethernet_phy@8 {
  1485. compatible = "ethernet-phy-id0180.3301",
  1486. "ethernet-phy-ieee802.3-c22";
  1487. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  1488. reg = <8>;
  1489. max-speed = <100>;
  1490. };
  1491. };
  1492. };
  1493. };
  1494. aobus: bus@ff800000 {
  1495. compatible = "simple-bus";
  1496. reg = <0x0 0xff800000 0x0 0x100000>;
  1497. #address-cells = <2>;
  1498. #size-cells = <2>;
  1499. ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
  1500. rti: sys-ctrl@0 {
  1501. compatible = "amlogic,meson-gx-ao-sysctrl",
  1502. "simple-mfd", "syscon";
  1503. reg = <0x0 0x0 0x0 0x100>;
  1504. #address-cells = <2>;
  1505. #size-cells = <2>;
  1506. ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
  1507. clkc_AO: clock-controller {
  1508. compatible = "amlogic,meson-g12a-aoclkc";
  1509. #clock-cells = <1>;
  1510. #reset-cells = <1>;
  1511. clocks = <&xtal>, <&clkc CLKID_CLK81>;
  1512. clock-names = "xtal", "mpeg-clk";
  1513. };
  1514. ao_pinctrl: pinctrl@14 {
  1515. compatible = "amlogic,meson-g12a-aobus-pinctrl";
  1516. #address-cells = <2>;
  1517. #size-cells = <2>;
  1518. ranges;
  1519. gpio_ao: bank@14 {
  1520. reg = <0x0 0x14 0x0 0x8>,
  1521. <0x0 0x1c 0x0 0x8>,
  1522. <0x0 0x24 0x0 0x14>;
  1523. reg-names = "mux",
  1524. "ds",
  1525. "gpio";
  1526. gpio-controller;
  1527. #gpio-cells = <2>;
  1528. gpio-ranges = <&ao_pinctrl 0 0 15>;
  1529. };
  1530. i2c_ao_sck_pins: i2c_ao_sck_pins {
  1531. mux {
  1532. groups = "i2c_ao_sck";
  1533. function = "i2c_ao";
  1534. bias-disable;
  1535. drive-strength-microamp = <3000>;
  1536. };
  1537. };
  1538. i2c_ao_sda_pins: i2c_ao_sda {
  1539. mux {
  1540. groups = "i2c_ao_sda";
  1541. function = "i2c_ao";
  1542. bias-disable;
  1543. drive-strength-microamp = <3000>;
  1544. };
  1545. };
  1546. i2c_ao_sck_e_pins: i2c_ao_sck_e {
  1547. mux {
  1548. groups = "i2c_ao_sck_e";
  1549. function = "i2c_ao";
  1550. bias-disable;
  1551. drive-strength-microamp = <3000>;
  1552. };
  1553. };
  1554. i2c_ao_sda_e_pins: i2c_ao_sda_e {
  1555. mux {
  1556. groups = "i2c_ao_sda_e";
  1557. function = "i2c_ao";
  1558. bias-disable;
  1559. drive-strength-microamp = <3000>;
  1560. };
  1561. };
  1562. mclk0_ao_pins: mclk0-ao {
  1563. mux {
  1564. groups = "mclk0_ao";
  1565. function = "mclk0_ao";
  1566. bias-disable;
  1567. drive-strength-microamp = <3000>;
  1568. };
  1569. };
  1570. tdm_ao_b_din0_pins: tdm-ao-b-din0 {
  1571. mux {
  1572. groups = "tdm_ao_b_din0";
  1573. function = "tdm_ao_b";
  1574. bias-disable;
  1575. };
  1576. };
  1577. spdif_ao_out_pins: spdif-ao-out {
  1578. mux {
  1579. groups = "spdif_ao_out";
  1580. function = "spdif_ao_out";
  1581. drive-strength-microamp = <500>;
  1582. bias-disable;
  1583. };
  1584. };
  1585. tdm_ao_b_din1_pins: tdm-ao-b-din1 {
  1586. mux {
  1587. groups = "tdm_ao_b_din1";
  1588. function = "tdm_ao_b";
  1589. bias-disable;
  1590. };
  1591. };
  1592. tdm_ao_b_din2_pins: tdm-ao-b-din2 {
  1593. mux {
  1594. groups = "tdm_ao_b_din2";
  1595. function = "tdm_ao_b";
  1596. bias-disable;
  1597. };
  1598. };
  1599. tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
  1600. mux {
  1601. groups = "tdm_ao_b_dout0";
  1602. function = "tdm_ao_b";
  1603. bias-disable;
  1604. drive-strength-microamp = <3000>;
  1605. };
  1606. };
  1607. tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
  1608. mux {
  1609. groups = "tdm_ao_b_dout1";
  1610. function = "tdm_ao_b";
  1611. bias-disable;
  1612. drive-strength-microamp = <3000>;
  1613. };
  1614. };
  1615. tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
  1616. mux {
  1617. groups = "tdm_ao_b_dout2";
  1618. function = "tdm_ao_b";
  1619. bias-disable;
  1620. drive-strength-microamp = <3000>;
  1621. };
  1622. };
  1623. tdm_ao_b_fs_pins: tdm-ao-b-fs {
  1624. mux {
  1625. groups = "tdm_ao_b_fs";
  1626. function = "tdm_ao_b";
  1627. bias-disable;
  1628. drive-strength-microamp = <3000>;
  1629. };
  1630. };
  1631. tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
  1632. mux {
  1633. groups = "tdm_ao_b_sclk";
  1634. function = "tdm_ao_b";
  1635. bias-disable;
  1636. drive-strength-microamp = <3000>;
  1637. };
  1638. };
  1639. tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
  1640. mux {
  1641. groups = "tdm_ao_b_slv_fs";
  1642. function = "tdm_ao_b";
  1643. bias-disable;
  1644. };
  1645. };
  1646. tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
  1647. mux {
  1648. groups = "tdm_ao_b_slv_sclk";
  1649. function = "tdm_ao_b";
  1650. bias-disable;
  1651. };
  1652. };
  1653. uart_ao_a_pins: uart-a-ao {
  1654. mux {
  1655. groups = "uart_ao_a_tx",
  1656. "uart_ao_a_rx";
  1657. function = "uart_ao_a";
  1658. bias-disable;
  1659. };
  1660. };
  1661. uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
  1662. mux {
  1663. groups = "uart_ao_a_cts",
  1664. "uart_ao_a_rts";
  1665. function = "uart_ao_a";
  1666. bias-disable;
  1667. };
  1668. };
  1669. pwm_a_e_pins: pwm-a-e {
  1670. mux {
  1671. groups = "pwm_a_e";
  1672. function = "pwm_a_e";
  1673. bias-disable;
  1674. };
  1675. };
  1676. pwm_ao_a_pins: pwm-ao-a {
  1677. mux {
  1678. groups = "pwm_ao_a";
  1679. function = "pwm_ao_a";
  1680. bias-disable;
  1681. };
  1682. };
  1683. pwm_ao_b_pins: pwm-ao-b {
  1684. mux {
  1685. groups = "pwm_ao_b";
  1686. function = "pwm_ao_b";
  1687. bias-disable;
  1688. };
  1689. };
  1690. pwm_ao_c_4_pins: pwm-ao-c-4 {
  1691. mux {
  1692. groups = "pwm_ao_c_4";
  1693. function = "pwm_ao_c";
  1694. bias-disable;
  1695. };
  1696. };
  1697. pwm_ao_c_6_pins: pwm-ao-c-6 {
  1698. mux {
  1699. groups = "pwm_ao_c_6";
  1700. function = "pwm_ao_c";
  1701. bias-disable;
  1702. };
  1703. };
  1704. pwm_ao_d_5_pins: pwm-ao-d-5 {
  1705. mux {
  1706. groups = "pwm_ao_d_5";
  1707. function = "pwm_ao_d";
  1708. bias-disable;
  1709. };
  1710. };
  1711. pwm_ao_d_10_pins: pwm-ao-d-10 {
  1712. mux {
  1713. groups = "pwm_ao_d_10";
  1714. function = "pwm_ao_d";
  1715. bias-disable;
  1716. };
  1717. };
  1718. pwm_ao_d_e_pins: pwm-ao-d-e {
  1719. mux {
  1720. groups = "pwm_ao_d_e";
  1721. function = "pwm_ao_d";
  1722. };
  1723. };
  1724. remote_input_ao_pins: remote-input-ao {
  1725. mux {
  1726. groups = "remote_ao_input";
  1727. function = "remote_ao_input";
  1728. bias-disable;
  1729. };
  1730. };
  1731. };
  1732. };
  1733. vrtc: rtc@0a8 {
  1734. compatible = "amlogic,meson-vrtc";
  1735. reg = <0x0 0x000a8 0x0 0x4>;
  1736. };
  1737. cec_AO: cec@100 {
  1738. compatible = "amlogic,meson-gx-ao-cec";
  1739. reg = <0x0 0x00100 0x0 0x14>;
  1740. interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
  1741. clocks = <&clkc_AO CLKID_AO_CEC>;
  1742. clock-names = "core";
  1743. status = "disabled";
  1744. };
  1745. sec_AO: ao-secure@140 {
  1746. compatible = "amlogic,meson-gx-ao-secure", "syscon";
  1747. reg = <0x0 0x140 0x0 0x140>;
  1748. amlogic,has-chip-id;
  1749. };
  1750. cecb_AO: cec@280 {
  1751. compatible = "amlogic,meson-g12a-ao-cec";
  1752. reg = <0x0 0x00280 0x0 0x1c>;
  1753. interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
  1754. clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
  1755. clock-names = "oscin";
  1756. status = "disabled";
  1757. };
  1758. pwm_AO_cd: pwm@2000 {
  1759. compatible = "amlogic,meson-g12a-ao-pwm-cd";
  1760. reg = <0x0 0x2000 0x0 0x20>;
  1761. #pwm-cells = <3>;
  1762. status = "disabled";
  1763. };
  1764. uart_AO: serial@3000 {
  1765. compatible = "amlogic,meson-gx-uart",
  1766. "amlogic,meson-ao-uart";
  1767. reg = <0x0 0x3000 0x0 0x18>;
  1768. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  1769. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
  1770. clock-names = "xtal", "pclk", "baud";
  1771. status = "disabled";
  1772. };
  1773. uart_AO_B: serial@4000 {
  1774. compatible = "amlogic,meson-gx-uart",
  1775. "amlogic,meson-ao-uart";
  1776. reg = <0x0 0x4000 0x0 0x18>;
  1777. interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
  1778. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  1779. clock-names = "xtal", "pclk", "baud";
  1780. status = "disabled";
  1781. };
  1782. i2c_AO: i2c@5000 {
  1783. compatible = "amlogic,meson-axg-i2c";
  1784. status = "disabled";
  1785. reg = <0x0 0x05000 0x0 0x20>;
  1786. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  1787. #address-cells = <1>;
  1788. #size-cells = <0>;
  1789. clocks = <&clkc CLKID_I2C>;
  1790. };
  1791. pwm_AO_ab: pwm@7000 {
  1792. compatible = "amlogic,meson-g12a-ao-pwm-ab";
  1793. reg = <0x0 0x7000 0x0 0x20>;
  1794. #pwm-cells = <3>;
  1795. status = "disabled";
  1796. };
  1797. ir: ir@8000 {
  1798. compatible = "amlogic,meson-gxbb-ir";
  1799. reg = <0x0 0x8000 0x0 0x20>;
  1800. interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
  1801. status = "disabled";
  1802. };
  1803. saradc: adc@9000 {
  1804. compatible = "amlogic,meson-g12a-saradc",
  1805. "amlogic,meson-saradc";
  1806. reg = <0x0 0x9000 0x0 0x48>;
  1807. #io-channel-cells = <1>;
  1808. interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
  1809. clocks = <&xtal>,
  1810. <&clkc_AO CLKID_AO_SAR_ADC>,
  1811. <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
  1812. <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
  1813. clock-names = "clkin", "core", "adc_clk", "adc_sel";
  1814. status = "disabled";
  1815. };
  1816. };
  1817. vdec: video-decoder@ff620000 {
  1818. compatible = "amlogic,g12a-vdec";
  1819. reg = <0x0 0xff620000 0x0 0x10000>,
  1820. <0x0 0xffd0e180 0x0 0xe4>;
  1821. reg-names = "dos", "esparser";
  1822. interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
  1823. <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
  1824. interrupt-names = "vdec", "esparser";
  1825. amlogic,ao-sysctrl = <&rti>;
  1826. amlogic,canvas = <&canvas>;
  1827. clocks = <&clkc CLKID_PARSER>,
  1828. <&clkc CLKID_DOS>,
  1829. <&clkc CLKID_VDEC_1>,
  1830. <&clkc CLKID_VDEC_HEVC>,
  1831. <&clkc CLKID_VDEC_HEVCF>;
  1832. clock-names = "dos_parser", "dos", "vdec_1",
  1833. "vdec_hevc", "vdec_hevcf";
  1834. resets = <&reset RESET_PARSER>;
  1835. reset-names = "esparser";
  1836. };
  1837. vpu: vpu@ff900000 {
  1838. compatible = "amlogic,meson-g12a-vpu";
  1839. reg = <0x0 0xff900000 0x0 0x100000>,
  1840. <0x0 0xff63c000 0x0 0x1000>;
  1841. reg-names = "vpu", "hhi";
  1842. interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
  1843. #address-cells = <1>;
  1844. #size-cells = <0>;
  1845. amlogic,canvas = <&canvas>;
  1846. /* CVBS VDAC output port */
  1847. cvbs_vdac_port: port@0 {
  1848. reg = <0>;
  1849. };
  1850. /* HDMI-TX output port */
  1851. hdmi_tx_port: port@1 {
  1852. reg = <1>;
  1853. hdmi_tx_out: endpoint {
  1854. remote-endpoint = <&hdmi_tx_in>;
  1855. };
  1856. };
  1857. };
  1858. gic: interrupt-controller@ffc01000 {
  1859. compatible = "arm,gic-400";
  1860. reg = <0x0 0xffc01000 0 0x1000>,
  1861. <0x0 0xffc02000 0 0x2000>,
  1862. <0x0 0xffc04000 0 0x2000>,
  1863. <0x0 0xffc06000 0 0x2000>;
  1864. interrupt-controller;
  1865. interrupts = <GIC_PPI 9
  1866. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  1867. #interrupt-cells = <3>;
  1868. #address-cells = <0>;
  1869. };
  1870. cbus: bus@ffd00000 {
  1871. compatible = "simple-bus";
  1872. reg = <0x0 0xffd00000 0x0 0x100000>;
  1873. #address-cells = <2>;
  1874. #size-cells = <2>;
  1875. ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
  1876. reset: reset-controller@1004 {
  1877. compatible = "amlogic,meson-axg-reset";
  1878. reg = <0x0 0x1004 0x0 0x9c>;
  1879. #reset-cells = <1>;
  1880. };
  1881. gpio_intc: interrupt-controller@f080 {
  1882. compatible = "amlogic,meson-g12a-gpio-intc",
  1883. "amlogic,meson-gpio-intc";
  1884. reg = <0x0 0xf080 0x0 0x10>;
  1885. interrupt-controller;
  1886. #interrupt-cells = <2>;
  1887. amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
  1888. };
  1889. spicc0: spi@13000 {
  1890. compatible = "amlogic,meson-g12a-spicc";
  1891. reg = <0x0 0x13000 0x0 0x44>;
  1892. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  1893. clocks = <&clkc CLKID_SPICC0>,
  1894. <&clkc CLKID_SPICC0_SCLK>;
  1895. clock-names = "core", "pclk";
  1896. #address-cells = <1>;
  1897. #size-cells = <0>;
  1898. status = "disabled";
  1899. };
  1900. spicc1: spi@15000 {
  1901. compatible = "amlogic,meson-g12a-spicc";
  1902. reg = <0x0 0x15000 0x0 0x44>;
  1903. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  1904. clocks = <&clkc CLKID_SPICC1>,
  1905. <&clkc CLKID_SPICC1_SCLK>;
  1906. clock-names = "core", "pclk";
  1907. #address-cells = <1>;
  1908. #size-cells = <0>;
  1909. status = "disabled";
  1910. };
  1911. spifc: spi@14000 {
  1912. compatible = "amlogic,meson-gxbb-spifc";
  1913. status = "disabled";
  1914. reg = <0x0 0x14000 0x0 0x80>;
  1915. #address-cells = <1>;
  1916. #size-cells = <0>;
  1917. clocks = <&clkc CLKID_CLK81>;
  1918. };
  1919. pwm_ef: pwm@19000 {
  1920. compatible = "amlogic,meson-g12a-ee-pwm";
  1921. reg = <0x0 0x19000 0x0 0x20>;
  1922. #pwm-cells = <3>;
  1923. status = "disabled";
  1924. };
  1925. pwm_cd: pwm@1a000 {
  1926. compatible = "amlogic,meson-g12a-ee-pwm";
  1927. reg = <0x0 0x1a000 0x0 0x20>;
  1928. #pwm-cells = <3>;
  1929. status = "disabled";
  1930. };
  1931. pwm_ab: pwm@1b000 {
  1932. compatible = "amlogic,meson-g12a-ee-pwm";
  1933. reg = <0x0 0x1b000 0x0 0x20>;
  1934. #pwm-cells = <3>;
  1935. status = "disabled";
  1936. };
  1937. i2c3: i2c@1c000 {
  1938. compatible = "amlogic,meson-axg-i2c";
  1939. status = "disabled";
  1940. reg = <0x0 0x1c000 0x0 0x20>;
  1941. interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
  1942. #address-cells = <1>;
  1943. #size-cells = <0>;
  1944. clocks = <&clkc CLKID_I2C>;
  1945. };
  1946. i2c2: i2c@1d000 {
  1947. compatible = "amlogic,meson-axg-i2c";
  1948. status = "disabled";
  1949. reg = <0x0 0x1d000 0x0 0x20>;
  1950. interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
  1951. #address-cells = <1>;
  1952. #size-cells = <0>;
  1953. clocks = <&clkc CLKID_I2C>;
  1954. };
  1955. i2c1: i2c@1e000 {
  1956. compatible = "amlogic,meson-axg-i2c";
  1957. status = "disabled";
  1958. reg = <0x0 0x1e000 0x0 0x20>;
  1959. interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
  1960. #address-cells = <1>;
  1961. #size-cells = <0>;
  1962. clocks = <&clkc CLKID_I2C>;
  1963. };
  1964. i2c0: i2c@1f000 {
  1965. compatible = "amlogic,meson-axg-i2c";
  1966. status = "disabled";
  1967. reg = <0x0 0x1f000 0x0 0x20>;
  1968. interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
  1969. #address-cells = <1>;
  1970. #size-cells = <0>;
  1971. clocks = <&clkc CLKID_I2C>;
  1972. };
  1973. clk_msr: clock-measure@18000 {
  1974. compatible = "amlogic,meson-g12a-clk-measure";
  1975. reg = <0x0 0x18000 0x0 0x10>;
  1976. };
  1977. uart_C: serial@22000 {
  1978. compatible = "amlogic,meson-gx-uart";
  1979. reg = <0x0 0x22000 0x0 0x18>;
  1980. interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
  1981. clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
  1982. clock-names = "xtal", "pclk", "baud";
  1983. status = "disabled";
  1984. };
  1985. uart_B: serial@23000 {
  1986. compatible = "amlogic,meson-gx-uart";
  1987. reg = <0x0 0x23000 0x0 0x18>;
  1988. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  1989. clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  1990. clock-names = "xtal", "pclk", "baud";
  1991. status = "disabled";
  1992. };
  1993. uart_A: serial@24000 {
  1994. compatible = "amlogic,meson-gx-uart";
  1995. reg = <0x0 0x24000 0x0 0x18>;
  1996. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  1997. clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  1998. clock-names = "xtal", "pclk", "baud";
  1999. status = "disabled";
  2000. };
  2001. };
  2002. sd_emmc_a: sd@ffe03000 {
  2003. compatible = "amlogic,meson-axg-mmc";
  2004. reg = <0x0 0xffe03000 0x0 0x800>;
  2005. interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
  2006. status = "disabled";
  2007. clocks = <&clkc CLKID_SD_EMMC_A>,
  2008. <&clkc CLKID_SD_EMMC_A_CLK0>,
  2009. <&clkc CLKID_FCLK_DIV2>;
  2010. clock-names = "core", "clkin0", "clkin1";
  2011. resets = <&reset RESET_SD_EMMC_A>;
  2012. };
  2013. sd_emmc_b: sd@ffe05000 {
  2014. compatible = "amlogic,meson-axg-mmc";
  2015. reg = <0x0 0xffe05000 0x0 0x800>;
  2016. interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
  2017. status = "disabled";
  2018. clocks = <&clkc CLKID_SD_EMMC_B>,
  2019. <&clkc CLKID_SD_EMMC_B_CLK0>,
  2020. <&clkc CLKID_FCLK_DIV2>;
  2021. clock-names = "core", "clkin0", "clkin1";
  2022. resets = <&reset RESET_SD_EMMC_B>;
  2023. };
  2024. sd_emmc_c: mmc@ffe07000 {
  2025. compatible = "amlogic,meson-axg-mmc";
  2026. reg = <0x0 0xffe07000 0x0 0x800>;
  2027. interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
  2028. status = "disabled";
  2029. clocks = <&clkc CLKID_SD_EMMC_C>,
  2030. <&clkc CLKID_SD_EMMC_C_CLK0>,
  2031. <&clkc CLKID_FCLK_DIV2>;
  2032. clock-names = "core", "clkin0", "clkin1";
  2033. resets = <&reset RESET_SD_EMMC_C>;
  2034. };
  2035. usb: usb@ffe09000 {
  2036. status = "disabled";
  2037. compatible = "amlogic,meson-g12a-usb-ctrl";
  2038. reg = <0x0 0xffe09000 0x0 0xa0>;
  2039. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  2040. #address-cells = <2>;
  2041. #size-cells = <2>;
  2042. ranges;
  2043. clocks = <&clkc CLKID_USB>;
  2044. resets = <&reset RESET_USB>;
  2045. dr_mode = "otg";
  2046. phys = <&usb2_phy0>, <&usb2_phy1>,
  2047. <&usb3_pcie_phy PHY_TYPE_USB3>;
  2048. phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
  2049. dwc2: usb@ff400000 {
  2050. compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
  2051. reg = <0x0 0xff400000 0x0 0x40000>;
  2052. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  2053. clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
  2054. clock-names = "ddr";
  2055. phys = <&usb2_phy1>;
  2056. phy-names = "usb2-phy";
  2057. dr_mode = "peripheral";
  2058. g-rx-fifo-size = <192>;
  2059. g-np-tx-fifo-size = <128>;
  2060. g-tx-fifo-size = <128 128 16 16 16>;
  2061. };
  2062. dwc3: usb@ff500000 {
  2063. compatible = "snps,dwc3";
  2064. reg = <0x0 0xff500000 0x0 0x100000>;
  2065. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  2066. dr_mode = "host";
  2067. snps,dis_u2_susphy_quirk;
  2068. snps,quirk-frame-length-adjustment;
  2069. snps,parkmode-disable-ss-quirk;
  2070. };
  2071. };
  2072. mali: gpu@ffe40000 {
  2073. compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
  2074. reg = <0x0 0xffe40000 0x0 0x40000>;
  2075. interrupt-parent = <&gic>;
  2076. interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
  2077. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  2078. <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
  2079. interrupt-names = "job", "mmu", "gpu";
  2080. clocks = <&clkc CLKID_MALI>;
  2081. resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
  2082. /*
  2083. * Mali clocking is provided by two identical clock paths
  2084. * MALI_0 and MALI_1 muxed to a single clock by a glitch
  2085. * free mux to safely change frequency while running.
  2086. */
  2087. assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
  2088. <&clkc CLKID_MALI_0>,
  2089. <&clkc CLKID_MALI>; /* Glitch free mux */
  2090. assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
  2091. <0>, /* Do Nothing */
  2092. <&clkc CLKID_MALI_0>;
  2093. assigned-clock-rates = <0>, /* Do Nothing */
  2094. <800000000>,
  2095. <0>; /* Do Nothing */
  2096. #cooling-cells = <2>;
  2097. };
  2098. };
  2099. timer {
  2100. compatible = "arm,armv8-timer";
  2101. interrupts = <GIC_PPI 13
  2102. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  2103. <GIC_PPI 14
  2104. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  2105. <GIC_PPI 11
  2106. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  2107. <GIC_PPI 10
  2108. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  2109. arm,no-tick-in-suspend;
  2110. };
  2111. xtal: xtal-clk {
  2112. compatible = "fixed-clock";
  2113. clock-frequency = <24000000>;
  2114. clock-output-names = "xtal";
  2115. #clock-cells = <0>;
  2116. };
  2117. };