meson-gxm.dtsi 3.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2016 Endless Computers, Inc.
  4. * Author: Carlo Caione <carlo@endlessm.com>
  5. */
  6. #include "meson-gxl.dtsi"
  7. / {
  8. compatible = "amlogic,meson-gxm";
  9. cpus {
  10. cpu-map {
  11. cluster0 {
  12. core0 {
  13. cpu = <&cpu0>;
  14. };
  15. core1 {
  16. cpu = <&cpu1>;
  17. };
  18. core2 {
  19. cpu = <&cpu2>;
  20. };
  21. core3 {
  22. cpu = <&cpu3>;
  23. };
  24. };
  25. cluster1 {
  26. core0 {
  27. cpu = <&cpu4>;
  28. };
  29. core1 {
  30. cpu = <&cpu5>;
  31. };
  32. core2 {
  33. cpu = <&cpu6>;
  34. };
  35. core3 {
  36. cpu = <&cpu7>;
  37. };
  38. };
  39. };
  40. cpu4: cpu@100 {
  41. device_type = "cpu";
  42. compatible = "arm,cortex-a53";
  43. reg = <0x0 0x100>;
  44. enable-method = "psci";
  45. next-level-cache = <&l2>;
  46. clocks = <&scpi_dvfs 1>;
  47. };
  48. cpu5: cpu@101 {
  49. device_type = "cpu";
  50. compatible = "arm,cortex-a53";
  51. reg = <0x0 0x101>;
  52. enable-method = "psci";
  53. next-level-cache = <&l2>;
  54. clocks = <&scpi_dvfs 1>;
  55. };
  56. cpu6: cpu@102 {
  57. device_type = "cpu";
  58. compatible = "arm,cortex-a53";
  59. reg = <0x0 0x102>;
  60. enable-method = "psci";
  61. next-level-cache = <&l2>;
  62. clocks = <&scpi_dvfs 1>;
  63. };
  64. cpu7: cpu@103 {
  65. device_type = "cpu";
  66. compatible = "arm,cortex-a53";
  67. reg = <0x0 0x103>;
  68. enable-method = "psci";
  69. next-level-cache = <&l2>;
  70. clocks = <&scpi_dvfs 1>;
  71. };
  72. };
  73. };
  74. &apb {
  75. usb2_phy2: phy@78040 {
  76. compatible = "amlogic,meson-gxl-usb2-phy";
  77. #phy-cells = <0>;
  78. reg = <0x0 0x78040 0x0 0x20>;
  79. clocks = <&clkc CLKID_USB>;
  80. clock-names = "phy";
  81. resets = <&reset RESET_USB_OTG>;
  82. reset-names = "phy";
  83. status = "okay";
  84. };
  85. mali: gpu@c0000 {
  86. compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
  87. reg = <0x0 0xc0000 0x0 0x40000>;
  88. interrupt-parent = <&gic>;
  89. interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
  90. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  91. <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
  92. interrupt-names = "job", "mmu", "gpu";
  93. clocks = <&clkc CLKID_MALI>;
  94. resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
  95. /*
  96. * Mali clocking is provided by two identical clock paths
  97. * MALI_0 and MALI_1 muxed to a single clock by a glitch
  98. * free mux to safely change frequency while running.
  99. */
  100. assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
  101. <&clkc CLKID_MALI_0>,
  102. <&clkc CLKID_MALI>; /* Glitch free mux */
  103. assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  104. <0>, /* Do Nothing */
  105. <&clkc CLKID_MALI_0>;
  106. assigned-clock-rates = <0>, /* Do Nothing */
  107. <666666666>,
  108. <0>; /* Do Nothing */
  109. };
  110. };
  111. &clkc_AO {
  112. compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
  113. };
  114. &saradc {
  115. compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
  116. };
  117. &scpi_dvfs {
  118. clock-indices = <0 1>;
  119. clock-output-names = "vbig", "vlittle";
  120. };
  121. &vpu {
  122. compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
  123. };
  124. &hdmi_tx {
  125. compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
  126. };
  127. &dwc3 {
  128. phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
  129. };
  130. &vdec {
  131. compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec";
  132. };