meson-gxl.dtsi 16 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2016 Endless Computers, Inc.
  4. * Author: Carlo Caione <carlo@endlessm.com>
  5. */
  6. #include "meson-gx.dtsi"
  7. #include <dt-bindings/clock/gxbb-clkc.h>
  8. #include <dt-bindings/clock/gxbb-aoclkc.h>
  9. #include <dt-bindings/gpio/meson-gxl-gpio.h>
  10. #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  11. / {
  12. compatible = "amlogic,meson-gxl";
  13. soc {
  14. usb0: usb@c9000000 {
  15. status = "disabled";
  16. compatible = "amlogic,meson-gxl-dwc3";
  17. #address-cells = <2>;
  18. #size-cells = <2>;
  19. ranges;
  20. clocks = <&clkc CLKID_USB>;
  21. clock-names = "usb_general";
  22. resets = <&reset RESET_USB_OTG>;
  23. reset-names = "usb_otg";
  24. dwc3: dwc3@c9000000 {
  25. compatible = "snps,dwc3";
  26. reg = <0x0 0xc9000000 0x0 0x100000>;
  27. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  28. dr_mode = "host";
  29. maximum-speed = "high-speed";
  30. snps,dis_u2_susphy_quirk;
  31. phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
  32. };
  33. };
  34. crypto: crypto@c883e000 {
  35. compatible = "amlogic,gxl-crypto";
  36. reg = <0x0 0xc883e000 0x0 0x36>;
  37. interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
  38. <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
  39. clocks = <&clkc CLKID_BLKMV>;
  40. clock-names = "blkmv";
  41. status = "okay";
  42. };
  43. };
  44. };
  45. &apb {
  46. usb2_phy0: phy@78000 {
  47. compatible = "amlogic,meson-gxl-usb2-phy";
  48. #phy-cells = <0>;
  49. reg = <0x0 0x78000 0x0 0x20>;
  50. clocks = <&clkc CLKID_USB>;
  51. clock-names = "phy";
  52. resets = <&reset RESET_USB_OTG>;
  53. reset-names = "phy";
  54. status = "okay";
  55. };
  56. usb2_phy1: phy@78020 {
  57. compatible = "amlogic,meson-gxl-usb2-phy";
  58. #phy-cells = <0>;
  59. reg = <0x0 0x78020 0x0 0x20>;
  60. clocks = <&clkc CLKID_USB>;
  61. clock-names = "phy";
  62. resets = <&reset RESET_USB_OTG>;
  63. reset-names = "phy";
  64. status = "okay";
  65. };
  66. usb3_phy: phy@78080 {
  67. compatible = "amlogic,meson-gxl-usb3-phy";
  68. #phy-cells = <0>;
  69. reg = <0x0 0x78080 0x0 0x20>;
  70. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  71. clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
  72. clock-names = "phy", "peripheral";
  73. resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
  74. reset-names = "phy", "peripheral";
  75. status = "okay";
  76. };
  77. };
  78. &efuse {
  79. clocks = <&clkc CLKID_EFUSE>;
  80. };
  81. &ethmac {
  82. clocks = <&clkc CLKID_ETH>,
  83. <&clkc CLKID_FCLK_DIV2>,
  84. <&clkc CLKID_MPLL2>;
  85. clock-names = "stmmaceth", "clkin0", "clkin1";
  86. mdio0: mdio {
  87. #address-cells = <1>;
  88. #size-cells = <0>;
  89. compatible = "snps,dwmac-mdio";
  90. };
  91. };
  92. &aobus {
  93. pinctrl_aobus: pinctrl@14 {
  94. compatible = "amlogic,meson-gxl-aobus-pinctrl";
  95. #address-cells = <2>;
  96. #size-cells = <2>;
  97. ranges;
  98. gpio_ao: bank@14 {
  99. reg = <0x0 0x00014 0x0 0x8>,
  100. <0x0 0x0002c 0x0 0x4>,
  101. <0x0 0x00024 0x0 0x8>;
  102. reg-names = "mux", "pull", "gpio";
  103. gpio-controller;
  104. #gpio-cells = <2>;
  105. gpio-ranges = <&pinctrl_aobus 0 0 14>;
  106. };
  107. uart_ao_a_pins: uart_ao_a {
  108. mux {
  109. groups = "uart_tx_ao_a", "uart_rx_ao_a";
  110. function = "uart_ao";
  111. bias-disable;
  112. };
  113. };
  114. uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
  115. mux {
  116. groups = "uart_cts_ao_a",
  117. "uart_rts_ao_a";
  118. function = "uart_ao";
  119. bias-disable;
  120. };
  121. };
  122. uart_ao_b_pins: uart_ao_b {
  123. mux {
  124. groups = "uart_tx_ao_b", "uart_rx_ao_b";
  125. function = "uart_ao_b";
  126. bias-disable;
  127. };
  128. };
  129. uart_ao_b_0_1_pins: uart_ao_b_0_1 {
  130. mux {
  131. groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
  132. function = "uart_ao_b";
  133. bias-disable;
  134. };
  135. };
  136. uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
  137. mux {
  138. groups = "uart_cts_ao_b",
  139. "uart_rts_ao_b";
  140. function = "uart_ao_b";
  141. bias-disable;
  142. };
  143. };
  144. remote_input_ao_pins: remote_input_ao {
  145. mux {
  146. groups = "remote_input_ao";
  147. function = "remote_input_ao";
  148. bias-disable;
  149. };
  150. };
  151. i2c_ao_pins: i2c_ao {
  152. mux {
  153. groups = "i2c_sck_ao",
  154. "i2c_sda_ao";
  155. function = "i2c_ao";
  156. bias-disable;
  157. };
  158. };
  159. pwm_ao_a_3_pins: pwm_ao_a_3 {
  160. mux {
  161. groups = "pwm_ao_a_3";
  162. function = "pwm_ao_a";
  163. bias-disable;
  164. };
  165. };
  166. pwm_ao_a_8_pins: pwm_ao_a_8 {
  167. mux {
  168. groups = "pwm_ao_a_8";
  169. function = "pwm_ao_a";
  170. bias-disable;
  171. };
  172. };
  173. pwm_ao_b_pins: pwm_ao_b {
  174. mux {
  175. groups = "pwm_ao_b";
  176. function = "pwm_ao_b";
  177. bias-disable;
  178. };
  179. };
  180. pwm_ao_b_6_pins: pwm_ao_b_6 {
  181. mux {
  182. groups = "pwm_ao_b_6";
  183. function = "pwm_ao_b";
  184. bias-disable;
  185. };
  186. };
  187. i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
  188. mux {
  189. groups = "i2s_out_ch23_ao";
  190. function = "i2s_out_ao";
  191. bias-disable;
  192. };
  193. };
  194. i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
  195. mux {
  196. groups = "i2s_out_ch45_ao";
  197. function = "i2s_out_ao";
  198. bias-disable;
  199. };
  200. };
  201. spdif_out_ao_6_pins: spdif_out_ao_6 {
  202. mux {
  203. groups = "spdif_out_ao_6";
  204. function = "spdif_out_ao";
  205. bias-disable;
  206. };
  207. };
  208. spdif_out_ao_9_pins: spdif_out_ao_9 {
  209. mux {
  210. groups = "spdif_out_ao_9";
  211. function = "spdif_out_ao";
  212. bias-disable;
  213. };
  214. };
  215. ao_cec_pins: ao_cec {
  216. mux {
  217. groups = "ao_cec";
  218. function = "cec_ao";
  219. bias-disable;
  220. };
  221. };
  222. ee_cec_pins: ee_cec {
  223. mux {
  224. groups = "ee_cec";
  225. function = "cec_ao";
  226. bias-disable;
  227. };
  228. };
  229. };
  230. };
  231. &cec_AO {
  232. clocks = <&clkc_AO CLKID_AO_CEC_32K>;
  233. clock-names = "core";
  234. };
  235. &clkc_AO {
  236. compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
  237. clocks = <&xtal>, <&clkc CLKID_CLK81>;
  238. clock-names = "xtal", "mpeg-clk";
  239. };
  240. &gpio_intc {
  241. compatible = "amlogic,meson-gpio-intc",
  242. "amlogic,meson-gxl-gpio-intc";
  243. status = "okay";
  244. };
  245. &hdmi_tx {
  246. compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
  247. resets = <&reset RESET_HDMITX_CAPB3>,
  248. <&reset RESET_HDMI_SYSTEM_RESET>,
  249. <&reset RESET_HDMI_TX>;
  250. reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
  251. clocks = <&clkc CLKID_HDMI_PCLK>,
  252. <&clkc CLKID_CLK81>,
  253. <&clkc CLKID_GCLK_VENCI_INT0>;
  254. clock-names = "isfr", "iahb", "venci";
  255. };
  256. &sysctrl {
  257. clkc: clock-controller {
  258. compatible = "amlogic,gxl-clkc";
  259. #clock-cells = <1>;
  260. clocks = <&xtal>;
  261. clock-names = "xtal";
  262. };
  263. };
  264. &i2c_A {
  265. clocks = <&clkc CLKID_I2C>;
  266. };
  267. &i2c_AO {
  268. clocks = <&clkc CLKID_AO_I2C>;
  269. };
  270. &i2c_B {
  271. clocks = <&clkc CLKID_I2C>;
  272. };
  273. &i2c_C {
  274. clocks = <&clkc CLKID_I2C>;
  275. };
  276. &periphs {
  277. pinctrl_periphs: pinctrl@4b0 {
  278. compatible = "amlogic,meson-gxl-periphs-pinctrl";
  279. #address-cells = <2>;
  280. #size-cells = <2>;
  281. ranges;
  282. gpio: bank@4b0 {
  283. reg = <0x0 0x004b0 0x0 0x28>,
  284. <0x0 0x004e8 0x0 0x14>,
  285. <0x0 0x00520 0x0 0x14>,
  286. <0x0 0x00430 0x0 0x40>;
  287. reg-names = "mux", "pull", "pull-enable", "gpio";
  288. gpio-controller;
  289. #gpio-cells = <2>;
  290. gpio-ranges = <&pinctrl_periphs 0 0 100>;
  291. };
  292. emmc_pins: emmc {
  293. mux-0 {
  294. groups = "emmc_nand_d07",
  295. "emmc_cmd";
  296. function = "emmc";
  297. bias-pull-up;
  298. };
  299. mux-1 {
  300. groups = "emmc_clk";
  301. function = "emmc";
  302. bias-disable;
  303. };
  304. };
  305. emmc_ds_pins: emmc-ds {
  306. mux {
  307. groups = "emmc_ds";
  308. function = "emmc";
  309. bias-pull-down;
  310. };
  311. };
  312. emmc_clk_gate_pins: emmc_clk_gate {
  313. mux {
  314. groups = "BOOT_8";
  315. function = "gpio_periphs";
  316. bias-pull-down;
  317. };
  318. };
  319. nor_pins: nor {
  320. mux {
  321. groups = "nor_d",
  322. "nor_q",
  323. "nor_c",
  324. "nor_cs";
  325. function = "nor";
  326. bias-disable;
  327. };
  328. };
  329. spi_pins: spi-pins {
  330. mux {
  331. groups = "spi_miso",
  332. "spi_mosi",
  333. "spi_sclk";
  334. function = "spi";
  335. bias-disable;
  336. };
  337. };
  338. spi_ss0_pins: spi-ss0 {
  339. mux {
  340. groups = "spi_ss0";
  341. function = "spi";
  342. bias-disable;
  343. };
  344. };
  345. sdcard_pins: sdcard {
  346. mux-0 {
  347. groups = "sdcard_d0",
  348. "sdcard_d1",
  349. "sdcard_d2",
  350. "sdcard_d3",
  351. "sdcard_cmd";
  352. function = "sdcard";
  353. bias-pull-up;
  354. };
  355. mux-1 {
  356. groups = "sdcard_clk";
  357. function = "sdcard";
  358. bias-disable;
  359. };
  360. };
  361. sdcard_clk_gate_pins: sdcard_clk_gate {
  362. mux {
  363. groups = "CARD_2";
  364. function = "gpio_periphs";
  365. bias-pull-down;
  366. };
  367. };
  368. sdio_pins: sdio {
  369. mux-0 {
  370. groups = "sdio_d0",
  371. "sdio_d1",
  372. "sdio_d2",
  373. "sdio_d3",
  374. "sdio_cmd";
  375. function = "sdio";
  376. bias-pull-up;
  377. };
  378. mux-1 {
  379. groups = "sdio_clk";
  380. function = "sdio";
  381. bias-disable;
  382. };
  383. };
  384. sdio_clk_gate_pins: sdio_clk_gate {
  385. mux {
  386. groups = "GPIOX_4";
  387. function = "gpio_periphs";
  388. bias-pull-down;
  389. };
  390. };
  391. sdio_irq_pins: sdio_irq {
  392. mux {
  393. groups = "sdio_irq";
  394. function = "sdio";
  395. bias-disable;
  396. };
  397. };
  398. uart_a_pins: uart_a {
  399. mux {
  400. groups = "uart_tx_a",
  401. "uart_rx_a";
  402. function = "uart_a";
  403. bias-disable;
  404. };
  405. };
  406. uart_a_cts_rts_pins: uart_a_cts_rts {
  407. mux {
  408. groups = "uart_cts_a",
  409. "uart_rts_a";
  410. function = "uart_a";
  411. bias-disable;
  412. };
  413. };
  414. uart_b_pins: uart_b {
  415. mux {
  416. groups = "uart_tx_b",
  417. "uart_rx_b";
  418. function = "uart_b";
  419. bias-disable;
  420. };
  421. };
  422. uart_b_cts_rts_pins: uart_b_cts_rts {
  423. mux {
  424. groups = "uart_cts_b",
  425. "uart_rts_b";
  426. function = "uart_b";
  427. bias-disable;
  428. };
  429. };
  430. uart_c_pins: uart_c {
  431. mux {
  432. groups = "uart_tx_c",
  433. "uart_rx_c";
  434. function = "uart_c";
  435. bias-disable;
  436. };
  437. };
  438. uart_c_cts_rts_pins: uart_c_cts_rts {
  439. mux {
  440. groups = "uart_cts_c",
  441. "uart_rts_c";
  442. function = "uart_c";
  443. bias-disable;
  444. };
  445. };
  446. i2c_a_pins: i2c_a {
  447. mux {
  448. groups = "i2c_sck_a",
  449. "i2c_sda_a";
  450. function = "i2c_a";
  451. bias-disable;
  452. };
  453. };
  454. i2c_b_pins: i2c_b {
  455. mux {
  456. groups = "i2c_sck_b",
  457. "i2c_sda_b";
  458. function = "i2c_b";
  459. bias-disable;
  460. };
  461. };
  462. i2c_c_pins: i2c_c {
  463. mux {
  464. groups = "i2c_sck_c",
  465. "i2c_sda_c";
  466. function = "i2c_c";
  467. bias-disable;
  468. };
  469. };
  470. i2c_c_dv18_pins: i2c_c_dv18 {
  471. mux {
  472. groups = "i2c_sck_c_dv19",
  473. "i2c_sda_c_dv18";
  474. function = "i2c_c";
  475. bias-disable;
  476. };
  477. };
  478. eth_pins: eth_c {
  479. mux {
  480. groups = "eth_mdio",
  481. "eth_mdc",
  482. "eth_clk_rx_clk",
  483. "eth_rx_dv",
  484. "eth_rxd0",
  485. "eth_rxd1",
  486. "eth_rxd2",
  487. "eth_rxd3",
  488. "eth_rgmii_tx_clk",
  489. "eth_tx_en",
  490. "eth_txd0",
  491. "eth_txd1",
  492. "eth_txd2",
  493. "eth_txd3";
  494. function = "eth";
  495. bias-disable;
  496. };
  497. };
  498. eth_link_led_pins: eth_link_led {
  499. mux {
  500. groups = "eth_link_led";
  501. function = "eth_led";
  502. bias-disable;
  503. };
  504. };
  505. eth_act_led_pins: eth_act_led {
  506. mux {
  507. groups = "eth_act_led";
  508. function = "eth_led";
  509. };
  510. };
  511. pwm_a_pins: pwm_a {
  512. mux {
  513. groups = "pwm_a";
  514. function = "pwm_a";
  515. bias-disable;
  516. };
  517. };
  518. pwm_b_pins: pwm_b {
  519. mux {
  520. groups = "pwm_b";
  521. function = "pwm_b";
  522. bias-disable;
  523. };
  524. };
  525. pwm_c_pins: pwm_c {
  526. mux {
  527. groups = "pwm_c";
  528. function = "pwm_c";
  529. bias-disable;
  530. };
  531. };
  532. pwm_d_pins: pwm_d {
  533. mux {
  534. groups = "pwm_d";
  535. function = "pwm_d";
  536. bias-disable;
  537. };
  538. };
  539. pwm_e_pins: pwm_e {
  540. mux {
  541. groups = "pwm_e";
  542. function = "pwm_e";
  543. bias-disable;
  544. };
  545. };
  546. pwm_f_clk_pins: pwm_f_clk {
  547. mux {
  548. groups = "pwm_f_clk";
  549. function = "pwm_f";
  550. bias-disable;
  551. };
  552. };
  553. pwm_f_x_pins: pwm_f_x {
  554. mux {
  555. groups = "pwm_f_x";
  556. function = "pwm_f";
  557. bias-disable;
  558. };
  559. };
  560. hdmi_hpd_pins: hdmi_hpd {
  561. mux {
  562. groups = "hdmi_hpd";
  563. function = "hdmi_hpd";
  564. bias-disable;
  565. };
  566. };
  567. hdmi_i2c_pins: hdmi_i2c {
  568. mux {
  569. groups = "hdmi_sda", "hdmi_scl";
  570. function = "hdmi_i2c";
  571. bias-disable;
  572. };
  573. };
  574. i2s_am_clk_pins: i2s_am_clk {
  575. mux {
  576. groups = "i2s_am_clk";
  577. function = "i2s_out";
  578. bias-disable;
  579. };
  580. };
  581. i2s_out_ao_clk_pins: i2s_out_ao_clk {
  582. mux {
  583. groups = "i2s_out_ao_clk";
  584. function = "i2s_out";
  585. bias-disable;
  586. };
  587. };
  588. i2s_out_lr_clk_pins: i2s_out_lr_clk {
  589. mux {
  590. groups = "i2s_out_lr_clk";
  591. function = "i2s_out";
  592. bias-disable;
  593. };
  594. };
  595. i2s_out_ch01_pins: i2s_out_ch01 {
  596. mux {
  597. groups = "i2s_out_ch01";
  598. function = "i2s_out";
  599. bias-disable;
  600. };
  601. };
  602. i2sout_ch23_z_pins: i2sout_ch23_z {
  603. mux {
  604. groups = "i2sout_ch23_z";
  605. function = "i2s_out";
  606. bias-disable;
  607. };
  608. };
  609. i2sout_ch45_z_pins: i2sout_ch45_z {
  610. mux {
  611. groups = "i2sout_ch45_z";
  612. function = "i2s_out";
  613. bias-disable;
  614. };
  615. };
  616. i2sout_ch67_z_pins: i2sout_ch67_z {
  617. mux {
  618. groups = "i2sout_ch67_z";
  619. function = "i2s_out";
  620. bias-disable;
  621. };
  622. };
  623. spdif_out_h_pins: spdif_out_ao_h {
  624. mux {
  625. groups = "spdif_out_h";
  626. function = "spdif_out";
  627. bias-disable;
  628. };
  629. };
  630. };
  631. eth-phy-mux {
  632. compatible = "mdio-mux-mmioreg", "mdio-mux";
  633. #address-cells = <1>;
  634. #size-cells = <0>;
  635. reg = <0x0 0x55c 0x0 0x4>;
  636. mux-mask = <0xffffffff>;
  637. mdio-parent-bus = <&mdio0>;
  638. internal_mdio: mdio@e40908ff {
  639. reg = <0xe40908ff>;
  640. #address-cells = <1>;
  641. #size-cells = <0>;
  642. internal_phy: ethernet-phy@8 {
  643. compatible = "ethernet-phy-id0181.4400";
  644. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  645. reg = <8>;
  646. max-speed = <100>;
  647. };
  648. };
  649. external_mdio: mdio@2009087f {
  650. reg = <0x2009087f>;
  651. #address-cells = <1>;
  652. #size-cells = <0>;
  653. };
  654. };
  655. };
  656. &pwrc_vpu {
  657. resets = <&reset RESET_VIU>,
  658. <&reset RESET_VENC>,
  659. <&reset RESET_VCBUS>,
  660. <&reset RESET_BT656>,
  661. <&reset RESET_DVIN_RESET>,
  662. <&reset RESET_RDMA>,
  663. <&reset RESET_VENCI>,
  664. <&reset RESET_VENCP>,
  665. <&reset RESET_VDAC>,
  666. <&reset RESET_VDI6>,
  667. <&reset RESET_VENCL>,
  668. <&reset RESET_VID_LOCK>;
  669. clocks = <&clkc CLKID_VPU>,
  670. <&clkc CLKID_VAPB>;
  671. clock-names = "vpu", "vapb";
  672. /*
  673. * VPU clocking is provided by two identical clock paths
  674. * VPU_0 and VPU_1 muxed to a single clock by a glitch
  675. * free mux to safely change frequency while running.
  676. * Same for VAPB but with a final gate after the glitch free mux.
  677. */
  678. assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
  679. <&clkc CLKID_VPU_0>,
  680. <&clkc CLKID_VPU>, /* Glitch free mux */
  681. <&clkc CLKID_VAPB_0_SEL>,
  682. <&clkc CLKID_VAPB_0>,
  683. <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
  684. assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  685. <0>, /* Do Nothing */
  686. <&clkc CLKID_VPU_0>,
  687. <&clkc CLKID_FCLK_DIV4>,
  688. <0>, /* Do Nothing */
  689. <&clkc CLKID_VAPB_0>;
  690. assigned-clock-rates = <0>, /* Do Nothing */
  691. <666666666>,
  692. <0>, /* Do Nothing */
  693. <0>, /* Do Nothing */
  694. <250000000>,
  695. <0>; /* Do Nothing */
  696. };
  697. &saradc {
  698. compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
  699. clocks = <&xtal>,
  700. <&clkc CLKID_SAR_ADC>,
  701. <&clkc CLKID_SAR_ADC_CLK>,
  702. <&clkc CLKID_SAR_ADC_SEL>;
  703. clock-names = "clkin", "core", "adc_clk", "adc_sel";
  704. };
  705. &sd_emmc_a {
  706. clocks = <&clkc CLKID_SD_EMMC_A>,
  707. <&clkc CLKID_SD_EMMC_A_CLK0>,
  708. <&clkc CLKID_FCLK_DIV2>;
  709. clock-names = "core", "clkin0", "clkin1";
  710. resets = <&reset RESET_SD_EMMC_A>;
  711. };
  712. &sd_emmc_b {
  713. clocks = <&clkc CLKID_SD_EMMC_B>,
  714. <&clkc CLKID_SD_EMMC_B_CLK0>,
  715. <&clkc CLKID_FCLK_DIV2>;
  716. clock-names = "core", "clkin0", "clkin1";
  717. resets = <&reset RESET_SD_EMMC_B>;
  718. };
  719. &sd_emmc_c {
  720. clocks = <&clkc CLKID_SD_EMMC_C>,
  721. <&clkc CLKID_SD_EMMC_C_CLK0>,
  722. <&clkc CLKID_FCLK_DIV2>;
  723. clock-names = "core", "clkin0", "clkin1";
  724. resets = <&reset RESET_SD_EMMC_C>;
  725. };
  726. &simplefb_hdmi {
  727. clocks = <&clkc CLKID_HDMI_PCLK>,
  728. <&clkc CLKID_CLK81>,
  729. <&clkc CLKID_GCLK_VENCI_INT0>;
  730. };
  731. &spicc {
  732. clocks = <&clkc CLKID_SPICC>;
  733. clock-names = "core";
  734. resets = <&reset RESET_PERIPHS_SPICC>;
  735. num-cs = <1>;
  736. };
  737. &spifc {
  738. clocks = <&clkc CLKID_SPI>;
  739. };
  740. &uart_A {
  741. clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  742. clock-names = "xtal", "pclk", "baud";
  743. };
  744. &uart_AO {
  745. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
  746. clock-names = "xtal", "pclk", "baud";
  747. };
  748. &uart_AO_B {
  749. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  750. clock-names = "xtal", "pclk", "baud";
  751. };
  752. &uart_B {
  753. clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  754. clock-names = "xtal", "pclk", "baud";
  755. };
  756. &uart_C {
  757. clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
  758. clock-names = "xtal", "pclk", "baud";
  759. };
  760. &vpu {
  761. compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
  762. power-domains = <&pwrc_vpu>;
  763. };
  764. &vdec {
  765. compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
  766. clocks = <&clkc CLKID_DOS_PARSER>,
  767. <&clkc CLKID_DOS>,
  768. <&clkc CLKID_VDEC_1>,
  769. <&clkc CLKID_VDEC_HEVC>;
  770. clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
  771. resets = <&reset RESET_PARSER>;
  772. reset-names = "esparser";
  773. };