meson-g12b.dtsi 1.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2019 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include "meson-g12.dtsi"
  7. / {
  8. compatible = "amlogic,g12b";
  9. cpus {
  10. #address-cells = <0x2>;
  11. #size-cells = <0x0>;
  12. cpu-map {
  13. cluster0 {
  14. core0 {
  15. cpu = <&cpu0>;
  16. };
  17. core1 {
  18. cpu = <&cpu1>;
  19. };
  20. };
  21. cluster1 {
  22. core0 {
  23. cpu = <&cpu100>;
  24. };
  25. core1 {
  26. cpu = <&cpu101>;
  27. };
  28. core2 {
  29. cpu = <&cpu102>;
  30. };
  31. core3 {
  32. cpu = <&cpu103>;
  33. };
  34. };
  35. };
  36. cpu0: cpu@0 {
  37. device_type = "cpu";
  38. compatible = "arm,cortex-a53";
  39. reg = <0x0 0x0>;
  40. enable-method = "psci";
  41. capacity-dmips-mhz = <592>;
  42. next-level-cache = <&l2>;
  43. #cooling-cells = <2>;
  44. };
  45. cpu1: cpu@1 {
  46. device_type = "cpu";
  47. compatible = "arm,cortex-a53";
  48. reg = <0x0 0x1>;
  49. enable-method = "psci";
  50. capacity-dmips-mhz = <592>;
  51. next-level-cache = <&l2>;
  52. #cooling-cells = <2>;
  53. };
  54. cpu100: cpu@100 {
  55. device_type = "cpu";
  56. compatible = "arm,cortex-a73";
  57. reg = <0x0 0x100>;
  58. enable-method = "psci";
  59. capacity-dmips-mhz = <1024>;
  60. next-level-cache = <&l2>;
  61. #cooling-cells = <2>;
  62. };
  63. cpu101: cpu@101 {
  64. device_type = "cpu";
  65. compatible = "arm,cortex-a73";
  66. reg = <0x0 0x101>;
  67. enable-method = "psci";
  68. capacity-dmips-mhz = <1024>;
  69. next-level-cache = <&l2>;
  70. #cooling-cells = <2>;
  71. };
  72. cpu102: cpu@102 {
  73. device_type = "cpu";
  74. compatible = "arm,cortex-a73";
  75. reg = <0x0 0x102>;
  76. enable-method = "psci";
  77. capacity-dmips-mhz = <1024>;
  78. next-level-cache = <&l2>;
  79. #cooling-cells = <2>;
  80. };
  81. cpu103: cpu@103 {
  82. device_type = "cpu";
  83. compatible = "arm,cortex-a73";
  84. reg = <0x0 0x103>;
  85. enable-method = "psci";
  86. capacity-dmips-mhz = <1024>;
  87. next-level-cache = <&l2>;
  88. #cooling-cells = <2>;
  89. };
  90. l2: l2-cache0 {
  91. compatible = "cache";
  92. };
  93. };
  94. };
  95. &clkc {
  96. compatible = "amlogic,g12b-clkc";
  97. };