pinctrl_stm32.c 12 KB

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  1. #include <common.h>
  2. #include <dm.h>
  3. #include <hwspinlock.h>
  4. #include <log.h>
  5. #include <malloc.h>
  6. #include <asm/arch/gpio.h>
  7. #include <asm/gpio.h>
  8. #include <asm/io.h>
  9. #include <dm/device_compat.h>
  10. #include <dm/lists.h>
  11. #include <dm/pinctrl.h>
  12. #include <linux/bitops.h>
  13. #include <linux/err.h>
  14. #include <linux/libfdt.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define MAX_PINS_ONE_IP 70
  17. #define MODE_BITS_MASK 3
  18. #define OSPEED_MASK 3
  19. #define PUPD_MASK 3
  20. #define OTYPE_MSK 1
  21. #define AFR_MASK 0xF
  22. struct stm32_pinctrl_priv {
  23. struct hwspinlock hws;
  24. int pinctrl_ngpios;
  25. struct list_head gpio_dev;
  26. };
  27. struct stm32_gpio_bank {
  28. struct udevice *gpio_dev;
  29. struct list_head list;
  30. };
  31. #ifndef CONFIG_SPL_BUILD
  32. static char pin_name[PINNAME_SIZE];
  33. #define PINMUX_MODE_COUNT 5
  34. static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
  35. "gpio input",
  36. "gpio output",
  37. "analog",
  38. "unknown",
  39. "alt function",
  40. };
  41. static const char * const pinmux_output[] = {
  42. [STM32_GPIO_PUPD_NO] = "bias-disable",
  43. [STM32_GPIO_PUPD_UP] = "bias-pull-up",
  44. [STM32_GPIO_PUPD_DOWN] = "bias-pull-down",
  45. };
  46. static const char * const pinmux_input[] = {
  47. [STM32_GPIO_OTYPE_PP] = "drive-push-pull",
  48. [STM32_GPIO_OTYPE_OD] = "drive-open-drain",
  49. };
  50. static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
  51. {
  52. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  53. struct stm32_gpio_regs *regs = priv->regs;
  54. u32 af;
  55. u32 alt_shift = (offset % 8) * 4;
  56. u32 alt_index = offset / 8;
  57. af = (readl(&regs->afr[alt_index]) &
  58. GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
  59. return af;
  60. }
  61. static int stm32_populate_gpio_dev_list(struct udevice *dev)
  62. {
  63. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  64. struct udevice *gpio_dev;
  65. struct udevice *child;
  66. struct stm32_gpio_bank *gpio_bank;
  67. int ret;
  68. /*
  69. * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
  70. * a list with all gpio device reference which belongs to the
  71. * current pin-controller. This list is used to find pin_name and
  72. * pin muxing
  73. */
  74. list_for_each_entry(child, &dev->child_head, sibling_node) {
  75. ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
  76. &gpio_dev);
  77. if (ret < 0)
  78. continue;
  79. gpio_bank = malloc(sizeof(*gpio_bank));
  80. if (!gpio_bank) {
  81. dev_err(dev, "Not enough memory\n");
  82. return -ENOMEM;
  83. }
  84. gpio_bank->gpio_dev = gpio_dev;
  85. list_add_tail(&gpio_bank->list, &priv->gpio_dev);
  86. }
  87. return 0;
  88. }
  89. static int stm32_pinctrl_get_pins_count(struct udevice *dev)
  90. {
  91. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  92. struct gpio_dev_priv *uc_priv;
  93. struct stm32_gpio_bank *gpio_bank;
  94. /*
  95. * if get_pins_count has already been executed once on this
  96. * pin-controller, no need to run it again
  97. */
  98. if (priv->pinctrl_ngpios)
  99. return priv->pinctrl_ngpios;
  100. if (list_empty(&priv->gpio_dev))
  101. stm32_populate_gpio_dev_list(dev);
  102. /*
  103. * walk through all banks to retrieve the pin-controller
  104. * pins number
  105. */
  106. list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
  107. uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
  108. priv->pinctrl_ngpios += uc_priv->gpio_count;
  109. }
  110. return priv->pinctrl_ngpios;
  111. }
  112. static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
  113. unsigned int selector,
  114. unsigned int *idx)
  115. {
  116. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  117. struct stm32_gpio_bank *gpio_bank;
  118. struct gpio_dev_priv *uc_priv;
  119. int pin_count = 0;
  120. if (list_empty(&priv->gpio_dev))
  121. stm32_populate_gpio_dev_list(dev);
  122. /* look up for the bank which owns the requested pin */
  123. list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
  124. uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
  125. if (selector < (pin_count + uc_priv->gpio_count)) {
  126. /*
  127. * we found the bank, convert pin selector to
  128. * gpio bank index
  129. */
  130. *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
  131. selector - pin_count);
  132. if (IS_ERR_VALUE(*idx))
  133. return NULL;
  134. return gpio_bank->gpio_dev;
  135. }
  136. pin_count += uc_priv->gpio_count;
  137. }
  138. return NULL;
  139. }
  140. static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
  141. unsigned int selector)
  142. {
  143. struct gpio_dev_priv *uc_priv;
  144. struct udevice *gpio_dev;
  145. unsigned int gpio_idx;
  146. /* look up for the bank which owns the requested pin */
  147. gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
  148. if (!gpio_dev) {
  149. snprintf(pin_name, PINNAME_SIZE, "Error");
  150. } else {
  151. uc_priv = dev_get_uclass_priv(gpio_dev);
  152. snprintf(pin_name, PINNAME_SIZE, "%s%d",
  153. uc_priv->bank_name,
  154. gpio_idx);
  155. }
  156. return pin_name;
  157. }
  158. static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
  159. unsigned int selector,
  160. char *buf,
  161. int size)
  162. {
  163. struct udevice *gpio_dev;
  164. struct stm32_gpio_priv *priv;
  165. const char *label;
  166. int mode;
  167. int af_num;
  168. unsigned int gpio_idx;
  169. u32 pupd, otype;
  170. /* look up for the bank which owns the requested pin */
  171. gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
  172. if (!gpio_dev)
  173. return -ENODEV;
  174. mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
  175. dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
  176. selector, gpio_idx, mode);
  177. priv = dev_get_priv(gpio_dev);
  178. switch (mode) {
  179. case GPIOF_UNKNOWN:
  180. /* should never happen */
  181. return -EINVAL;
  182. case GPIOF_UNUSED:
  183. snprintf(buf, size, "%s", pinmux_mode[mode]);
  184. break;
  185. case GPIOF_FUNC:
  186. af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
  187. snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
  188. break;
  189. case GPIOF_OUTPUT:
  190. pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) &
  191. PUPD_MASK;
  192. snprintf(buf, size, "%s %s %s",
  193. pinmux_mode[mode], pinmux_output[pupd],
  194. label ? label : "");
  195. break;
  196. case GPIOF_INPUT:
  197. otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
  198. snprintf(buf, size, "%s %s %s",
  199. pinmux_mode[mode], pinmux_input[otype],
  200. label ? label : "");
  201. break;
  202. }
  203. return 0;
  204. }
  205. #endif
  206. static int stm32_pinctrl_probe(struct udevice *dev)
  207. {
  208. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  209. int ret;
  210. INIT_LIST_HEAD(&priv->gpio_dev);
  211. /* hwspinlock property is optional, just log the error */
  212. ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
  213. if (ret)
  214. debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
  215. __func__, ret);
  216. return 0;
  217. }
  218. static int stm32_gpio_config(struct gpio_desc *desc,
  219. const struct stm32_gpio_ctl *ctl)
  220. {
  221. struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
  222. struct stm32_gpio_regs *regs = priv->regs;
  223. struct stm32_pinctrl_priv *ctrl_priv;
  224. int ret;
  225. u32 index;
  226. if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
  227. ctl->pupd > 2 || ctl->speed > 3)
  228. return -EINVAL;
  229. ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
  230. ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
  231. if (ret == -ETIME) {
  232. dev_err(desc->dev, "HWSpinlock timeout\n");
  233. return ret;
  234. }
  235. index = (desc->offset & 0x07) * 4;
  236. clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
  237. ctl->af << index);
  238. index = desc->offset * 2;
  239. clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
  240. ctl->mode << index);
  241. clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
  242. ctl->speed << index);
  243. clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
  244. index = desc->offset;
  245. clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
  246. hwspinlock_unlock(&ctrl_priv->hws);
  247. return 0;
  248. }
  249. static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
  250. {
  251. gpio_dsc->port = (port_pin & 0x1F000) >> 12;
  252. gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
  253. debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
  254. gpio_dsc->pin);
  255. return 0;
  256. }
  257. static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
  258. {
  259. gpio_fn &= 0x00FF;
  260. gpio_ctl->af = 0;
  261. switch (gpio_fn) {
  262. case 0:
  263. gpio_ctl->mode = STM32_GPIO_MODE_IN;
  264. break;
  265. case 1 ... 16:
  266. gpio_ctl->mode = STM32_GPIO_MODE_AF;
  267. gpio_ctl->af = gpio_fn - 1;
  268. break;
  269. case 17:
  270. gpio_ctl->mode = STM32_GPIO_MODE_AN;
  271. break;
  272. default:
  273. gpio_ctl->mode = STM32_GPIO_MODE_OUT;
  274. break;
  275. }
  276. gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
  277. if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
  278. gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
  279. else
  280. gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
  281. if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
  282. gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
  283. else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
  284. gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
  285. else
  286. gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
  287. debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
  288. __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
  289. gpio_ctl->pupd);
  290. return 0;
  291. }
  292. static int stm32_pinctrl_config(int offset)
  293. {
  294. u32 pin_mux[MAX_PINS_ONE_IP];
  295. int rv, len;
  296. /*
  297. * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
  298. * usart1) of pin controller phandle "pinctrl-0"
  299. * */
  300. fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
  301. struct stm32_gpio_dsc gpio_dsc;
  302. struct stm32_gpio_ctl gpio_ctl;
  303. int i;
  304. len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
  305. "pinmux", pin_mux,
  306. ARRAY_SIZE(pin_mux));
  307. debug("%s: no of pinmux entries= %d\n", __func__, len);
  308. if (len < 0)
  309. return -EINVAL;
  310. for (i = 0; i < len; i++) {
  311. struct gpio_desc desc;
  312. debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
  313. prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
  314. prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
  315. rv = uclass_get_device_by_seq(UCLASS_GPIO,
  316. gpio_dsc.port,
  317. &desc.dev);
  318. if (rv)
  319. return rv;
  320. desc.offset = gpio_dsc.pin;
  321. rv = stm32_gpio_config(&desc, &gpio_ctl);
  322. debug("%s: rv = %d\n\n", __func__, rv);
  323. if (rv)
  324. return rv;
  325. }
  326. }
  327. return 0;
  328. }
  329. static int stm32_pinctrl_bind(struct udevice *dev)
  330. {
  331. ofnode node;
  332. const char *name;
  333. int ret;
  334. dev_for_each_subnode(node, dev) {
  335. debug("%s: bind %s\n", __func__, ofnode_get_name(node));
  336. ofnode_get_property(node, "gpio-controller", &ret);
  337. if (ret < 0)
  338. continue;
  339. /* Get the name of each gpio node */
  340. name = ofnode_get_name(node);
  341. if (!name)
  342. return -EINVAL;
  343. /* Bind each gpio node */
  344. ret = device_bind_driver_to_node(dev, "gpio_stm32",
  345. name, node, NULL);
  346. if (ret)
  347. return ret;
  348. debug("%s: bind %s\n", __func__, name);
  349. }
  350. return 0;
  351. }
  352. #if CONFIG_IS_ENABLED(PINCTRL_FULL)
  353. static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  354. {
  355. return stm32_pinctrl_config(dev_of_offset(config));
  356. }
  357. #else /* PINCTRL_FULL */
  358. static int stm32_pinctrl_set_state_simple(struct udevice *dev,
  359. struct udevice *periph)
  360. {
  361. const void *fdt = gd->fdt_blob;
  362. const fdt32_t *list;
  363. uint32_t phandle;
  364. int config_node;
  365. int size, i, ret;
  366. list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
  367. if (!list)
  368. return -EINVAL;
  369. debug("%s: periph->name = %s\n", __func__, periph->name);
  370. size /= sizeof(*list);
  371. for (i = 0; i < size; i++) {
  372. phandle = fdt32_to_cpu(*list++);
  373. config_node = fdt_node_offset_by_phandle(fdt, phandle);
  374. if (config_node < 0) {
  375. pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
  376. return -EINVAL;
  377. }
  378. ret = stm32_pinctrl_config(config_node);
  379. if (ret)
  380. return ret;
  381. }
  382. return 0;
  383. }
  384. #endif /* PINCTRL_FULL */
  385. static struct pinctrl_ops stm32_pinctrl_ops = {
  386. #if CONFIG_IS_ENABLED(PINCTRL_FULL)
  387. .set_state = stm32_pinctrl_set_state,
  388. #else /* PINCTRL_FULL */
  389. .set_state_simple = stm32_pinctrl_set_state_simple,
  390. #endif /* PINCTRL_FULL */
  391. #ifndef CONFIG_SPL_BUILD
  392. .get_pin_name = stm32_pinctrl_get_pin_name,
  393. .get_pins_count = stm32_pinctrl_get_pins_count,
  394. .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
  395. #endif
  396. };
  397. static const struct udevice_id stm32_pinctrl_ids[] = {
  398. { .compatible = "st,stm32f429-pinctrl" },
  399. { .compatible = "st,stm32f469-pinctrl" },
  400. { .compatible = "st,stm32f746-pinctrl" },
  401. { .compatible = "st,stm32f769-pinctrl" },
  402. { .compatible = "st,stm32h743-pinctrl" },
  403. { .compatible = "st,stm32mp157-pinctrl" },
  404. { .compatible = "st,stm32mp157-z-pinctrl" },
  405. { }
  406. };
  407. U_BOOT_DRIVER(pinctrl_stm32) = {
  408. .name = "pinctrl_stm32",
  409. .id = UCLASS_PINCTRL,
  410. .of_match = stm32_pinctrl_ids,
  411. .ops = &stm32_pinctrl_ops,
  412. .bind = stm32_pinctrl_bind,
  413. .probe = stm32_pinctrl_probe,
  414. .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
  415. };