dwc_eth_qos.c 58 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. *
  5. * Portions based on U-Boot's rtl8169.c.
  6. */
  7. /*
  8. * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
  9. * Service) IP block. The IP supports multiple options for bus type, clocking/
  10. * reset structure, and feature list.
  11. *
  12. * The driver is written such that generic core logic is kept separate from
  13. * configuration-specific logic. Code that interacts with configuration-
  14. * specific resources is split out into separate functions to avoid polluting
  15. * common code. If/when this driver is enhanced to support multiple
  16. * configurations, the core code should be adapted to call all configuration-
  17. * specific functions through function pointers, with the definition of those
  18. * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
  19. * field.
  20. *
  21. * The following configurations are currently supported:
  22. * tegra186:
  23. * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
  24. * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
  25. * supports a single RGMII PHY. This configuration also has SW control over
  26. * all clock and reset signals to the HW block.
  27. */
  28. #include <common.h>
  29. #include <clk.h>
  30. #include <cpu_func.h>
  31. #include <dm.h>
  32. #include <errno.h>
  33. #include <log.h>
  34. #include <malloc.h>
  35. #include <memalign.h>
  36. #include <miiphy.h>
  37. #include <net.h>
  38. #include <netdev.h>
  39. #include <phy.h>
  40. #include <reset.h>
  41. #include <wait_bit.h>
  42. #include <asm/cache.h>
  43. #include <asm/gpio.h>
  44. #include <asm/io.h>
  45. #include <eth_phy.h>
  46. #ifdef CONFIG_ARCH_IMX8M
  47. #include <asm/arch/clock.h>
  48. #include <asm/mach-imx/sys_proto.h>
  49. #endif
  50. #include <linux/bitops.h>
  51. #include <linux/delay.h>
  52. /* Core registers */
  53. #define EQOS_MAC_REGS_BASE 0x000
  54. struct eqos_mac_regs {
  55. uint32_t configuration; /* 0x000 */
  56. uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
  57. uint32_t q0_tx_flow_ctrl; /* 0x070 */
  58. uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
  59. uint32_t rx_flow_ctrl; /* 0x090 */
  60. uint32_t unused_094; /* 0x094 */
  61. uint32_t txq_prty_map0; /* 0x098 */
  62. uint32_t unused_09c; /* 0x09c */
  63. uint32_t rxq_ctrl0; /* 0x0a0 */
  64. uint32_t unused_0a4; /* 0x0a4 */
  65. uint32_t rxq_ctrl2; /* 0x0a8 */
  66. uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
  67. uint32_t us_tic_counter; /* 0x0dc */
  68. uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
  69. uint32_t hw_feature0; /* 0x11c */
  70. uint32_t hw_feature1; /* 0x120 */
  71. uint32_t hw_feature2; /* 0x124 */
  72. uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
  73. uint32_t mdio_address; /* 0x200 */
  74. uint32_t mdio_data; /* 0x204 */
  75. uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
  76. uint32_t address0_high; /* 0x300 */
  77. uint32_t address0_low; /* 0x304 */
  78. };
  79. #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
  80. #define EQOS_MAC_CONFIGURATION_CST BIT(21)
  81. #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
  82. #define EQOS_MAC_CONFIGURATION_WD BIT(19)
  83. #define EQOS_MAC_CONFIGURATION_JD BIT(17)
  84. #define EQOS_MAC_CONFIGURATION_JE BIT(16)
  85. #define EQOS_MAC_CONFIGURATION_PS BIT(15)
  86. #define EQOS_MAC_CONFIGURATION_FES BIT(14)
  87. #define EQOS_MAC_CONFIGURATION_DM BIT(13)
  88. #define EQOS_MAC_CONFIGURATION_LM BIT(12)
  89. #define EQOS_MAC_CONFIGURATION_TE BIT(1)
  90. #define EQOS_MAC_CONFIGURATION_RE BIT(0)
  91. #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
  92. #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
  93. #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
  94. #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
  95. #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
  96. #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
  97. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
  98. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
  99. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
  100. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
  101. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
  102. #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
  103. #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
  104. #define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
  105. #define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
  106. #define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
  107. #define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
  108. #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
  109. #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
  110. #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
  111. #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
  112. #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
  113. #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
  114. #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
  115. #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
  116. #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
  117. #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
  118. #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
  119. #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
  120. #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
  121. #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
  122. #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
  123. #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
  124. #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
  125. #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
  126. #define EQOS_MTL_REGS_BASE 0xd00
  127. struct eqos_mtl_regs {
  128. uint32_t txq0_operation_mode; /* 0xd00 */
  129. uint32_t unused_d04; /* 0xd04 */
  130. uint32_t txq0_debug; /* 0xd08 */
  131. uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
  132. uint32_t txq0_quantum_weight; /* 0xd18 */
  133. uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
  134. uint32_t rxq0_operation_mode; /* 0xd30 */
  135. uint32_t unused_d34; /* 0xd34 */
  136. uint32_t rxq0_debug; /* 0xd38 */
  137. };
  138. #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
  139. #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
  140. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
  141. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
  142. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
  143. #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
  144. #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
  145. #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
  146. #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
  147. #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
  148. #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
  149. #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
  150. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
  151. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
  152. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
  153. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
  154. #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
  155. #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
  156. #define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4)
  157. #define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3)
  158. #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
  159. #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
  160. #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
  161. #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
  162. #define EQOS_DMA_REGS_BASE 0x1000
  163. struct eqos_dma_regs {
  164. uint32_t mode; /* 0x1000 */
  165. uint32_t sysbus_mode; /* 0x1004 */
  166. uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
  167. uint32_t ch0_control; /* 0x1100 */
  168. uint32_t ch0_tx_control; /* 0x1104 */
  169. uint32_t ch0_rx_control; /* 0x1108 */
  170. uint32_t unused_110c; /* 0x110c */
  171. uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
  172. uint32_t ch0_txdesc_list_address; /* 0x1114 */
  173. uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
  174. uint32_t ch0_rxdesc_list_address; /* 0x111c */
  175. uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
  176. uint32_t unused_1124; /* 0x1124 */
  177. uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
  178. uint32_t ch0_txdesc_ring_length; /* 0x112c */
  179. uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
  180. };
  181. #define EQOS_DMA_MODE_SWR BIT(0)
  182. #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
  183. #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
  184. #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
  185. #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
  186. #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
  187. #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
  188. #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
  189. #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
  190. #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
  191. #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
  192. #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
  193. #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
  194. #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
  195. #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
  196. #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
  197. #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
  198. /* These registers are Tegra186-specific */
  199. #define EQOS_TEGRA186_REGS_BASE 0x8800
  200. struct eqos_tegra186_regs {
  201. uint32_t sdmemcomppadctrl; /* 0x8800 */
  202. uint32_t auto_cal_config; /* 0x8804 */
  203. uint32_t unused_8808; /* 0x8808 */
  204. uint32_t auto_cal_status; /* 0x880c */
  205. };
  206. #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
  207. #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
  208. #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
  209. #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
  210. /* Descriptors */
  211. #define EQOS_DESCRIPTOR_WORDS 4
  212. #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
  213. /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
  214. #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
  215. #define EQOS_DESCRIPTORS_TX 4
  216. #define EQOS_DESCRIPTORS_RX 4
  217. #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
  218. #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
  219. EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
  220. #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
  221. #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
  222. #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
  223. /*
  224. * Warn if the cache-line size is larger than the descriptor size. In such
  225. * cases the driver will likely fail because the CPU needs to flush the cache
  226. * when requeuing RX buffers, therefore descriptors written by the hardware
  227. * may be discarded. Architectures with full IO coherence, such as x86, do not
  228. * experience this issue, and hence are excluded from this condition.
  229. *
  230. * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  231. * the driver to allocate descriptors from a pool of non-cached memory.
  232. */
  233. #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
  234. #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
  235. !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
  236. #warning Cache line size is larger than descriptor size
  237. #endif
  238. #endif
  239. struct eqos_desc {
  240. u32 des0;
  241. u32 des1;
  242. u32 des2;
  243. u32 des3;
  244. };
  245. #define EQOS_DESC3_OWN BIT(31)
  246. #define EQOS_DESC3_FD BIT(29)
  247. #define EQOS_DESC3_LD BIT(28)
  248. #define EQOS_DESC3_BUF1V BIT(24)
  249. struct eqos_config {
  250. bool reg_access_always_ok;
  251. int mdio_wait;
  252. int swr_wait;
  253. int config_mac;
  254. int config_mac_mdio;
  255. phy_interface_t (*interface)(struct udevice *dev);
  256. struct eqos_ops *ops;
  257. };
  258. struct eqos_ops {
  259. void (*eqos_inval_desc)(void *desc);
  260. void (*eqos_flush_desc)(void *desc);
  261. void (*eqos_inval_buffer)(void *buf, size_t size);
  262. void (*eqos_flush_buffer)(void *buf, size_t size);
  263. int (*eqos_probe_resources)(struct udevice *dev);
  264. int (*eqos_remove_resources)(struct udevice *dev);
  265. int (*eqos_stop_resets)(struct udevice *dev);
  266. int (*eqos_start_resets)(struct udevice *dev);
  267. void (*eqos_stop_clks)(struct udevice *dev);
  268. int (*eqos_start_clks)(struct udevice *dev);
  269. int (*eqos_calibrate_pads)(struct udevice *dev);
  270. int (*eqos_disable_calibration)(struct udevice *dev);
  271. int (*eqos_set_tx_clk_speed)(struct udevice *dev);
  272. ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
  273. };
  274. struct eqos_priv {
  275. struct udevice *dev;
  276. const struct eqos_config *config;
  277. fdt_addr_t regs;
  278. struct eqos_mac_regs *mac_regs;
  279. struct eqos_mtl_regs *mtl_regs;
  280. struct eqos_dma_regs *dma_regs;
  281. struct eqos_tegra186_regs *tegra186_regs;
  282. struct reset_ctl reset_ctl;
  283. struct gpio_desc phy_reset_gpio;
  284. struct clk clk_master_bus;
  285. struct clk clk_rx;
  286. struct clk clk_ptp_ref;
  287. struct clk clk_tx;
  288. struct clk clk_ck;
  289. struct clk clk_slave_bus;
  290. struct mii_dev *mii;
  291. struct phy_device *phy;
  292. int phyaddr;
  293. u32 max_speed;
  294. void *descs;
  295. struct eqos_desc *tx_descs;
  296. struct eqos_desc *rx_descs;
  297. int tx_desc_idx, rx_desc_idx;
  298. void *tx_dma_buf;
  299. void *rx_dma_buf;
  300. void *rx_pkt;
  301. bool started;
  302. bool reg_access_ok;
  303. };
  304. /*
  305. * TX and RX descriptors are 16 bytes. This causes problems with the cache
  306. * maintenance on CPUs where the cache-line size exceeds the size of these
  307. * descriptors. What will happen is that when the driver receives a packet
  308. * it will be immediately requeued for the hardware to reuse. The CPU will
  309. * therefore need to flush the cache-line containing the descriptor, which
  310. * will cause all other descriptors in the same cache-line to be flushed
  311. * along with it. If one of those descriptors had been written to by the
  312. * device those changes (and the associated packet) will be lost.
  313. *
  314. * To work around this, we make use of non-cached memory if available. If
  315. * descriptors are mapped uncached there's no need to manually flush them
  316. * or invalidate them.
  317. *
  318. * Note that this only applies to descriptors. The packet data buffers do
  319. * not have the same constraints since they are 1536 bytes large, so they
  320. * are unlikely to share cache-lines.
  321. */
  322. static void *eqos_alloc_descs(unsigned int num)
  323. {
  324. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  325. return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
  326. EQOS_DESCRIPTOR_ALIGN);
  327. #else
  328. return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
  329. #endif
  330. }
  331. static void eqos_free_descs(void *descs)
  332. {
  333. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  334. /* FIXME: noncached_alloc() has no opposite */
  335. #else
  336. free(descs);
  337. #endif
  338. }
  339. static void eqos_inval_desc_tegra186(void *desc)
  340. {
  341. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  342. unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
  343. unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
  344. ARCH_DMA_MINALIGN);
  345. invalidate_dcache_range(start, end);
  346. #endif
  347. }
  348. static void eqos_inval_desc_generic(void *desc)
  349. {
  350. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  351. unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
  352. unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
  353. ARCH_DMA_MINALIGN);
  354. invalidate_dcache_range(start, end);
  355. #endif
  356. }
  357. static void eqos_flush_desc_tegra186(void *desc)
  358. {
  359. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  360. flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
  361. #endif
  362. }
  363. static void eqos_flush_desc_generic(void *desc)
  364. {
  365. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  366. unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
  367. unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
  368. ARCH_DMA_MINALIGN);
  369. flush_dcache_range(start, end);
  370. #endif
  371. }
  372. static void eqos_inval_buffer_tegra186(void *buf, size_t size)
  373. {
  374. unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
  375. unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
  376. invalidate_dcache_range(start, end);
  377. }
  378. static void eqos_inval_buffer_generic(void *buf, size_t size)
  379. {
  380. unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
  381. unsigned long end = roundup((unsigned long)buf + size,
  382. ARCH_DMA_MINALIGN);
  383. invalidate_dcache_range(start, end);
  384. }
  385. static void eqos_flush_buffer_tegra186(void *buf, size_t size)
  386. {
  387. flush_cache((unsigned long)buf, size);
  388. }
  389. static void eqos_flush_buffer_generic(void *buf, size_t size)
  390. {
  391. unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
  392. unsigned long end = roundup((unsigned long)buf + size,
  393. ARCH_DMA_MINALIGN);
  394. flush_dcache_range(start, end);
  395. }
  396. static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
  397. {
  398. return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
  399. EQOS_MAC_MDIO_ADDRESS_GB, false,
  400. 1000000, true);
  401. }
  402. static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
  403. int mdio_reg)
  404. {
  405. struct eqos_priv *eqos = bus->priv;
  406. u32 val;
  407. int ret;
  408. debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
  409. mdio_reg);
  410. ret = eqos_mdio_wait_idle(eqos);
  411. if (ret) {
  412. pr_err("MDIO not idle at entry");
  413. return ret;
  414. }
  415. val = readl(&eqos->mac_regs->mdio_address);
  416. val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
  417. EQOS_MAC_MDIO_ADDRESS_C45E;
  418. val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
  419. (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
  420. (eqos->config->config_mac_mdio <<
  421. EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
  422. (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
  423. EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
  424. EQOS_MAC_MDIO_ADDRESS_GB;
  425. writel(val, &eqos->mac_regs->mdio_address);
  426. udelay(eqos->config->mdio_wait);
  427. ret = eqos_mdio_wait_idle(eqos);
  428. if (ret) {
  429. pr_err("MDIO read didn't complete");
  430. return ret;
  431. }
  432. val = readl(&eqos->mac_regs->mdio_data);
  433. val &= EQOS_MAC_MDIO_DATA_GD_MASK;
  434. debug("%s: val=%x\n", __func__, val);
  435. return val;
  436. }
  437. static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
  438. int mdio_reg, u16 mdio_val)
  439. {
  440. struct eqos_priv *eqos = bus->priv;
  441. u32 val;
  442. int ret;
  443. debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
  444. mdio_addr, mdio_reg, mdio_val);
  445. ret = eqos_mdio_wait_idle(eqos);
  446. if (ret) {
  447. pr_err("MDIO not idle at entry");
  448. return ret;
  449. }
  450. writel(mdio_val, &eqos->mac_regs->mdio_data);
  451. val = readl(&eqos->mac_regs->mdio_address);
  452. val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
  453. EQOS_MAC_MDIO_ADDRESS_C45E;
  454. val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
  455. (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
  456. (eqos->config->config_mac_mdio <<
  457. EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
  458. (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
  459. EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
  460. EQOS_MAC_MDIO_ADDRESS_GB;
  461. writel(val, &eqos->mac_regs->mdio_address);
  462. udelay(eqos->config->mdio_wait);
  463. ret = eqos_mdio_wait_idle(eqos);
  464. if (ret) {
  465. pr_err("MDIO read didn't complete");
  466. return ret;
  467. }
  468. return 0;
  469. }
  470. static int eqos_start_clks_tegra186(struct udevice *dev)
  471. {
  472. #ifdef CONFIG_CLK
  473. struct eqos_priv *eqos = dev_get_priv(dev);
  474. int ret;
  475. debug("%s(dev=%p):\n", __func__, dev);
  476. ret = clk_enable(&eqos->clk_slave_bus);
  477. if (ret < 0) {
  478. pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
  479. goto err;
  480. }
  481. ret = clk_enable(&eqos->clk_master_bus);
  482. if (ret < 0) {
  483. pr_err("clk_enable(clk_master_bus) failed: %d", ret);
  484. goto err_disable_clk_slave_bus;
  485. }
  486. ret = clk_enable(&eqos->clk_rx);
  487. if (ret < 0) {
  488. pr_err("clk_enable(clk_rx) failed: %d", ret);
  489. goto err_disable_clk_master_bus;
  490. }
  491. ret = clk_enable(&eqos->clk_ptp_ref);
  492. if (ret < 0) {
  493. pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
  494. goto err_disable_clk_rx;
  495. }
  496. ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
  497. if (ret < 0) {
  498. pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
  499. goto err_disable_clk_ptp_ref;
  500. }
  501. ret = clk_enable(&eqos->clk_tx);
  502. if (ret < 0) {
  503. pr_err("clk_enable(clk_tx) failed: %d", ret);
  504. goto err_disable_clk_ptp_ref;
  505. }
  506. #endif
  507. debug("%s: OK\n", __func__);
  508. return 0;
  509. #ifdef CONFIG_CLK
  510. err_disable_clk_ptp_ref:
  511. clk_disable(&eqos->clk_ptp_ref);
  512. err_disable_clk_rx:
  513. clk_disable(&eqos->clk_rx);
  514. err_disable_clk_master_bus:
  515. clk_disable(&eqos->clk_master_bus);
  516. err_disable_clk_slave_bus:
  517. clk_disable(&eqos->clk_slave_bus);
  518. err:
  519. debug("%s: FAILED: %d\n", __func__, ret);
  520. return ret;
  521. #endif
  522. }
  523. static int eqos_start_clks_stm32(struct udevice *dev)
  524. {
  525. #ifdef CONFIG_CLK
  526. struct eqos_priv *eqos = dev_get_priv(dev);
  527. int ret;
  528. debug("%s(dev=%p):\n", __func__, dev);
  529. ret = clk_enable(&eqos->clk_master_bus);
  530. if (ret < 0) {
  531. pr_err("clk_enable(clk_master_bus) failed: %d", ret);
  532. goto err;
  533. }
  534. ret = clk_enable(&eqos->clk_rx);
  535. if (ret < 0) {
  536. pr_err("clk_enable(clk_rx) failed: %d", ret);
  537. goto err_disable_clk_master_bus;
  538. }
  539. ret = clk_enable(&eqos->clk_tx);
  540. if (ret < 0) {
  541. pr_err("clk_enable(clk_tx) failed: %d", ret);
  542. goto err_disable_clk_rx;
  543. }
  544. if (clk_valid(&eqos->clk_ck)) {
  545. ret = clk_enable(&eqos->clk_ck);
  546. if (ret < 0) {
  547. pr_err("clk_enable(clk_ck) failed: %d", ret);
  548. goto err_disable_clk_tx;
  549. }
  550. }
  551. #endif
  552. debug("%s: OK\n", __func__);
  553. return 0;
  554. #ifdef CONFIG_CLK
  555. err_disable_clk_tx:
  556. clk_disable(&eqos->clk_tx);
  557. err_disable_clk_rx:
  558. clk_disable(&eqos->clk_rx);
  559. err_disable_clk_master_bus:
  560. clk_disable(&eqos->clk_master_bus);
  561. err:
  562. debug("%s: FAILED: %d\n", __func__, ret);
  563. return ret;
  564. #endif
  565. }
  566. static int eqos_start_clks_imx(struct udevice *dev)
  567. {
  568. return 0;
  569. }
  570. static void eqos_stop_clks_tegra186(struct udevice *dev)
  571. {
  572. #ifdef CONFIG_CLK
  573. struct eqos_priv *eqos = dev_get_priv(dev);
  574. debug("%s(dev=%p):\n", __func__, dev);
  575. clk_disable(&eqos->clk_tx);
  576. clk_disable(&eqos->clk_ptp_ref);
  577. clk_disable(&eqos->clk_rx);
  578. clk_disable(&eqos->clk_master_bus);
  579. clk_disable(&eqos->clk_slave_bus);
  580. #endif
  581. debug("%s: OK\n", __func__);
  582. }
  583. static void eqos_stop_clks_stm32(struct udevice *dev)
  584. {
  585. #ifdef CONFIG_CLK
  586. struct eqos_priv *eqos = dev_get_priv(dev);
  587. debug("%s(dev=%p):\n", __func__, dev);
  588. clk_disable(&eqos->clk_tx);
  589. clk_disable(&eqos->clk_rx);
  590. clk_disable(&eqos->clk_master_bus);
  591. if (clk_valid(&eqos->clk_ck))
  592. clk_disable(&eqos->clk_ck);
  593. #endif
  594. debug("%s: OK\n", __func__);
  595. }
  596. static void eqos_stop_clks_imx(struct udevice *dev)
  597. {
  598. /* empty */
  599. }
  600. static int eqos_start_resets_tegra186(struct udevice *dev)
  601. {
  602. struct eqos_priv *eqos = dev_get_priv(dev);
  603. int ret;
  604. debug("%s(dev=%p):\n", __func__, dev);
  605. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
  606. if (ret < 0) {
  607. pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
  608. return ret;
  609. }
  610. udelay(2);
  611. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
  612. if (ret < 0) {
  613. pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
  614. return ret;
  615. }
  616. ret = reset_assert(&eqos->reset_ctl);
  617. if (ret < 0) {
  618. pr_err("reset_assert() failed: %d", ret);
  619. return ret;
  620. }
  621. udelay(2);
  622. ret = reset_deassert(&eqos->reset_ctl);
  623. if (ret < 0) {
  624. pr_err("reset_deassert() failed: %d", ret);
  625. return ret;
  626. }
  627. debug("%s: OK\n", __func__);
  628. return 0;
  629. }
  630. static int eqos_start_resets_stm32(struct udevice *dev)
  631. {
  632. struct eqos_priv *eqos = dev_get_priv(dev);
  633. int ret;
  634. debug("%s(dev=%p):\n", __func__, dev);
  635. if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
  636. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
  637. if (ret < 0) {
  638. pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
  639. ret);
  640. return ret;
  641. }
  642. udelay(2);
  643. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
  644. if (ret < 0) {
  645. pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d",
  646. ret);
  647. return ret;
  648. }
  649. }
  650. debug("%s: OK\n", __func__);
  651. return 0;
  652. }
  653. static int eqos_start_resets_imx(struct udevice *dev)
  654. {
  655. return 0;
  656. }
  657. static int eqos_stop_resets_tegra186(struct udevice *dev)
  658. {
  659. struct eqos_priv *eqos = dev_get_priv(dev);
  660. reset_assert(&eqos->reset_ctl);
  661. dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
  662. return 0;
  663. }
  664. static int eqos_stop_resets_stm32(struct udevice *dev)
  665. {
  666. struct eqos_priv *eqos = dev_get_priv(dev);
  667. int ret;
  668. if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
  669. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
  670. if (ret < 0) {
  671. pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
  672. ret);
  673. return ret;
  674. }
  675. }
  676. return 0;
  677. }
  678. static int eqos_stop_resets_imx(struct udevice *dev)
  679. {
  680. return 0;
  681. }
  682. static int eqos_calibrate_pads_tegra186(struct udevice *dev)
  683. {
  684. struct eqos_priv *eqos = dev_get_priv(dev);
  685. int ret;
  686. debug("%s(dev=%p):\n", __func__, dev);
  687. setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
  688. EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
  689. udelay(1);
  690. setbits_le32(&eqos->tegra186_regs->auto_cal_config,
  691. EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
  692. ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
  693. EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
  694. if (ret) {
  695. pr_err("calibrate didn't start");
  696. goto failed;
  697. }
  698. ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
  699. EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
  700. if (ret) {
  701. pr_err("calibrate didn't finish");
  702. goto failed;
  703. }
  704. ret = 0;
  705. failed:
  706. clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
  707. EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
  708. debug("%s: returns %d\n", __func__, ret);
  709. return ret;
  710. }
  711. static int eqos_disable_calibration_tegra186(struct udevice *dev)
  712. {
  713. struct eqos_priv *eqos = dev_get_priv(dev);
  714. debug("%s(dev=%p):\n", __func__, dev);
  715. clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
  716. EQOS_AUTO_CAL_CONFIG_ENABLE);
  717. return 0;
  718. }
  719. static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
  720. {
  721. #ifdef CONFIG_CLK
  722. struct eqos_priv *eqos = dev_get_priv(dev);
  723. return clk_get_rate(&eqos->clk_slave_bus);
  724. #else
  725. return 0;
  726. #endif
  727. }
  728. static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
  729. {
  730. #ifdef CONFIG_CLK
  731. struct eqos_priv *eqos = dev_get_priv(dev);
  732. return clk_get_rate(&eqos->clk_master_bus);
  733. #else
  734. return 0;
  735. #endif
  736. }
  737. __weak u32 imx_get_eqos_csr_clk(void)
  738. {
  739. return 100 * 1000000;
  740. }
  741. __weak int imx_eqos_txclk_set_rate(unsigned long rate)
  742. {
  743. return 0;
  744. }
  745. static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
  746. {
  747. return imx_get_eqos_csr_clk();
  748. }
  749. static int eqos_calibrate_pads_stm32(struct udevice *dev)
  750. {
  751. return 0;
  752. }
  753. static int eqos_calibrate_pads_imx(struct udevice *dev)
  754. {
  755. return 0;
  756. }
  757. static int eqos_disable_calibration_stm32(struct udevice *dev)
  758. {
  759. return 0;
  760. }
  761. static int eqos_disable_calibration_imx(struct udevice *dev)
  762. {
  763. return 0;
  764. }
  765. static int eqos_set_full_duplex(struct udevice *dev)
  766. {
  767. struct eqos_priv *eqos = dev_get_priv(dev);
  768. debug("%s(dev=%p):\n", __func__, dev);
  769. setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
  770. return 0;
  771. }
  772. static int eqos_set_half_duplex(struct udevice *dev)
  773. {
  774. struct eqos_priv *eqos = dev_get_priv(dev);
  775. debug("%s(dev=%p):\n", __func__, dev);
  776. clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
  777. /* WAR: Flush TX queue when switching to half-duplex */
  778. setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  779. EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
  780. return 0;
  781. }
  782. static int eqos_set_gmii_speed(struct udevice *dev)
  783. {
  784. struct eqos_priv *eqos = dev_get_priv(dev);
  785. debug("%s(dev=%p):\n", __func__, dev);
  786. clrbits_le32(&eqos->mac_regs->configuration,
  787. EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
  788. return 0;
  789. }
  790. static int eqos_set_mii_speed_100(struct udevice *dev)
  791. {
  792. struct eqos_priv *eqos = dev_get_priv(dev);
  793. debug("%s(dev=%p):\n", __func__, dev);
  794. setbits_le32(&eqos->mac_regs->configuration,
  795. EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
  796. return 0;
  797. }
  798. static int eqos_set_mii_speed_10(struct udevice *dev)
  799. {
  800. struct eqos_priv *eqos = dev_get_priv(dev);
  801. debug("%s(dev=%p):\n", __func__, dev);
  802. clrsetbits_le32(&eqos->mac_regs->configuration,
  803. EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
  804. return 0;
  805. }
  806. static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
  807. {
  808. #ifdef CONFIG_CLK
  809. struct eqos_priv *eqos = dev_get_priv(dev);
  810. ulong rate;
  811. int ret;
  812. debug("%s(dev=%p):\n", __func__, dev);
  813. switch (eqos->phy->speed) {
  814. case SPEED_1000:
  815. rate = 125 * 1000 * 1000;
  816. break;
  817. case SPEED_100:
  818. rate = 25 * 1000 * 1000;
  819. break;
  820. case SPEED_10:
  821. rate = 2.5 * 1000 * 1000;
  822. break;
  823. default:
  824. pr_err("invalid speed %d", eqos->phy->speed);
  825. return -EINVAL;
  826. }
  827. ret = clk_set_rate(&eqos->clk_tx, rate);
  828. if (ret < 0) {
  829. pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
  830. return ret;
  831. }
  832. #endif
  833. return 0;
  834. }
  835. static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
  836. {
  837. return 0;
  838. }
  839. static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
  840. {
  841. struct eqos_priv *eqos = dev_get_priv(dev);
  842. ulong rate;
  843. int ret;
  844. debug("%s(dev=%p):\n", __func__, dev);
  845. switch (eqos->phy->speed) {
  846. case SPEED_1000:
  847. rate = 125 * 1000 * 1000;
  848. break;
  849. case SPEED_100:
  850. rate = 25 * 1000 * 1000;
  851. break;
  852. case SPEED_10:
  853. rate = 2.5 * 1000 * 1000;
  854. break;
  855. default:
  856. pr_err("invalid speed %d", eqos->phy->speed);
  857. return -EINVAL;
  858. }
  859. ret = imx_eqos_txclk_set_rate(rate);
  860. if (ret < 0) {
  861. pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
  862. return ret;
  863. }
  864. return 0;
  865. }
  866. static int eqos_adjust_link(struct udevice *dev)
  867. {
  868. struct eqos_priv *eqos = dev_get_priv(dev);
  869. int ret;
  870. bool en_calibration;
  871. debug("%s(dev=%p):\n", __func__, dev);
  872. if (eqos->phy->duplex)
  873. ret = eqos_set_full_duplex(dev);
  874. else
  875. ret = eqos_set_half_duplex(dev);
  876. if (ret < 0) {
  877. pr_err("eqos_set_*_duplex() failed: %d", ret);
  878. return ret;
  879. }
  880. switch (eqos->phy->speed) {
  881. case SPEED_1000:
  882. en_calibration = true;
  883. ret = eqos_set_gmii_speed(dev);
  884. break;
  885. case SPEED_100:
  886. en_calibration = true;
  887. ret = eqos_set_mii_speed_100(dev);
  888. break;
  889. case SPEED_10:
  890. en_calibration = false;
  891. ret = eqos_set_mii_speed_10(dev);
  892. break;
  893. default:
  894. pr_err("invalid speed %d", eqos->phy->speed);
  895. return -EINVAL;
  896. }
  897. if (ret < 0) {
  898. pr_err("eqos_set_*mii_speed*() failed: %d", ret);
  899. return ret;
  900. }
  901. if (en_calibration) {
  902. ret = eqos->config->ops->eqos_calibrate_pads(dev);
  903. if (ret < 0) {
  904. pr_err("eqos_calibrate_pads() failed: %d",
  905. ret);
  906. return ret;
  907. }
  908. } else {
  909. ret = eqos->config->ops->eqos_disable_calibration(dev);
  910. if (ret < 0) {
  911. pr_err("eqos_disable_calibration() failed: %d",
  912. ret);
  913. return ret;
  914. }
  915. }
  916. ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
  917. if (ret < 0) {
  918. pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
  919. return ret;
  920. }
  921. return 0;
  922. }
  923. static int eqos_write_hwaddr(struct udevice *dev)
  924. {
  925. struct eth_pdata *plat = dev_get_platdata(dev);
  926. struct eqos_priv *eqos = dev_get_priv(dev);
  927. uint32_t val;
  928. /*
  929. * This function may be called before start() or after stop(). At that
  930. * time, on at least some configurations of the EQoS HW, all clocks to
  931. * the EQoS HW block will be stopped, and a reset signal applied. If
  932. * any register access is attempted in this state, bus timeouts or CPU
  933. * hangs may occur. This check prevents that.
  934. *
  935. * A simple solution to this problem would be to not implement
  936. * write_hwaddr(), since start() always writes the MAC address into HW
  937. * anyway. However, it is desirable to implement write_hwaddr() to
  938. * support the case of SW that runs subsequent to U-Boot which expects
  939. * the MAC address to already be programmed into the EQoS registers,
  940. * which must happen irrespective of whether the U-Boot user (or
  941. * scripts) actually made use of the EQoS device, and hence
  942. * irrespective of whether start() was ever called.
  943. *
  944. * Note that this requirement by subsequent SW is not valid for
  945. * Tegra186, and is likely not valid for any non-PCI instantiation of
  946. * the EQoS HW block. This function is implemented solely as
  947. * future-proofing with the expectation the driver will eventually be
  948. * ported to some system where the expectation above is true.
  949. */
  950. if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
  951. return 0;
  952. /* Update the MAC address */
  953. val = (plat->enetaddr[5] << 8) |
  954. (plat->enetaddr[4]);
  955. writel(val, &eqos->mac_regs->address0_high);
  956. val = (plat->enetaddr[3] << 24) |
  957. (plat->enetaddr[2] << 16) |
  958. (plat->enetaddr[1] << 8) |
  959. (plat->enetaddr[0]);
  960. writel(val, &eqos->mac_regs->address0_low);
  961. return 0;
  962. }
  963. static int eqos_read_rom_hwaddr(struct udevice *dev)
  964. {
  965. struct eth_pdata *pdata = dev_get_platdata(dev);
  966. #ifdef CONFIG_ARCH_IMX8M
  967. imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr);
  968. #endif
  969. return !is_valid_ethaddr(pdata->enetaddr);
  970. }
  971. static int eqos_start(struct udevice *dev)
  972. {
  973. struct eqos_priv *eqos = dev_get_priv(dev);
  974. int ret, i;
  975. ulong rate;
  976. u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
  977. ulong last_rx_desc;
  978. debug("%s(dev=%p):\n", __func__, dev);
  979. eqos->tx_desc_idx = 0;
  980. eqos->rx_desc_idx = 0;
  981. ret = eqos->config->ops->eqos_start_clks(dev);
  982. if (ret < 0) {
  983. pr_err("eqos_start_clks() failed: %d", ret);
  984. goto err;
  985. }
  986. ret = eqos->config->ops->eqos_start_resets(dev);
  987. if (ret < 0) {
  988. pr_err("eqos_start_resets() failed: %d", ret);
  989. goto err_stop_clks;
  990. }
  991. udelay(10);
  992. eqos->reg_access_ok = true;
  993. ret = wait_for_bit_le32(&eqos->dma_regs->mode,
  994. EQOS_DMA_MODE_SWR, false,
  995. eqos->config->swr_wait, false);
  996. if (ret) {
  997. pr_err("EQOS_DMA_MODE_SWR stuck");
  998. goto err_stop_resets;
  999. }
  1000. ret = eqos->config->ops->eqos_calibrate_pads(dev);
  1001. if (ret < 0) {
  1002. pr_err("eqos_calibrate_pads() failed: %d", ret);
  1003. goto err_stop_resets;
  1004. }
  1005. rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
  1006. val = (rate / 1000000) - 1;
  1007. writel(val, &eqos->mac_regs->us_tic_counter);
  1008. /*
  1009. * if PHY was already connected and configured,
  1010. * don't need to reconnect/reconfigure again
  1011. */
  1012. if (!eqos->phy) {
  1013. int addr = -1;
  1014. #ifdef CONFIG_DM_ETH_PHY
  1015. addr = eth_phy_get_addr(dev);
  1016. #endif
  1017. #ifdef DWC_NET_PHYADDR
  1018. addr = DWC_NET_PHYADDR;
  1019. #endif
  1020. eqos->phy = phy_connect(eqos->mii, addr, dev,
  1021. eqos->config->interface(dev));
  1022. if (!eqos->phy) {
  1023. pr_err("phy_connect() failed");
  1024. goto err_stop_resets;
  1025. }
  1026. if (eqos->max_speed) {
  1027. ret = phy_set_supported(eqos->phy, eqos->max_speed);
  1028. if (ret) {
  1029. pr_err("phy_set_supported() failed: %d", ret);
  1030. goto err_shutdown_phy;
  1031. }
  1032. }
  1033. ret = phy_config(eqos->phy);
  1034. if (ret < 0) {
  1035. pr_err("phy_config() failed: %d", ret);
  1036. goto err_shutdown_phy;
  1037. }
  1038. }
  1039. ret = phy_startup(eqos->phy);
  1040. if (ret < 0) {
  1041. pr_err("phy_startup() failed: %d", ret);
  1042. goto err_shutdown_phy;
  1043. }
  1044. if (!eqos->phy->link) {
  1045. pr_err("No link");
  1046. goto err_shutdown_phy;
  1047. }
  1048. ret = eqos_adjust_link(dev);
  1049. if (ret < 0) {
  1050. pr_err("eqos_adjust_link() failed: %d", ret);
  1051. goto err_shutdown_phy;
  1052. }
  1053. /* Configure MTL */
  1054. writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
  1055. /* Enable Store and Forward mode for TX */
  1056. /* Program Tx operating mode */
  1057. setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  1058. EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
  1059. (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
  1060. EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
  1061. /* Transmit Queue weight */
  1062. writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
  1063. /* Enable Store and Forward mode for RX, since no jumbo frame */
  1064. setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  1065. EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
  1066. EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
  1067. EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
  1068. /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
  1069. val = readl(&eqos->mac_regs->hw_feature1);
  1070. tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
  1071. EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
  1072. rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
  1073. EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
  1074. /*
  1075. * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
  1076. * r/tqs is encoded as (n / 256) - 1.
  1077. */
  1078. tqs = (128 << tx_fifo_sz) / 256 - 1;
  1079. rqs = (128 << rx_fifo_sz) / 256 - 1;
  1080. clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  1081. EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
  1082. EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
  1083. tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
  1084. clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  1085. EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
  1086. EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
  1087. rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
  1088. /* Flow control used only if each channel gets 4KB or more FIFO */
  1089. if (rqs >= ((4096 / 256) - 1)) {
  1090. u32 rfd, rfa;
  1091. setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  1092. EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
  1093. /*
  1094. * Set Threshold for Activating Flow Contol space for min 2
  1095. * frames ie, (1500 * 1) = 1500 bytes.
  1096. *
  1097. * Set Threshold for Deactivating Flow Contol for space of
  1098. * min 1 frame (frame size 1500bytes) in receive fifo
  1099. */
  1100. if (rqs == ((4096 / 256) - 1)) {
  1101. /*
  1102. * This violates the above formula because of FIFO size
  1103. * limit therefore overflow may occur inspite of this.
  1104. */
  1105. rfd = 0x3; /* Full-3K */
  1106. rfa = 0x1; /* Full-1.5K */
  1107. } else if (rqs == ((8192 / 256) - 1)) {
  1108. rfd = 0x6; /* Full-4K */
  1109. rfa = 0xa; /* Full-6K */
  1110. } else if (rqs == ((16384 / 256) - 1)) {
  1111. rfd = 0x6; /* Full-4K */
  1112. rfa = 0x12; /* Full-10K */
  1113. } else {
  1114. rfd = 0x6; /* Full-4K */
  1115. rfa = 0x1E; /* Full-16K */
  1116. }
  1117. clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  1118. (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
  1119. EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
  1120. (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
  1121. EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
  1122. (rfd <<
  1123. EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
  1124. (rfa <<
  1125. EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
  1126. }
  1127. /* Configure MAC */
  1128. clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
  1129. EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
  1130. EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
  1131. eqos->config->config_mac <<
  1132. EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
  1133. clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
  1134. EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
  1135. EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
  1136. 0x2 <<
  1137. EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
  1138. /* Multicast and Broadcast Queue Enable */
  1139. setbits_le32(&eqos->mac_regs->unused_0a4,
  1140. 0x00100000);
  1141. /* enable promise mode */
  1142. setbits_le32(&eqos->mac_regs->unused_004[1],
  1143. 0x1);
  1144. /* Set TX flow control parameters */
  1145. /* Set Pause Time */
  1146. setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
  1147. 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
  1148. /* Assign priority for TX flow control */
  1149. clrbits_le32(&eqos->mac_regs->txq_prty_map0,
  1150. EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
  1151. EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
  1152. /* Assign priority for RX flow control */
  1153. clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
  1154. EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
  1155. EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
  1156. /* Enable flow control */
  1157. setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
  1158. EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
  1159. setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
  1160. EQOS_MAC_RX_FLOW_CTRL_RFE);
  1161. clrsetbits_le32(&eqos->mac_regs->configuration,
  1162. EQOS_MAC_CONFIGURATION_GPSLCE |
  1163. EQOS_MAC_CONFIGURATION_WD |
  1164. EQOS_MAC_CONFIGURATION_JD |
  1165. EQOS_MAC_CONFIGURATION_JE,
  1166. EQOS_MAC_CONFIGURATION_CST |
  1167. EQOS_MAC_CONFIGURATION_ACS);
  1168. eqos_write_hwaddr(dev);
  1169. /* Configure DMA */
  1170. /* Enable OSP mode */
  1171. setbits_le32(&eqos->dma_regs->ch0_tx_control,
  1172. EQOS_DMA_CH0_TX_CONTROL_OSP);
  1173. /* RX buffer size. Must be a multiple of bus width */
  1174. clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
  1175. EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
  1176. EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
  1177. EQOS_MAX_PACKET_SIZE <<
  1178. EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
  1179. setbits_le32(&eqos->dma_regs->ch0_control,
  1180. EQOS_DMA_CH0_CONTROL_PBLX8);
  1181. /*
  1182. * Burst length must be < 1/2 FIFO size.
  1183. * FIFO size in tqs is encoded as (n / 256) - 1.
  1184. * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
  1185. * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
  1186. */
  1187. pbl = tqs + 1;
  1188. if (pbl > 32)
  1189. pbl = 32;
  1190. clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
  1191. EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
  1192. EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
  1193. pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
  1194. clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
  1195. EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
  1196. EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
  1197. 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
  1198. /* DMA performance configuration */
  1199. val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
  1200. EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
  1201. EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
  1202. writel(val, &eqos->dma_regs->sysbus_mode);
  1203. /* Set up descriptors */
  1204. memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
  1205. for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
  1206. struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
  1207. rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
  1208. (i * EQOS_MAX_PACKET_SIZE));
  1209. rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
  1210. mb();
  1211. eqos->config->ops->eqos_flush_desc(rx_desc);
  1212. eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
  1213. (i * EQOS_MAX_PACKET_SIZE),
  1214. EQOS_MAX_PACKET_SIZE);
  1215. }
  1216. writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
  1217. writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
  1218. writel(EQOS_DESCRIPTORS_TX - 1,
  1219. &eqos->dma_regs->ch0_txdesc_ring_length);
  1220. writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
  1221. writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
  1222. writel(EQOS_DESCRIPTORS_RX - 1,
  1223. &eqos->dma_regs->ch0_rxdesc_ring_length);
  1224. /* Enable everything */
  1225. setbits_le32(&eqos->dma_regs->ch0_tx_control,
  1226. EQOS_DMA_CH0_TX_CONTROL_ST);
  1227. setbits_le32(&eqos->dma_regs->ch0_rx_control,
  1228. EQOS_DMA_CH0_RX_CONTROL_SR);
  1229. setbits_le32(&eqos->mac_regs->configuration,
  1230. EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
  1231. /* TX tail pointer not written until we need to TX a packet */
  1232. /*
  1233. * Point RX tail pointer at last descriptor. Ideally, we'd point at the
  1234. * first descriptor, implying all descriptors were available. However,
  1235. * that's not distinguishable from none of the descriptors being
  1236. * available.
  1237. */
  1238. last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
  1239. writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
  1240. eqos->started = true;
  1241. debug("%s: OK\n", __func__);
  1242. return 0;
  1243. err_shutdown_phy:
  1244. phy_shutdown(eqos->phy);
  1245. err_stop_resets:
  1246. eqos->config->ops->eqos_stop_resets(dev);
  1247. err_stop_clks:
  1248. eqos->config->ops->eqos_stop_clks(dev);
  1249. err:
  1250. pr_err("FAILED: %d", ret);
  1251. return ret;
  1252. }
  1253. static void eqos_stop(struct udevice *dev)
  1254. {
  1255. struct eqos_priv *eqos = dev_get_priv(dev);
  1256. int i;
  1257. debug("%s(dev=%p):\n", __func__, dev);
  1258. if (!eqos->started)
  1259. return;
  1260. eqos->started = false;
  1261. eqos->reg_access_ok = false;
  1262. /* Disable TX DMA */
  1263. clrbits_le32(&eqos->dma_regs->ch0_tx_control,
  1264. EQOS_DMA_CH0_TX_CONTROL_ST);
  1265. /* Wait for TX all packets to drain out of MTL */
  1266. for (i = 0; i < 1000000; i++) {
  1267. u32 val = readl(&eqos->mtl_regs->txq0_debug);
  1268. u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
  1269. EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
  1270. u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
  1271. if ((trcsts != 1) && (!txqsts))
  1272. break;
  1273. }
  1274. /* Turn off MAC TX and RX */
  1275. clrbits_le32(&eqos->mac_regs->configuration,
  1276. EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
  1277. /* Wait for all RX packets to drain out of MTL */
  1278. for (i = 0; i < 1000000; i++) {
  1279. u32 val = readl(&eqos->mtl_regs->rxq0_debug);
  1280. u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
  1281. EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
  1282. u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
  1283. EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
  1284. if ((!prxq) && (!rxqsts))
  1285. break;
  1286. }
  1287. /* Turn off RX DMA */
  1288. clrbits_le32(&eqos->dma_regs->ch0_rx_control,
  1289. EQOS_DMA_CH0_RX_CONTROL_SR);
  1290. if (eqos->phy) {
  1291. phy_shutdown(eqos->phy);
  1292. }
  1293. eqos->config->ops->eqos_stop_resets(dev);
  1294. eqos->config->ops->eqos_stop_clks(dev);
  1295. debug("%s: OK\n", __func__);
  1296. }
  1297. static int eqos_send(struct udevice *dev, void *packet, int length)
  1298. {
  1299. struct eqos_priv *eqos = dev_get_priv(dev);
  1300. struct eqos_desc *tx_desc;
  1301. int i;
  1302. debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
  1303. length);
  1304. memcpy(eqos->tx_dma_buf, packet, length);
  1305. eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
  1306. tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
  1307. eqos->tx_desc_idx++;
  1308. eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
  1309. tx_desc->des0 = (ulong)eqos->tx_dma_buf;
  1310. tx_desc->des1 = 0;
  1311. tx_desc->des2 = length;
  1312. /*
  1313. * Make sure that if HW sees the _OWN write below, it will see all the
  1314. * writes to the rest of the descriptor too.
  1315. */
  1316. mb();
  1317. tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
  1318. eqos->config->ops->eqos_flush_desc(tx_desc);
  1319. writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])),
  1320. &eqos->dma_regs->ch0_txdesc_tail_pointer);
  1321. for (i = 0; i < 1000000; i++) {
  1322. eqos->config->ops->eqos_inval_desc(tx_desc);
  1323. if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
  1324. return 0;
  1325. udelay(1);
  1326. }
  1327. debug("%s: TX timeout\n", __func__);
  1328. return -ETIMEDOUT;
  1329. }
  1330. static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
  1331. {
  1332. struct eqos_priv *eqos = dev_get_priv(dev);
  1333. struct eqos_desc *rx_desc;
  1334. int length;
  1335. debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
  1336. rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
  1337. eqos->config->ops->eqos_inval_desc(rx_desc);
  1338. if (rx_desc->des3 & EQOS_DESC3_OWN) {
  1339. debug("%s: RX packet not available\n", __func__);
  1340. return -EAGAIN;
  1341. }
  1342. *packetp = eqos->rx_dma_buf +
  1343. (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
  1344. length = rx_desc->des3 & 0x7fff;
  1345. debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
  1346. eqos->config->ops->eqos_inval_buffer(*packetp, length);
  1347. return length;
  1348. }
  1349. static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
  1350. {
  1351. struct eqos_priv *eqos = dev_get_priv(dev);
  1352. uchar *packet_expected;
  1353. struct eqos_desc *rx_desc;
  1354. debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
  1355. packet_expected = eqos->rx_dma_buf +
  1356. (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
  1357. if (packet != packet_expected) {
  1358. debug("%s: Unexpected packet (expected %p)\n", __func__,
  1359. packet_expected);
  1360. return -EINVAL;
  1361. }
  1362. eqos->config->ops->eqos_inval_buffer(packet, length);
  1363. rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
  1364. rx_desc->des0 = 0;
  1365. mb();
  1366. eqos->config->ops->eqos_flush_desc(rx_desc);
  1367. eqos->config->ops->eqos_inval_buffer(packet, length);
  1368. rx_desc->des0 = (u32)(ulong)packet;
  1369. rx_desc->des1 = 0;
  1370. rx_desc->des2 = 0;
  1371. /*
  1372. * Make sure that if HW sees the _OWN write below, it will see all the
  1373. * writes to the rest of the descriptor too.
  1374. */
  1375. mb();
  1376. rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
  1377. eqos->config->ops->eqos_flush_desc(rx_desc);
  1378. writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
  1379. eqos->rx_desc_idx++;
  1380. eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
  1381. return 0;
  1382. }
  1383. static int eqos_probe_resources_core(struct udevice *dev)
  1384. {
  1385. struct eqos_priv *eqos = dev_get_priv(dev);
  1386. int ret;
  1387. debug("%s(dev=%p):\n", __func__, dev);
  1388. eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
  1389. EQOS_DESCRIPTORS_RX);
  1390. if (!eqos->descs) {
  1391. debug("%s: eqos_alloc_descs() failed\n", __func__);
  1392. ret = -ENOMEM;
  1393. goto err;
  1394. }
  1395. eqos->tx_descs = (struct eqos_desc *)eqos->descs;
  1396. eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
  1397. debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
  1398. eqos->rx_descs);
  1399. eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
  1400. if (!eqos->tx_dma_buf) {
  1401. debug("%s: memalign(tx_dma_buf) failed\n", __func__);
  1402. ret = -ENOMEM;
  1403. goto err_free_descs;
  1404. }
  1405. debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
  1406. eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
  1407. if (!eqos->rx_dma_buf) {
  1408. debug("%s: memalign(rx_dma_buf) failed\n", __func__);
  1409. ret = -ENOMEM;
  1410. goto err_free_tx_dma_buf;
  1411. }
  1412. debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
  1413. eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
  1414. if (!eqos->rx_pkt) {
  1415. debug("%s: malloc(rx_pkt) failed\n", __func__);
  1416. ret = -ENOMEM;
  1417. goto err_free_rx_dma_buf;
  1418. }
  1419. debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
  1420. eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
  1421. EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
  1422. debug("%s: OK\n", __func__);
  1423. return 0;
  1424. err_free_rx_dma_buf:
  1425. free(eqos->rx_dma_buf);
  1426. err_free_tx_dma_buf:
  1427. free(eqos->tx_dma_buf);
  1428. err_free_descs:
  1429. eqos_free_descs(eqos->descs);
  1430. err:
  1431. debug("%s: returns %d\n", __func__, ret);
  1432. return ret;
  1433. }
  1434. static int eqos_remove_resources_core(struct udevice *dev)
  1435. {
  1436. struct eqos_priv *eqos = dev_get_priv(dev);
  1437. debug("%s(dev=%p):\n", __func__, dev);
  1438. free(eqos->rx_pkt);
  1439. free(eqos->rx_dma_buf);
  1440. free(eqos->tx_dma_buf);
  1441. eqos_free_descs(eqos->descs);
  1442. debug("%s: OK\n", __func__);
  1443. return 0;
  1444. }
  1445. static int eqos_probe_resources_tegra186(struct udevice *dev)
  1446. {
  1447. struct eqos_priv *eqos = dev_get_priv(dev);
  1448. int ret;
  1449. debug("%s(dev=%p):\n", __func__, dev);
  1450. ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
  1451. if (ret) {
  1452. pr_err("reset_get_by_name(rst) failed: %d", ret);
  1453. return ret;
  1454. }
  1455. ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1456. &eqos->phy_reset_gpio,
  1457. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  1458. if (ret) {
  1459. pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
  1460. goto err_free_reset_eqos;
  1461. }
  1462. ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
  1463. if (ret) {
  1464. pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
  1465. goto err_free_gpio_phy_reset;
  1466. }
  1467. ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
  1468. if (ret) {
  1469. pr_err("clk_get_by_name(master_bus) failed: %d", ret);
  1470. goto err_free_clk_slave_bus;
  1471. }
  1472. ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
  1473. if (ret) {
  1474. pr_err("clk_get_by_name(rx) failed: %d", ret);
  1475. goto err_free_clk_master_bus;
  1476. }
  1477. ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
  1478. if (ret) {
  1479. pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
  1480. goto err_free_clk_rx;
  1481. return ret;
  1482. }
  1483. ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
  1484. if (ret) {
  1485. pr_err("clk_get_by_name(tx) failed: %d", ret);
  1486. goto err_free_clk_ptp_ref;
  1487. }
  1488. debug("%s: OK\n", __func__);
  1489. return 0;
  1490. err_free_clk_ptp_ref:
  1491. clk_free(&eqos->clk_ptp_ref);
  1492. err_free_clk_rx:
  1493. clk_free(&eqos->clk_rx);
  1494. err_free_clk_master_bus:
  1495. clk_free(&eqos->clk_master_bus);
  1496. err_free_clk_slave_bus:
  1497. clk_free(&eqos->clk_slave_bus);
  1498. err_free_gpio_phy_reset:
  1499. dm_gpio_free(dev, &eqos->phy_reset_gpio);
  1500. err_free_reset_eqos:
  1501. reset_free(&eqos->reset_ctl);
  1502. debug("%s: returns %d\n", __func__, ret);
  1503. return ret;
  1504. }
  1505. /* board-specific Ethernet Interface initializations. */
  1506. __weak int board_interface_eth_init(struct udevice *dev,
  1507. phy_interface_t interface_type)
  1508. {
  1509. return 0;
  1510. }
  1511. static int eqos_probe_resources_stm32(struct udevice *dev)
  1512. {
  1513. struct eqos_priv *eqos = dev_get_priv(dev);
  1514. int ret;
  1515. phy_interface_t interface;
  1516. struct ofnode_phandle_args phandle_args;
  1517. debug("%s(dev=%p):\n", __func__, dev);
  1518. interface = eqos->config->interface(dev);
  1519. if (interface == PHY_INTERFACE_MODE_NONE) {
  1520. pr_err("Invalid PHY interface\n");
  1521. return -EINVAL;
  1522. }
  1523. ret = board_interface_eth_init(dev, interface);
  1524. if (ret)
  1525. return -EINVAL;
  1526. eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
  1527. ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
  1528. if (ret) {
  1529. pr_err("clk_get_by_name(master_bus) failed: %d", ret);
  1530. goto err_probe;
  1531. }
  1532. ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
  1533. if (ret) {
  1534. pr_err("clk_get_by_name(rx) failed: %d", ret);
  1535. goto err_free_clk_master_bus;
  1536. }
  1537. ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
  1538. if (ret) {
  1539. pr_err("clk_get_by_name(tx) failed: %d", ret);
  1540. goto err_free_clk_rx;
  1541. }
  1542. /* Get ETH_CLK clocks (optional) */
  1543. ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
  1544. if (ret)
  1545. pr_warn("No phy clock provided %d", ret);
  1546. eqos->phyaddr = -1;
  1547. ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  1548. &phandle_args);
  1549. if (!ret) {
  1550. /* search "reset-gpios" in phy node */
  1551. ret = gpio_request_by_name_nodev(phandle_args.node,
  1552. "reset-gpios", 0,
  1553. &eqos->phy_reset_gpio,
  1554. GPIOD_IS_OUT |
  1555. GPIOD_IS_OUT_ACTIVE);
  1556. if (ret)
  1557. pr_warn("gpio_request_by_name(phy reset) not provided %d",
  1558. ret);
  1559. eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
  1560. "reg", -1);
  1561. }
  1562. debug("%s: OK\n", __func__);
  1563. return 0;
  1564. err_free_clk_rx:
  1565. clk_free(&eqos->clk_rx);
  1566. err_free_clk_master_bus:
  1567. clk_free(&eqos->clk_master_bus);
  1568. err_probe:
  1569. debug("%s: returns %d\n", __func__, ret);
  1570. return ret;
  1571. }
  1572. static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
  1573. {
  1574. const char *phy_mode;
  1575. phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
  1576. debug("%s(dev=%p):\n", __func__, dev);
  1577. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1578. NULL);
  1579. if (phy_mode)
  1580. interface = phy_get_interface_by_name(phy_mode);
  1581. return interface;
  1582. }
  1583. static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
  1584. {
  1585. return PHY_INTERFACE_MODE_MII;
  1586. }
  1587. static int eqos_probe_resources_imx(struct udevice *dev)
  1588. {
  1589. struct eqos_priv *eqos = dev_get_priv(dev);
  1590. phy_interface_t interface;
  1591. debug("%s(dev=%p):\n", __func__, dev);
  1592. interface = eqos->config->interface(dev);
  1593. if (interface == PHY_INTERFACE_MODE_NONE) {
  1594. pr_err("Invalid PHY interface\n");
  1595. return -EINVAL;
  1596. }
  1597. debug("%s: OK\n", __func__);
  1598. return 0;
  1599. }
  1600. static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
  1601. {
  1602. const char *phy_mode;
  1603. phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
  1604. debug("%s(dev=%p):\n", __func__, dev);
  1605. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1606. NULL);
  1607. if (phy_mode)
  1608. interface = phy_get_interface_by_name(phy_mode);
  1609. return interface;
  1610. }
  1611. static int eqos_remove_resources_tegra186(struct udevice *dev)
  1612. {
  1613. struct eqos_priv *eqos = dev_get_priv(dev);
  1614. debug("%s(dev=%p):\n", __func__, dev);
  1615. #ifdef CONFIG_CLK
  1616. clk_free(&eqos->clk_tx);
  1617. clk_free(&eqos->clk_ptp_ref);
  1618. clk_free(&eqos->clk_rx);
  1619. clk_free(&eqos->clk_slave_bus);
  1620. clk_free(&eqos->clk_master_bus);
  1621. #endif
  1622. dm_gpio_free(dev, &eqos->phy_reset_gpio);
  1623. reset_free(&eqos->reset_ctl);
  1624. debug("%s: OK\n", __func__);
  1625. return 0;
  1626. }
  1627. static int eqos_remove_resources_stm32(struct udevice *dev)
  1628. {
  1629. #ifdef CONFIG_CLK
  1630. struct eqos_priv *eqos = dev_get_priv(dev);
  1631. debug("%s(dev=%p):\n", __func__, dev);
  1632. clk_free(&eqos->clk_tx);
  1633. clk_free(&eqos->clk_rx);
  1634. clk_free(&eqos->clk_master_bus);
  1635. if (clk_valid(&eqos->clk_ck))
  1636. clk_free(&eqos->clk_ck);
  1637. #endif
  1638. if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
  1639. dm_gpio_free(dev, &eqos->phy_reset_gpio);
  1640. debug("%s: OK\n", __func__);
  1641. return 0;
  1642. }
  1643. static int eqos_remove_resources_imx(struct udevice *dev)
  1644. {
  1645. return 0;
  1646. }
  1647. static int eqos_probe(struct udevice *dev)
  1648. {
  1649. struct eqos_priv *eqos = dev_get_priv(dev);
  1650. int ret;
  1651. debug("%s(dev=%p):\n", __func__, dev);
  1652. eqos->dev = dev;
  1653. eqos->config = (void *)dev_get_driver_data(dev);
  1654. eqos->regs = devfdt_get_addr(dev);
  1655. if (eqos->regs == FDT_ADDR_T_NONE) {
  1656. pr_err("devfdt_get_addr() failed");
  1657. return -ENODEV;
  1658. }
  1659. eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
  1660. eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
  1661. eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
  1662. eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
  1663. ret = eqos_probe_resources_core(dev);
  1664. if (ret < 0) {
  1665. pr_err("eqos_probe_resources_core() failed: %d", ret);
  1666. return ret;
  1667. }
  1668. ret = eqos->config->ops->eqos_probe_resources(dev);
  1669. if (ret < 0) {
  1670. pr_err("eqos_probe_resources() failed: %d", ret);
  1671. goto err_remove_resources_core;
  1672. }
  1673. #ifdef CONFIG_DM_ETH_PHY
  1674. eqos->mii = eth_phy_get_mdio_bus(dev);
  1675. #endif
  1676. if (!eqos->mii) {
  1677. eqos->mii = mdio_alloc();
  1678. if (!eqos->mii) {
  1679. pr_err("mdio_alloc() failed");
  1680. ret = -ENOMEM;
  1681. goto err_remove_resources_tegra;
  1682. }
  1683. eqos->mii->read = eqos_mdio_read;
  1684. eqos->mii->write = eqos_mdio_write;
  1685. eqos->mii->priv = eqos;
  1686. strcpy(eqos->mii->name, dev->name);
  1687. ret = mdio_register(eqos->mii);
  1688. if (ret < 0) {
  1689. pr_err("mdio_register() failed: %d", ret);
  1690. goto err_free_mdio;
  1691. }
  1692. }
  1693. #ifdef CONFIG_DM_ETH_PHY
  1694. eth_phy_set_mdio_bus(dev, eqos->mii);
  1695. #endif
  1696. debug("%s: OK\n", __func__);
  1697. return 0;
  1698. err_free_mdio:
  1699. mdio_free(eqos->mii);
  1700. err_remove_resources_tegra:
  1701. eqos->config->ops->eqos_remove_resources(dev);
  1702. err_remove_resources_core:
  1703. eqos_remove_resources_core(dev);
  1704. debug("%s: returns %d\n", __func__, ret);
  1705. return ret;
  1706. }
  1707. static int eqos_remove(struct udevice *dev)
  1708. {
  1709. struct eqos_priv *eqos = dev_get_priv(dev);
  1710. debug("%s(dev=%p):\n", __func__, dev);
  1711. mdio_unregister(eqos->mii);
  1712. mdio_free(eqos->mii);
  1713. eqos->config->ops->eqos_remove_resources(dev);
  1714. eqos_probe_resources_core(dev);
  1715. debug("%s: OK\n", __func__);
  1716. return 0;
  1717. }
  1718. static const struct eth_ops eqos_ops = {
  1719. .start = eqos_start,
  1720. .stop = eqos_stop,
  1721. .send = eqos_send,
  1722. .recv = eqos_recv,
  1723. .free_pkt = eqos_free_pkt,
  1724. .write_hwaddr = eqos_write_hwaddr,
  1725. .read_rom_hwaddr = eqos_read_rom_hwaddr,
  1726. };
  1727. static struct eqos_ops eqos_tegra186_ops = {
  1728. .eqos_inval_desc = eqos_inval_desc_tegra186,
  1729. .eqos_flush_desc = eqos_flush_desc_tegra186,
  1730. .eqos_inval_buffer = eqos_inval_buffer_tegra186,
  1731. .eqos_flush_buffer = eqos_flush_buffer_tegra186,
  1732. .eqos_probe_resources = eqos_probe_resources_tegra186,
  1733. .eqos_remove_resources = eqos_remove_resources_tegra186,
  1734. .eqos_stop_resets = eqos_stop_resets_tegra186,
  1735. .eqos_start_resets = eqos_start_resets_tegra186,
  1736. .eqos_stop_clks = eqos_stop_clks_tegra186,
  1737. .eqos_start_clks = eqos_start_clks_tegra186,
  1738. .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
  1739. .eqos_disable_calibration = eqos_disable_calibration_tegra186,
  1740. .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
  1741. .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
  1742. };
  1743. static const struct eqos_config eqos_tegra186_config = {
  1744. .reg_access_always_ok = false,
  1745. .mdio_wait = 10,
  1746. .swr_wait = 10,
  1747. .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
  1748. .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
  1749. .interface = eqos_get_interface_tegra186,
  1750. .ops = &eqos_tegra186_ops
  1751. };
  1752. static struct eqos_ops eqos_stm32_ops = {
  1753. .eqos_inval_desc = eqos_inval_desc_generic,
  1754. .eqos_flush_desc = eqos_flush_desc_generic,
  1755. .eqos_inval_buffer = eqos_inval_buffer_generic,
  1756. .eqos_flush_buffer = eqos_flush_buffer_generic,
  1757. .eqos_probe_resources = eqos_probe_resources_stm32,
  1758. .eqos_remove_resources = eqos_remove_resources_stm32,
  1759. .eqos_stop_resets = eqos_stop_resets_stm32,
  1760. .eqos_start_resets = eqos_start_resets_stm32,
  1761. .eqos_stop_clks = eqos_stop_clks_stm32,
  1762. .eqos_start_clks = eqos_start_clks_stm32,
  1763. .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
  1764. .eqos_disable_calibration = eqos_disable_calibration_stm32,
  1765. .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
  1766. .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
  1767. };
  1768. static const struct eqos_config eqos_stm32_config = {
  1769. .reg_access_always_ok = false,
  1770. .mdio_wait = 10000,
  1771. .swr_wait = 50,
  1772. .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
  1773. .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
  1774. .interface = eqos_get_interface_stm32,
  1775. .ops = &eqos_stm32_ops
  1776. };
  1777. static struct eqos_ops eqos_imx_ops = {
  1778. .eqos_inval_desc = eqos_inval_desc_generic,
  1779. .eqos_flush_desc = eqos_flush_desc_generic,
  1780. .eqos_inval_buffer = eqos_inval_buffer_generic,
  1781. .eqos_flush_buffer = eqos_flush_buffer_generic,
  1782. .eqos_probe_resources = eqos_probe_resources_imx,
  1783. .eqos_remove_resources = eqos_remove_resources_imx,
  1784. .eqos_stop_resets = eqos_stop_resets_imx,
  1785. .eqos_start_resets = eqos_start_resets_imx,
  1786. .eqos_stop_clks = eqos_stop_clks_imx,
  1787. .eqos_start_clks = eqos_start_clks_imx,
  1788. .eqos_calibrate_pads = eqos_calibrate_pads_imx,
  1789. .eqos_disable_calibration = eqos_disable_calibration_imx,
  1790. .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
  1791. .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
  1792. };
  1793. struct eqos_config eqos_imx_config = {
  1794. .reg_access_always_ok = false,
  1795. .mdio_wait = 10000,
  1796. .swr_wait = 50,
  1797. .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
  1798. .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
  1799. .interface = eqos_get_interface_imx,
  1800. .ops = &eqos_imx_ops
  1801. };
  1802. static const struct udevice_id eqos_ids[] = {
  1803. {
  1804. .compatible = "nvidia,tegra186-eqos",
  1805. .data = (ulong)&eqos_tegra186_config
  1806. },
  1807. {
  1808. .compatible = "st,stm32mp1-dwmac",
  1809. .data = (ulong)&eqos_stm32_config
  1810. },
  1811. {
  1812. .compatible = "fsl,imx-eqos",
  1813. .data = (ulong)&eqos_imx_config
  1814. },
  1815. { }
  1816. };
  1817. U_BOOT_DRIVER(eth_eqos) = {
  1818. .name = "eth_eqos",
  1819. .id = UCLASS_ETH,
  1820. .of_match = of_match_ptr(eqos_ids),
  1821. .probe = eqos_probe,
  1822. .remove = eqos_remove,
  1823. .ops = &eqos_ops,
  1824. .priv_auto_alloc_size = sizeof(struct eqos_priv),
  1825. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1826. };