stm32_gpio.c 7.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <log.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/arch/stm32.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #include <linux/errno.h>
  18. #include <linux/io.h>
  19. #define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
  20. #define MODE_BITS_MASK 3
  21. #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
  22. #define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
  23. #define PUPD_MASK 3
  24. #define OTYPE_BITS(gpio_pin) (gpio_pin)
  25. #define OTYPE_MSK 1
  26. static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
  27. int idx,
  28. int mode)
  29. {
  30. int bits_index;
  31. int mask;
  32. bits_index = MODE_BITS(idx);
  33. mask = MODE_BITS_MASK << bits_index;
  34. clrsetbits_le32(&regs->moder, mask, mode << bits_index);
  35. }
  36. static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
  37. {
  38. return (readl(&regs->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
  39. }
  40. static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
  41. int idx,
  42. enum stm32_gpio_otype otype)
  43. {
  44. int bits;
  45. bits = OTYPE_BITS(idx);
  46. clrsetbits_le32(&regs->otyper, OTYPE_MSK << bits, otype << bits);
  47. }
  48. static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
  49. int idx)
  50. {
  51. return (readl(&regs->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
  52. }
  53. static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
  54. int idx,
  55. enum stm32_gpio_pupd pupd)
  56. {
  57. int bits;
  58. bits = PUPD_BITS(idx);
  59. clrsetbits_le32(&regs->pupdr, PUPD_MASK << bits, pupd << bits);
  60. }
  61. static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
  62. int idx)
  63. {
  64. return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
  65. }
  66. /*
  67. * convert gpio offset to gpio index taking into account gpio holes
  68. * into gpio bank
  69. */
  70. int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
  71. {
  72. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  73. unsigned int idx = 0;
  74. int i;
  75. for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
  76. if (priv->gpio_range & BIT(i)) {
  77. if (idx == offset)
  78. return idx;
  79. idx++;
  80. }
  81. }
  82. /* shouldn't happen */
  83. return -EINVAL;
  84. }
  85. static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
  86. {
  87. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  88. struct stm32_gpio_regs *regs = priv->regs;
  89. int idx;
  90. idx = stm32_offset_to_index(dev, offset);
  91. if (idx < 0)
  92. return idx;
  93. stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
  94. return 0;
  95. }
  96. static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
  97. int value)
  98. {
  99. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  100. struct stm32_gpio_regs *regs = priv->regs;
  101. int idx;
  102. idx = stm32_offset_to_index(dev, offset);
  103. if (idx < 0)
  104. return idx;
  105. stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
  106. writel(BSRR_BIT(idx, value), &regs->bsrr);
  107. return 0;
  108. }
  109. static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
  110. {
  111. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  112. struct stm32_gpio_regs *regs = priv->regs;
  113. int idx;
  114. idx = stm32_offset_to_index(dev, offset);
  115. if (idx < 0)
  116. return idx;
  117. return readl(&regs->idr) & BIT(idx) ? 1 : 0;
  118. }
  119. static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
  120. {
  121. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  122. struct stm32_gpio_regs *regs = priv->regs;
  123. int idx;
  124. idx = stm32_offset_to_index(dev, offset);
  125. if (idx < 0)
  126. return idx;
  127. writel(BSRR_BIT(idx, value), &regs->bsrr);
  128. return 0;
  129. }
  130. static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
  131. {
  132. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  133. struct stm32_gpio_regs *regs = priv->regs;
  134. int bits_index;
  135. int mask;
  136. int idx;
  137. u32 mode;
  138. idx = stm32_offset_to_index(dev, offset);
  139. if (idx < 0)
  140. return idx;
  141. bits_index = MODE_BITS(idx);
  142. mask = MODE_BITS_MASK << bits_index;
  143. mode = (readl(&regs->moder) & mask) >> bits_index;
  144. if (mode == STM32_GPIO_MODE_OUT)
  145. return GPIOF_OUTPUT;
  146. if (mode == STM32_GPIO_MODE_IN)
  147. return GPIOF_INPUT;
  148. if (mode == STM32_GPIO_MODE_AN)
  149. return GPIOF_UNUSED;
  150. return GPIOF_FUNC;
  151. }
  152. static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
  153. ulong flags)
  154. {
  155. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  156. struct stm32_gpio_regs *regs = priv->regs;
  157. int idx;
  158. idx = stm32_offset_to_index(dev, offset);
  159. if (idx < 0)
  160. return idx;
  161. if (flags & GPIOD_IS_OUT) {
  162. int value = GPIOD_FLAGS_OUTPUT(flags);
  163. if (flags & GPIOD_OPEN_DRAIN)
  164. stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
  165. else
  166. stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
  167. stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
  168. writel(BSRR_BIT(idx, value), &regs->bsrr);
  169. } else if (flags & GPIOD_IS_IN) {
  170. stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
  171. if (flags & GPIOD_PULL_UP)
  172. stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
  173. else if (flags & GPIOD_PULL_DOWN)
  174. stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
  175. }
  176. return 0;
  177. }
  178. static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
  179. ulong *flags)
  180. {
  181. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  182. struct stm32_gpio_regs *regs = priv->regs;
  183. int idx;
  184. ulong dir_flags = 0;
  185. idx = stm32_offset_to_index(dev, offset);
  186. if (idx < 0)
  187. return idx;
  188. switch (stm32_gpio_get_moder(regs, idx)) {
  189. case STM32_GPIO_MODE_OUT:
  190. dir_flags |= GPIOD_IS_OUT;
  191. if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
  192. dir_flags |= GPIOD_OPEN_DRAIN;
  193. if (readl(&regs->idr) & BIT(idx))
  194. dir_flags |= GPIOD_IS_OUT_ACTIVE;
  195. break;
  196. case STM32_GPIO_MODE_IN:
  197. dir_flags |= GPIOD_IS_IN;
  198. switch (stm32_gpio_get_pupd(regs, idx)) {
  199. case STM32_GPIO_PUPD_UP:
  200. dir_flags |= GPIOD_PULL_UP;
  201. break;
  202. case STM32_GPIO_PUPD_DOWN:
  203. dir_flags |= GPIOD_PULL_DOWN;
  204. break;
  205. default:
  206. break;
  207. }
  208. break;
  209. default:
  210. break;
  211. }
  212. *flags = dir_flags;
  213. return 0;
  214. }
  215. static const struct dm_gpio_ops gpio_stm32_ops = {
  216. .direction_input = stm32_gpio_direction_input,
  217. .direction_output = stm32_gpio_direction_output,
  218. .get_value = stm32_gpio_get_value,
  219. .set_value = stm32_gpio_set_value,
  220. .get_function = stm32_gpio_get_function,
  221. .set_dir_flags = stm32_gpio_set_dir_flags,
  222. .get_dir_flags = stm32_gpio_get_dir_flags,
  223. };
  224. static int gpio_stm32_probe(struct udevice *dev)
  225. {
  226. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  227. struct clk clk;
  228. fdt_addr_t addr;
  229. int ret;
  230. addr = dev_read_addr(dev);
  231. if (addr == FDT_ADDR_T_NONE)
  232. return -EINVAL;
  233. priv->regs = (struct stm32_gpio_regs *)addr;
  234. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  235. struct ofnode_phandle_args args;
  236. const char *name;
  237. int i;
  238. name = dev_read_string(dev, "st,bank-name");
  239. if (!name)
  240. return -EINVAL;
  241. uc_priv->bank_name = name;
  242. i = 0;
  243. ret = dev_read_phandle_with_args(dev, "gpio-ranges",
  244. NULL, 3, i, &args);
  245. if (ret == -ENOENT) {
  246. uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
  247. priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
  248. }
  249. while (ret != -ENOENT) {
  250. priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
  251. args.args[0]);
  252. uc_priv->gpio_count += args.args[2];
  253. ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
  254. ++i, &args);
  255. }
  256. dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
  257. (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
  258. priv->gpio_range);
  259. ret = clk_get_by_index(dev, 0, &clk);
  260. if (ret < 0)
  261. return ret;
  262. ret = clk_enable(&clk);
  263. if (ret) {
  264. dev_err(dev, "failed to enable clock\n");
  265. return ret;
  266. }
  267. debug("clock enabled for device %s\n", dev->name);
  268. return 0;
  269. }
  270. U_BOOT_DRIVER(gpio_stm32) = {
  271. .name = "gpio_stm32",
  272. .id = UCLASS_GPIO,
  273. .probe = gpio_stm32_probe,
  274. .ops = &gpio_stm32_ops,
  275. .flags = DM_UC_FLAG_SEQ_ALIAS,
  276. .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
  277. };