clk_stm32mp1.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <div64.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <regmap.h>
  12. #include <spl.h>
  13. #include <syscon.h>
  14. #include <time.h>
  15. #include <vsprintf.h>
  16. #include <linux/bitops.h>
  17. #include <linux/io.h>
  18. #include <linux/iopoll.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <dt-bindings/clock/stm32mp1-clks.h>
  21. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #ifndef CONFIG_TFABOOT
  24. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  25. /* activate clock tree initialization in the driver */
  26. #define STM32MP1_CLOCK_TREE_INIT
  27. #endif
  28. #endif
  29. #define MAX_HSI_HZ 64000000
  30. /* TIMEOUT */
  31. #define TIMEOUT_200MS 200000
  32. #define TIMEOUT_1S 1000000
  33. /* STGEN registers */
  34. #define STGENC_CNTCR 0x00
  35. #define STGENC_CNTSR 0x04
  36. #define STGENC_CNTCVL 0x08
  37. #define STGENC_CNTCVU 0x0C
  38. #define STGENC_CNTFID0 0x20
  39. #define STGENC_CNTCR_EN BIT(0)
  40. /* RCC registers */
  41. #define RCC_OCENSETR 0x0C
  42. #define RCC_OCENCLRR 0x10
  43. #define RCC_HSICFGR 0x18
  44. #define RCC_MPCKSELR 0x20
  45. #define RCC_ASSCKSELR 0x24
  46. #define RCC_RCK12SELR 0x28
  47. #define RCC_MPCKDIVR 0x2C
  48. #define RCC_AXIDIVR 0x30
  49. #define RCC_APB4DIVR 0x3C
  50. #define RCC_APB5DIVR 0x40
  51. #define RCC_RTCDIVR 0x44
  52. #define RCC_MSSCKSELR 0x48
  53. #define RCC_PLL1CR 0x80
  54. #define RCC_PLL1CFGR1 0x84
  55. #define RCC_PLL1CFGR2 0x88
  56. #define RCC_PLL1FRACR 0x8C
  57. #define RCC_PLL1CSGR 0x90
  58. #define RCC_PLL2CR 0x94
  59. #define RCC_PLL2CFGR1 0x98
  60. #define RCC_PLL2CFGR2 0x9C
  61. #define RCC_PLL2FRACR 0xA0
  62. #define RCC_PLL2CSGR 0xA4
  63. #define RCC_I2C46CKSELR 0xC0
  64. #define RCC_CPERCKSELR 0xD0
  65. #define RCC_STGENCKSELR 0xD4
  66. #define RCC_DDRITFCR 0xD8
  67. #define RCC_BDCR 0x140
  68. #define RCC_RDLSICR 0x144
  69. #define RCC_MP_APB4ENSETR 0x200
  70. #define RCC_MP_APB5ENSETR 0x208
  71. #define RCC_MP_AHB5ENSETR 0x210
  72. #define RCC_MP_AHB6ENSETR 0x218
  73. #define RCC_OCRDYR 0x808
  74. #define RCC_DBGCFGR 0x80C
  75. #define RCC_RCK3SELR 0x820
  76. #define RCC_RCK4SELR 0x824
  77. #define RCC_MCUDIVR 0x830
  78. #define RCC_APB1DIVR 0x834
  79. #define RCC_APB2DIVR 0x838
  80. #define RCC_APB3DIVR 0x83C
  81. #define RCC_PLL3CR 0x880
  82. #define RCC_PLL3CFGR1 0x884
  83. #define RCC_PLL3CFGR2 0x888
  84. #define RCC_PLL3FRACR 0x88C
  85. #define RCC_PLL3CSGR 0x890
  86. #define RCC_PLL4CR 0x894
  87. #define RCC_PLL4CFGR1 0x898
  88. #define RCC_PLL4CFGR2 0x89C
  89. #define RCC_PLL4FRACR 0x8A0
  90. #define RCC_PLL4CSGR 0x8A4
  91. #define RCC_I2C12CKSELR 0x8C0
  92. #define RCC_I2C35CKSELR 0x8C4
  93. #define RCC_SPI2S1CKSELR 0x8D8
  94. #define RCC_SPI45CKSELR 0x8E0
  95. #define RCC_UART6CKSELR 0x8E4
  96. #define RCC_UART24CKSELR 0x8E8
  97. #define RCC_UART35CKSELR 0x8EC
  98. #define RCC_UART78CKSELR 0x8F0
  99. #define RCC_SDMMC12CKSELR 0x8F4
  100. #define RCC_SDMMC3CKSELR 0x8F8
  101. #define RCC_ETHCKSELR 0x8FC
  102. #define RCC_QSPICKSELR 0x900
  103. #define RCC_FMCCKSELR 0x904
  104. #define RCC_USBCKSELR 0x91C
  105. #define RCC_DSICKSELR 0x924
  106. #define RCC_ADCCKSELR 0x928
  107. #define RCC_MP_APB1ENSETR 0xA00
  108. #define RCC_MP_APB2ENSETR 0XA08
  109. #define RCC_MP_APB3ENSETR 0xA10
  110. #define RCC_MP_AHB2ENSETR 0xA18
  111. #define RCC_MP_AHB3ENSETR 0xA20
  112. #define RCC_MP_AHB4ENSETR 0xA28
  113. /* used for most of SELR register */
  114. #define RCC_SELR_SRC_MASK GENMASK(2, 0)
  115. #define RCC_SELR_SRCRDY BIT(31)
  116. /* Values of RCC_MPCKSELR register */
  117. #define RCC_MPCKSELR_HSI 0
  118. #define RCC_MPCKSELR_HSE 1
  119. #define RCC_MPCKSELR_PLL 2
  120. #define RCC_MPCKSELR_PLL_MPUDIV 3
  121. /* Values of RCC_ASSCKSELR register */
  122. #define RCC_ASSCKSELR_HSI 0
  123. #define RCC_ASSCKSELR_HSE 1
  124. #define RCC_ASSCKSELR_PLL 2
  125. /* Values of RCC_MSSCKSELR register */
  126. #define RCC_MSSCKSELR_HSI 0
  127. #define RCC_MSSCKSELR_HSE 1
  128. #define RCC_MSSCKSELR_CSI 2
  129. #define RCC_MSSCKSELR_PLL 3
  130. /* Values of RCC_CPERCKSELR register */
  131. #define RCC_CPERCKSELR_HSI 0
  132. #define RCC_CPERCKSELR_CSI 1
  133. #define RCC_CPERCKSELR_HSE 2
  134. /* used for most of DIVR register : max div for RTC */
  135. #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
  136. #define RCC_DIVR_DIVRDY BIT(31)
  137. /* Masks for specific DIVR registers */
  138. #define RCC_APBXDIV_MASK GENMASK(2, 0)
  139. #define RCC_MPUDIV_MASK GENMASK(2, 0)
  140. #define RCC_AXIDIV_MASK GENMASK(2, 0)
  141. #define RCC_MCUDIV_MASK GENMASK(3, 0)
  142. /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
  143. #define RCC_MP_ENCLRR_OFFSET 4
  144. /* Fields of RCC_BDCR register */
  145. #define RCC_BDCR_LSEON BIT(0)
  146. #define RCC_BDCR_LSEBYP BIT(1)
  147. #define RCC_BDCR_LSERDY BIT(2)
  148. #define RCC_BDCR_DIGBYP BIT(3)
  149. #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
  150. #define RCC_BDCR_LSEDRV_SHIFT 4
  151. #define RCC_BDCR_LSECSSON BIT(8)
  152. #define RCC_BDCR_RTCCKEN BIT(20)
  153. #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
  154. #define RCC_BDCR_RTCSRC_SHIFT 16
  155. /* Fields of RCC_RDLSICR register */
  156. #define RCC_RDLSICR_LSION BIT(0)
  157. #define RCC_RDLSICR_LSIRDY BIT(1)
  158. /* used for ALL PLLNCR registers */
  159. #define RCC_PLLNCR_PLLON BIT(0)
  160. #define RCC_PLLNCR_PLLRDY BIT(1)
  161. #define RCC_PLLNCR_SSCG_CTRL BIT(2)
  162. #define RCC_PLLNCR_DIVPEN BIT(4)
  163. #define RCC_PLLNCR_DIVQEN BIT(5)
  164. #define RCC_PLLNCR_DIVREN BIT(6)
  165. #define RCC_PLLNCR_DIVEN_SHIFT 4
  166. /* used for ALL PLLNCFGR1 registers */
  167. #define RCC_PLLNCFGR1_DIVM_SHIFT 16
  168. #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
  169. #define RCC_PLLNCFGR1_DIVN_SHIFT 0
  170. #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
  171. /* only for PLL3 and PLL4 */
  172. #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
  173. #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
  174. /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
  175. #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
  176. #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
  177. #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
  178. #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
  179. #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
  180. #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
  181. #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
  182. #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
  183. /* used for ALL PLLNFRACR registers */
  184. #define RCC_PLLNFRACR_FRACV_SHIFT 3
  185. #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
  186. #define RCC_PLLNFRACR_FRACLE BIT(16)
  187. /* used for ALL PLLNCSGR registers */
  188. #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
  189. #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
  190. #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
  191. #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
  192. #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
  193. #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
  194. /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
  195. #define RCC_OCENR_HSION BIT(0)
  196. #define RCC_OCENR_CSION BIT(4)
  197. #define RCC_OCENR_DIGBYP BIT(7)
  198. #define RCC_OCENR_HSEON BIT(8)
  199. #define RCC_OCENR_HSEBYP BIT(10)
  200. #define RCC_OCENR_HSECSSON BIT(11)
  201. /* Fields of RCC_OCRDYR register */
  202. #define RCC_OCRDYR_HSIRDY BIT(0)
  203. #define RCC_OCRDYR_HSIDIVRDY BIT(2)
  204. #define RCC_OCRDYR_CSIRDY BIT(4)
  205. #define RCC_OCRDYR_HSERDY BIT(8)
  206. /* Fields of DDRITFCR register */
  207. #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
  208. #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
  209. #define RCC_DDRITFCR_DDRCKMOD_SSR 0
  210. /* Fields of RCC_HSICFGR register */
  211. #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
  212. /* used for MCO related operations */
  213. #define RCC_MCOCFG_MCOON BIT(12)
  214. #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
  215. #define RCC_MCOCFG_MCODIV_SHIFT 4
  216. #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
  217. enum stm32mp1_parent_id {
  218. /*
  219. * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
  220. * they are used as index in osc[] as entry point
  221. */
  222. _HSI,
  223. _HSE,
  224. _CSI,
  225. _LSI,
  226. _LSE,
  227. _I2S_CKIN,
  228. NB_OSC,
  229. /* other parent source */
  230. _HSI_KER = NB_OSC,
  231. _HSE_KER,
  232. _HSE_KER_DIV2,
  233. _CSI_KER,
  234. _PLL1_P,
  235. _PLL1_Q,
  236. _PLL1_R,
  237. _PLL2_P,
  238. _PLL2_Q,
  239. _PLL2_R,
  240. _PLL3_P,
  241. _PLL3_Q,
  242. _PLL3_R,
  243. _PLL4_P,
  244. _PLL4_Q,
  245. _PLL4_R,
  246. _ACLK,
  247. _PCLK1,
  248. _PCLK2,
  249. _PCLK3,
  250. _PCLK4,
  251. _PCLK5,
  252. _HCLK6,
  253. _HCLK2,
  254. _CK_PER,
  255. _CK_MPU,
  256. _CK_MCU,
  257. _DSI_PHY,
  258. _USB_PHY_48,
  259. _PARENT_NB,
  260. _UNKNOWN_ID = 0xff,
  261. };
  262. enum stm32mp1_parent_sel {
  263. _I2C12_SEL,
  264. _I2C35_SEL,
  265. _I2C46_SEL,
  266. _UART6_SEL,
  267. _UART24_SEL,
  268. _UART35_SEL,
  269. _UART78_SEL,
  270. _SDMMC12_SEL,
  271. _SDMMC3_SEL,
  272. _ETH_SEL,
  273. _QSPI_SEL,
  274. _FMC_SEL,
  275. _USBPHY_SEL,
  276. _USBO_SEL,
  277. _STGEN_SEL,
  278. _DSI_SEL,
  279. _ADC12_SEL,
  280. _SPI1_SEL,
  281. _SPI45_SEL,
  282. _RTC_SEL,
  283. _PARENT_SEL_NB,
  284. _UNKNOWN_SEL = 0xff,
  285. };
  286. enum stm32mp1_pll_id {
  287. _PLL1,
  288. _PLL2,
  289. _PLL3,
  290. _PLL4,
  291. _PLL_NB
  292. };
  293. enum stm32mp1_div_id {
  294. _DIV_P,
  295. _DIV_Q,
  296. _DIV_R,
  297. _DIV_NB,
  298. };
  299. enum stm32mp1_clksrc_id {
  300. CLKSRC_MPU,
  301. CLKSRC_AXI,
  302. CLKSRC_MCU,
  303. CLKSRC_PLL12,
  304. CLKSRC_PLL3,
  305. CLKSRC_PLL4,
  306. CLKSRC_RTC,
  307. CLKSRC_MCO1,
  308. CLKSRC_MCO2,
  309. CLKSRC_NB
  310. };
  311. enum stm32mp1_clkdiv_id {
  312. CLKDIV_MPU,
  313. CLKDIV_AXI,
  314. CLKDIV_MCU,
  315. CLKDIV_APB1,
  316. CLKDIV_APB2,
  317. CLKDIV_APB3,
  318. CLKDIV_APB4,
  319. CLKDIV_APB5,
  320. CLKDIV_RTC,
  321. CLKDIV_MCO1,
  322. CLKDIV_MCO2,
  323. CLKDIV_NB
  324. };
  325. enum stm32mp1_pllcfg {
  326. PLLCFG_M,
  327. PLLCFG_N,
  328. PLLCFG_P,
  329. PLLCFG_Q,
  330. PLLCFG_R,
  331. PLLCFG_O,
  332. PLLCFG_NB
  333. };
  334. enum stm32mp1_pllcsg {
  335. PLLCSG_MOD_PER,
  336. PLLCSG_INC_STEP,
  337. PLLCSG_SSCG_MODE,
  338. PLLCSG_NB
  339. };
  340. enum stm32mp1_plltype {
  341. PLL_800,
  342. PLL_1600,
  343. PLL_TYPE_NB
  344. };
  345. struct stm32mp1_pll {
  346. u8 refclk_min;
  347. u8 refclk_max;
  348. u8 divn_max;
  349. };
  350. struct stm32mp1_clk_gate {
  351. u16 offset;
  352. u8 bit;
  353. u8 index;
  354. u8 set_clr;
  355. u8 sel;
  356. u8 fixed;
  357. };
  358. struct stm32mp1_clk_sel {
  359. u16 offset;
  360. u8 src;
  361. u8 msk;
  362. u8 nb_parent;
  363. const u8 *parent;
  364. };
  365. #define REFCLK_SIZE 4
  366. struct stm32mp1_clk_pll {
  367. enum stm32mp1_plltype plltype;
  368. u16 rckxselr;
  369. u16 pllxcfgr1;
  370. u16 pllxcfgr2;
  371. u16 pllxfracr;
  372. u16 pllxcr;
  373. u16 pllxcsgr;
  374. u8 refclk[REFCLK_SIZE];
  375. };
  376. struct stm32mp1_clk_data {
  377. const struct stm32mp1_clk_gate *gate;
  378. const struct stm32mp1_clk_sel *sel;
  379. const struct stm32mp1_clk_pll *pll;
  380. const int nb_gate;
  381. };
  382. struct stm32mp1_clk_priv {
  383. fdt_addr_t base;
  384. const struct stm32mp1_clk_data *data;
  385. ulong osc[NB_OSC];
  386. struct udevice *osc_dev[NB_OSC];
  387. };
  388. #define STM32MP1_CLK(off, b, idx, s) \
  389. { \
  390. .offset = (off), \
  391. .bit = (b), \
  392. .index = (idx), \
  393. .set_clr = 0, \
  394. .sel = (s), \
  395. .fixed = _UNKNOWN_ID, \
  396. }
  397. #define STM32MP1_CLK_F(off, b, idx, f) \
  398. { \
  399. .offset = (off), \
  400. .bit = (b), \
  401. .index = (idx), \
  402. .set_clr = 0, \
  403. .sel = _UNKNOWN_SEL, \
  404. .fixed = (f), \
  405. }
  406. #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
  407. { \
  408. .offset = (off), \
  409. .bit = (b), \
  410. .index = (idx), \
  411. .set_clr = 1, \
  412. .sel = (s), \
  413. .fixed = _UNKNOWN_ID, \
  414. }
  415. #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
  416. { \
  417. .offset = (off), \
  418. .bit = (b), \
  419. .index = (idx), \
  420. .set_clr = 1, \
  421. .sel = _UNKNOWN_SEL, \
  422. .fixed = (f), \
  423. }
  424. #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
  425. [(idx)] = { \
  426. .offset = (off), \
  427. .src = (s), \
  428. .msk = (m), \
  429. .parent = (p), \
  430. .nb_parent = ARRAY_SIZE((p)) \
  431. }
  432. #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
  433. p1, p2, p3, p4) \
  434. [(idx)] = { \
  435. .plltype = (type), \
  436. .rckxselr = (off1), \
  437. .pllxcfgr1 = (off2), \
  438. .pllxcfgr2 = (off3), \
  439. .pllxfracr = (off4), \
  440. .pllxcr = (off5), \
  441. .pllxcsgr = (off6), \
  442. .refclk[0] = (p1), \
  443. .refclk[1] = (p2), \
  444. .refclk[2] = (p3), \
  445. .refclk[3] = (p4), \
  446. }
  447. static const u8 stm32mp1_clks[][2] = {
  448. {CK_PER, _CK_PER},
  449. {CK_MPU, _CK_MPU},
  450. {CK_AXI, _ACLK},
  451. {CK_MCU, _CK_MCU},
  452. {CK_HSE, _HSE},
  453. {CK_CSI, _CSI},
  454. {CK_LSI, _LSI},
  455. {CK_LSE, _LSE},
  456. {CK_HSI, _HSI},
  457. {CK_HSE_DIV2, _HSE_KER_DIV2},
  458. };
  459. static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
  460. STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
  461. STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
  462. STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
  463. STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
  464. STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
  465. STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
  466. STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
  467. STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
  468. STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
  469. STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
  470. STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
  471. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
  472. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
  473. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
  474. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
  475. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
  476. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
  477. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
  478. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
  479. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
  480. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
  481. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
  482. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
  483. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
  484. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
  485. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
  486. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
  487. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
  488. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
  489. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
  490. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
  491. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
  492. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
  493. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
  494. STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
  495. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
  496. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
  497. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
  498. STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
  499. STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
  500. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
  501. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
  502. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
  503. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
  504. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
  505. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
  506. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
  507. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
  508. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
  509. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
  510. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
  511. STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
  512. STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
  513. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
  514. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
  515. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
  516. STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
  517. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
  518. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
  519. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
  520. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
  521. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
  522. STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
  523. STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
  524. };
  525. static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  526. static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  527. static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
  528. static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
  529. _HSE_KER};
  530. static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  531. _HSE_KER};
  532. static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  533. _HSE_KER};
  534. static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  535. _HSE_KER};
  536. static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
  537. static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
  538. static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
  539. static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  540. static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  541. static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
  542. static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
  543. static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
  544. static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
  545. static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
  546. static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
  547. _PLL3_R};
  548. static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
  549. _HSE_KER};
  550. static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
  551. static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
  552. STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
  553. STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
  554. STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
  555. STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
  556. STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
  557. uart24_parents),
  558. STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
  559. uart35_parents),
  560. STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
  561. uart78_parents),
  562. STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
  563. sdmmc12_parents),
  564. STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
  565. sdmmc3_parents),
  566. STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
  567. STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
  568. STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
  569. STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
  570. STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
  571. STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
  572. STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
  573. STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
  574. STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
  575. STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
  576. STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
  577. (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
  578. rtc_parents),
  579. };
  580. #ifdef STM32MP1_CLOCK_TREE_INIT
  581. /* define characteristic of PLL according type */
  582. #define DIVM_MIN 0
  583. #define DIVM_MAX 63
  584. #define DIVN_MIN 24
  585. #define DIVP_MIN 0
  586. #define DIVP_MAX 127
  587. #define FRAC_MAX 8192
  588. #define PLL1600_VCO_MIN 800000000
  589. #define PLL1600_VCO_MAX 1600000000
  590. static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
  591. [PLL_800] = {
  592. .refclk_min = 4,
  593. .refclk_max = 16,
  594. .divn_max = 99,
  595. },
  596. [PLL_1600] = {
  597. .refclk_min = 8,
  598. .refclk_max = 16,
  599. .divn_max = 199,
  600. },
  601. };
  602. #endif /* STM32MP1_CLOCK_TREE_INIT */
  603. static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
  604. STM32MP1_CLK_PLL(_PLL1, PLL_1600,
  605. RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
  606. RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
  607. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  608. STM32MP1_CLK_PLL(_PLL2, PLL_1600,
  609. RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
  610. RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
  611. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  612. STM32MP1_CLK_PLL(_PLL3, PLL_800,
  613. RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
  614. RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
  615. _HSI, _HSE, _CSI, _UNKNOWN_ID),
  616. STM32MP1_CLK_PLL(_PLL4, PLL_800,
  617. RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
  618. RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
  619. _HSI, _HSE, _CSI, _I2S_CKIN),
  620. };
  621. /* Prescaler table lookups for clock computation */
  622. /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
  623. static const u8 stm32mp1_mcu_div[16] = {
  624. 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
  625. };
  626. /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
  627. #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
  628. #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
  629. static const u8 stm32mp1_mpu_apbx_div[8] = {
  630. 0, 1, 2, 3, 4, 4, 4, 4
  631. };
  632. /* div = /1 /2 /3 /4 */
  633. static const u8 stm32mp1_axi_div[8] = {
  634. 1, 2, 3, 4, 4, 4, 4, 4
  635. };
  636. static const __maybe_unused
  637. char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
  638. [_HSI] = "HSI",
  639. [_HSE] = "HSE",
  640. [_CSI] = "CSI",
  641. [_LSI] = "LSI",
  642. [_LSE] = "LSE",
  643. [_I2S_CKIN] = "I2S_CKIN",
  644. [_HSI_KER] = "HSI_KER",
  645. [_HSE_KER] = "HSE_KER",
  646. [_HSE_KER_DIV2] = "HSE_KER_DIV2",
  647. [_CSI_KER] = "CSI_KER",
  648. [_PLL1_P] = "PLL1_P",
  649. [_PLL1_Q] = "PLL1_Q",
  650. [_PLL1_R] = "PLL1_R",
  651. [_PLL2_P] = "PLL2_P",
  652. [_PLL2_Q] = "PLL2_Q",
  653. [_PLL2_R] = "PLL2_R",
  654. [_PLL3_P] = "PLL3_P",
  655. [_PLL3_Q] = "PLL3_Q",
  656. [_PLL3_R] = "PLL3_R",
  657. [_PLL4_P] = "PLL4_P",
  658. [_PLL4_Q] = "PLL4_Q",
  659. [_PLL4_R] = "PLL4_R",
  660. [_ACLK] = "ACLK",
  661. [_PCLK1] = "PCLK1",
  662. [_PCLK2] = "PCLK2",
  663. [_PCLK3] = "PCLK3",
  664. [_PCLK4] = "PCLK4",
  665. [_PCLK5] = "PCLK5",
  666. [_HCLK6] = "KCLK6",
  667. [_HCLK2] = "HCLK2",
  668. [_CK_PER] = "CK_PER",
  669. [_CK_MPU] = "CK_MPU",
  670. [_CK_MCU] = "CK_MCU",
  671. [_USB_PHY_48] = "USB_PHY_48",
  672. [_DSI_PHY] = "DSI_PHY_PLL",
  673. };
  674. static const __maybe_unused
  675. char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
  676. [_I2C12_SEL] = "I2C12",
  677. [_I2C35_SEL] = "I2C35",
  678. [_I2C46_SEL] = "I2C46",
  679. [_UART6_SEL] = "UART6",
  680. [_UART24_SEL] = "UART24",
  681. [_UART35_SEL] = "UART35",
  682. [_UART78_SEL] = "UART78",
  683. [_SDMMC12_SEL] = "SDMMC12",
  684. [_SDMMC3_SEL] = "SDMMC3",
  685. [_ETH_SEL] = "ETH",
  686. [_QSPI_SEL] = "QSPI",
  687. [_FMC_SEL] = "FMC",
  688. [_USBPHY_SEL] = "USBPHY",
  689. [_USBO_SEL] = "USBO",
  690. [_STGEN_SEL] = "STGEN",
  691. [_DSI_SEL] = "DSI",
  692. [_ADC12_SEL] = "ADC12",
  693. [_SPI1_SEL] = "SPI1",
  694. [_SPI45_SEL] = "SPI45",
  695. [_RTC_SEL] = "RTC",
  696. };
  697. static const struct stm32mp1_clk_data stm32mp1_data = {
  698. .gate = stm32mp1_clk_gate,
  699. .sel = stm32mp1_clk_sel,
  700. .pll = stm32mp1_clk_pll,
  701. .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
  702. };
  703. static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
  704. {
  705. if (idx >= NB_OSC) {
  706. debug("%s: clk id %d not found\n", __func__, idx);
  707. return 0;
  708. }
  709. return priv->osc[idx];
  710. }
  711. static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
  712. {
  713. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  714. int i, nb_clks = priv->data->nb_gate;
  715. for (i = 0; i < nb_clks; i++) {
  716. if (gate[i].index == id)
  717. break;
  718. }
  719. if (i == nb_clks) {
  720. printf("%s: clk id %d not found\n", __func__, (u32)id);
  721. return -EINVAL;
  722. }
  723. return i;
  724. }
  725. static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
  726. int i)
  727. {
  728. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  729. if (gate[i].sel > _PARENT_SEL_NB) {
  730. printf("%s: parents for clk id %d not found\n",
  731. __func__, i);
  732. return -EINVAL;
  733. }
  734. return gate[i].sel;
  735. }
  736. static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
  737. int i)
  738. {
  739. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  740. if (gate[i].fixed == _UNKNOWN_ID)
  741. return -ENOENT;
  742. return gate[i].fixed;
  743. }
  744. static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
  745. unsigned long id)
  746. {
  747. const struct stm32mp1_clk_sel *sel = priv->data->sel;
  748. int i;
  749. int s, p;
  750. unsigned int idx;
  751. for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
  752. if (stm32mp1_clks[idx][0] == id)
  753. return stm32mp1_clks[idx][1];
  754. i = stm32mp1_clk_get_id(priv, id);
  755. if (i < 0)
  756. return i;
  757. p = stm32mp1_clk_get_fixed_parent(priv, i);
  758. if (p >= 0 && p < _PARENT_NB)
  759. return p;
  760. s = stm32mp1_clk_get_sel(priv, i);
  761. if (s < 0)
  762. return s;
  763. p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
  764. if (p < sel[s].nb_parent) {
  765. #ifdef DEBUG
  766. debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
  767. stm32mp1_clk_parent_name[sel[s].parent[p]],
  768. stm32mp1_clk_parent_sel_name[s],
  769. (u32)id);
  770. #endif
  771. return sel[s].parent[p];
  772. }
  773. pr_err("%s: no parents defined for clk id %d\n",
  774. __func__, (u32)id);
  775. return -EINVAL;
  776. }
  777. static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
  778. int pll_id)
  779. {
  780. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  781. u32 selr;
  782. int src;
  783. ulong refclk;
  784. /* Get current refclk */
  785. selr = readl(priv->base + pll[pll_id].rckxselr);
  786. src = selr & RCC_SELR_SRC_MASK;
  787. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
  788. return refclk;
  789. }
  790. /*
  791. * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
  792. * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
  793. * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
  794. * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
  795. */
  796. static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
  797. int pll_id)
  798. {
  799. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  800. int divm, divn;
  801. ulong refclk, fvco;
  802. u32 cfgr1, fracr;
  803. cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
  804. fracr = readl(priv->base + pll[pll_id].pllxfracr);
  805. divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
  806. divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
  807. refclk = pll_get_fref_ck(priv, pll_id);
  808. /* with FRACV :
  809. * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
  810. * without FRACV
  811. * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
  812. */
  813. if (fracr & RCC_PLLNFRACR_FRACLE) {
  814. u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
  815. >> RCC_PLLNFRACR_FRACV_SHIFT;
  816. fvco = (ulong)lldiv((unsigned long long)refclk *
  817. (((divn + 1) << 13) + fracv),
  818. ((unsigned long long)(divm + 1)) << 13);
  819. } else {
  820. fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
  821. }
  822. return fvco;
  823. }
  824. static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
  825. int pll_id, int div_id)
  826. {
  827. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  828. int divy;
  829. ulong dfout;
  830. u32 cfgr2;
  831. if (div_id >= _DIV_NB)
  832. return 0;
  833. cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
  834. divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
  835. dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
  836. return dfout;
  837. }
  838. static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
  839. {
  840. u32 reg;
  841. ulong clock = 0;
  842. switch (p) {
  843. case _CK_MPU:
  844. /* MPU sub system */
  845. reg = readl(priv->base + RCC_MPCKSELR);
  846. switch (reg & RCC_SELR_SRC_MASK) {
  847. case RCC_MPCKSELR_HSI:
  848. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  849. break;
  850. case RCC_MPCKSELR_HSE:
  851. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  852. break;
  853. case RCC_MPCKSELR_PLL:
  854. case RCC_MPCKSELR_PLL_MPUDIV:
  855. clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
  856. if ((reg & RCC_SELR_SRC_MASK) ==
  857. RCC_MPCKSELR_PLL_MPUDIV) {
  858. reg = readl(priv->base + RCC_MPCKDIVR);
  859. clock >>= stm32mp1_mpu_div[reg &
  860. RCC_MPUDIV_MASK];
  861. }
  862. break;
  863. }
  864. break;
  865. /* AXI sub system */
  866. case _ACLK:
  867. case _HCLK2:
  868. case _HCLK6:
  869. case _PCLK4:
  870. case _PCLK5:
  871. reg = readl(priv->base + RCC_ASSCKSELR);
  872. switch (reg & RCC_SELR_SRC_MASK) {
  873. case RCC_ASSCKSELR_HSI:
  874. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  875. break;
  876. case RCC_ASSCKSELR_HSE:
  877. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  878. break;
  879. case RCC_ASSCKSELR_PLL:
  880. clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
  881. break;
  882. }
  883. /* System clock divider */
  884. reg = readl(priv->base + RCC_AXIDIVR);
  885. clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
  886. switch (p) {
  887. case _PCLK4:
  888. reg = readl(priv->base + RCC_APB4DIVR);
  889. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  890. break;
  891. case _PCLK5:
  892. reg = readl(priv->base + RCC_APB5DIVR);
  893. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  894. break;
  895. default:
  896. break;
  897. }
  898. break;
  899. /* MCU sub system */
  900. case _CK_MCU:
  901. case _PCLK1:
  902. case _PCLK2:
  903. case _PCLK3:
  904. reg = readl(priv->base + RCC_MSSCKSELR);
  905. switch (reg & RCC_SELR_SRC_MASK) {
  906. case RCC_MSSCKSELR_HSI:
  907. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  908. break;
  909. case RCC_MSSCKSELR_HSE:
  910. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  911. break;
  912. case RCC_MSSCKSELR_CSI:
  913. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  914. break;
  915. case RCC_MSSCKSELR_PLL:
  916. clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
  917. break;
  918. }
  919. /* MCU clock divider */
  920. reg = readl(priv->base + RCC_MCUDIVR);
  921. clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
  922. switch (p) {
  923. case _PCLK1:
  924. reg = readl(priv->base + RCC_APB1DIVR);
  925. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  926. break;
  927. case _PCLK2:
  928. reg = readl(priv->base + RCC_APB2DIVR);
  929. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  930. break;
  931. case _PCLK3:
  932. reg = readl(priv->base + RCC_APB3DIVR);
  933. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  934. break;
  935. case _CK_MCU:
  936. default:
  937. break;
  938. }
  939. break;
  940. case _CK_PER:
  941. reg = readl(priv->base + RCC_CPERCKSELR);
  942. switch (reg & RCC_SELR_SRC_MASK) {
  943. case RCC_CPERCKSELR_HSI:
  944. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  945. break;
  946. case RCC_CPERCKSELR_HSE:
  947. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  948. break;
  949. case RCC_CPERCKSELR_CSI:
  950. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  951. break;
  952. }
  953. break;
  954. case _HSI:
  955. case _HSI_KER:
  956. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  957. break;
  958. case _CSI:
  959. case _CSI_KER:
  960. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  961. break;
  962. case _HSE:
  963. case _HSE_KER:
  964. case _HSE_KER_DIV2:
  965. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  966. if (p == _HSE_KER_DIV2)
  967. clock >>= 1;
  968. break;
  969. case _LSI:
  970. clock = stm32mp1_clk_get_fixed(priv, _LSI);
  971. break;
  972. case _LSE:
  973. clock = stm32mp1_clk_get_fixed(priv, _LSE);
  974. break;
  975. /* PLL */
  976. case _PLL1_P:
  977. case _PLL1_Q:
  978. case _PLL1_R:
  979. clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
  980. break;
  981. case _PLL2_P:
  982. case _PLL2_Q:
  983. case _PLL2_R:
  984. clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
  985. break;
  986. case _PLL3_P:
  987. case _PLL3_Q:
  988. case _PLL3_R:
  989. clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
  990. break;
  991. case _PLL4_P:
  992. case _PLL4_Q:
  993. case _PLL4_R:
  994. clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
  995. break;
  996. /* other */
  997. case _USB_PHY_48:
  998. clock = 48000000;
  999. break;
  1000. case _DSI_PHY:
  1001. {
  1002. struct clk clk;
  1003. struct udevice *dev = NULL;
  1004. if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
  1005. &dev)) {
  1006. if (clk_request(dev, &clk)) {
  1007. pr_err("ck_dsi_phy request");
  1008. } else {
  1009. clk.id = 0;
  1010. clock = clk_get_rate(&clk);
  1011. }
  1012. }
  1013. break;
  1014. }
  1015. default:
  1016. break;
  1017. }
  1018. debug("%s(%d) clock = %lx : %ld kHz\n",
  1019. __func__, p, clock, clock / 1000);
  1020. return clock;
  1021. }
  1022. static int stm32mp1_clk_enable(struct clk *clk)
  1023. {
  1024. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1025. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  1026. int i = stm32mp1_clk_get_id(priv, clk->id);
  1027. if (i < 0)
  1028. return i;
  1029. if (gate[i].set_clr)
  1030. writel(BIT(gate[i].bit), priv->base + gate[i].offset);
  1031. else
  1032. setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  1033. debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
  1034. return 0;
  1035. }
  1036. static int stm32mp1_clk_disable(struct clk *clk)
  1037. {
  1038. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1039. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  1040. int i = stm32mp1_clk_get_id(priv, clk->id);
  1041. if (i < 0)
  1042. return i;
  1043. if (gate[i].set_clr)
  1044. writel(BIT(gate[i].bit),
  1045. priv->base + gate[i].offset
  1046. + RCC_MP_ENCLRR_OFFSET);
  1047. else
  1048. clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  1049. debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
  1050. return 0;
  1051. }
  1052. static ulong stm32mp1_clk_get_rate(struct clk *clk)
  1053. {
  1054. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1055. int p = stm32mp1_clk_get_parent(priv, clk->id);
  1056. ulong rate;
  1057. if (p < 0)
  1058. return 0;
  1059. rate = stm32mp1_clk_get(priv, p);
  1060. #ifdef DEBUG
  1061. debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
  1062. __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
  1063. #endif
  1064. return rate;
  1065. }
  1066. #ifdef STM32MP1_CLOCK_TREE_INIT
  1067. bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
  1068. {
  1069. unsigned int id;
  1070. switch (opp_id) {
  1071. case 1:
  1072. case 2:
  1073. id = opp_id;
  1074. break;
  1075. default:
  1076. id = 1; /* default value */
  1077. break;
  1078. }
  1079. switch (cpu_type) {
  1080. case CPU_STM32MP157Fxx:
  1081. case CPU_STM32MP157Dxx:
  1082. case CPU_STM32MP153Fxx:
  1083. case CPU_STM32MP153Dxx:
  1084. case CPU_STM32MP151Fxx:
  1085. case CPU_STM32MP151Dxx:
  1086. return true;
  1087. default:
  1088. return id == 1;
  1089. }
  1090. }
  1091. __weak void board_vddcore_init(u32 voltage_mv)
  1092. {
  1093. }
  1094. /*
  1095. * gets OPP parameters (frequency in KHz and voltage in mV) from
  1096. * an OPP table subnode. Platform HW support capabilities are also checked.
  1097. * Returns 0 on success and a negative FDT error code on failure.
  1098. */
  1099. static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
  1100. u32 *freq_khz, u32 *voltage_mv)
  1101. {
  1102. u32 opp_hw;
  1103. u64 read_freq_64;
  1104. u32 read_voltage_32;
  1105. *freq_khz = 0;
  1106. *voltage_mv = 0;
  1107. opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
  1108. if (opp_hw)
  1109. if (!stm32mp1_supports_opp(opp_hw, cpu_type))
  1110. return -FDT_ERR_BADVALUE;
  1111. read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
  1112. 1000ULL;
  1113. read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
  1114. 1000U;
  1115. if (!read_voltage_32 || !read_freq_64)
  1116. return -FDT_ERR_NOTFOUND;
  1117. /* Frequency value expressed in KHz must fit on 32 bits */
  1118. if (read_freq_64 > U32_MAX)
  1119. return -FDT_ERR_BADVALUE;
  1120. /* Millivolt value must fit on 16 bits */
  1121. if (read_voltage_32 > U16_MAX)
  1122. return -FDT_ERR_BADVALUE;
  1123. *freq_khz = (u32)read_freq_64;
  1124. *voltage_mv = read_voltage_32;
  1125. return 0;
  1126. }
  1127. /*
  1128. * parses OPP table in DT and finds the parameters for the
  1129. * highest frequency supported by the HW platform.
  1130. * Returns 0 on success and a negative FDT error code on failure.
  1131. */
  1132. int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
  1133. {
  1134. ofnode node, subnode;
  1135. int ret;
  1136. u32 freq = 0U, voltage = 0U;
  1137. u32 cpu_type = get_cpu_type();
  1138. node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
  1139. if (!ofnode_valid(node))
  1140. return -FDT_ERR_NOTFOUND;
  1141. ofnode_for_each_subnode(subnode, node) {
  1142. unsigned int read_freq;
  1143. unsigned int read_voltage;
  1144. ret = stm32mp1_get_opp(cpu_type, subnode,
  1145. &read_freq, &read_voltage);
  1146. if (ret)
  1147. continue;
  1148. if (read_freq > freq) {
  1149. freq = read_freq;
  1150. voltage = read_voltage;
  1151. }
  1152. }
  1153. if (!freq || !voltage)
  1154. return -FDT_ERR_NOTFOUND;
  1155. *freq_hz = (u64)1000U * freq;
  1156. board_vddcore_init(voltage);
  1157. return 0;
  1158. }
  1159. static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
  1160. u32 *pllcfg, u32 *fracv)
  1161. {
  1162. u32 post_divm;
  1163. u32 input_freq;
  1164. u64 output_freq;
  1165. u64 freq;
  1166. u64 vco;
  1167. u32 divm, divn, divp, frac;
  1168. int i, ret;
  1169. u32 diff;
  1170. u32 best_diff = U32_MAX;
  1171. /* PLL1 is 1600 */
  1172. const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
  1173. const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
  1174. const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
  1175. ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
  1176. if (ret) {
  1177. debug("PLL1 OPP configuration not found (%d).\n", ret);
  1178. return ret;
  1179. }
  1180. switch (clksrc) {
  1181. case CLK_PLL12_HSI:
  1182. input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
  1183. break;
  1184. case CLK_PLL12_HSE:
  1185. input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
  1186. break;
  1187. default:
  1188. return -EINTR;
  1189. }
  1190. /* Following parameters have always the same value */
  1191. pllcfg[PLLCFG_Q] = 0;
  1192. pllcfg[PLLCFG_R] = 0;
  1193. pllcfg[PLLCFG_O] = PQR(1, 0, 0);
  1194. for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
  1195. post_divm = (u32)(input_freq / (divm + 1));
  1196. if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
  1197. continue;
  1198. for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
  1199. freq = output_freq * (divm + 1) * (divp + 1);
  1200. divn = (u32)((freq / input_freq) - 1);
  1201. if (divn < DIVN_MIN || divn > DIVN_MAX)
  1202. continue;
  1203. frac = (u32)(((freq * FRAC_MAX) / input_freq) -
  1204. ((divn + 1) * FRAC_MAX));
  1205. /* 2 loops to refine the fractional part */
  1206. for (i = 2; i != 0; i--) {
  1207. if (frac > FRAC_MAX)
  1208. break;
  1209. vco = (post_divm * (divn + 1)) +
  1210. ((post_divm * (u64)frac) /
  1211. FRAC_MAX);
  1212. if (vco < (PLL1600_VCO_MIN / 2) ||
  1213. vco > (PLL1600_VCO_MAX / 2)) {
  1214. frac++;
  1215. continue;
  1216. }
  1217. freq = vco / (divp + 1);
  1218. if (output_freq < freq)
  1219. diff = (u32)(freq - output_freq);
  1220. else
  1221. diff = (u32)(output_freq - freq);
  1222. if (diff < best_diff) {
  1223. pllcfg[PLLCFG_M] = divm;
  1224. pllcfg[PLLCFG_N] = divn;
  1225. pllcfg[PLLCFG_P] = divp;
  1226. *fracv = frac;
  1227. if (diff == 0)
  1228. return 0;
  1229. best_diff = diff;
  1230. }
  1231. frac++;
  1232. }
  1233. }
  1234. }
  1235. if (best_diff == U32_MAX)
  1236. return -1;
  1237. return 0;
  1238. }
  1239. static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
  1240. u32 mask_on)
  1241. {
  1242. u32 address = rcc + offset;
  1243. if (enable)
  1244. setbits_le32(address, mask_on);
  1245. else
  1246. clrbits_le32(address, mask_on);
  1247. }
  1248. static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
  1249. {
  1250. writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
  1251. }
  1252. static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
  1253. u32 mask_rdy)
  1254. {
  1255. u32 mask_test = 0;
  1256. u32 address = rcc + offset;
  1257. u32 val;
  1258. int ret;
  1259. if (enable)
  1260. mask_test = mask_rdy;
  1261. ret = readl_poll_timeout(address, val,
  1262. (val & mask_rdy) == mask_test,
  1263. TIMEOUT_1S);
  1264. if (ret)
  1265. pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
  1266. mask_rdy, address, enable, readl(address));
  1267. return ret;
  1268. }
  1269. static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
  1270. u32 lsedrv)
  1271. {
  1272. u32 value;
  1273. if (digbyp)
  1274. setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
  1275. if (bypass || digbyp)
  1276. setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
  1277. /*
  1278. * warning: not recommended to switch directly from "high drive"
  1279. * to "medium low drive", and vice-versa.
  1280. */
  1281. value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
  1282. >> RCC_BDCR_LSEDRV_SHIFT;
  1283. while (value != lsedrv) {
  1284. if (value > lsedrv)
  1285. value--;
  1286. else
  1287. value++;
  1288. clrsetbits_le32(rcc + RCC_BDCR,
  1289. RCC_BDCR_LSEDRV_MASK,
  1290. value << RCC_BDCR_LSEDRV_SHIFT);
  1291. }
  1292. stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
  1293. }
  1294. static void stm32mp1_lse_wait(fdt_addr_t rcc)
  1295. {
  1296. stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
  1297. }
  1298. static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
  1299. {
  1300. stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
  1301. stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
  1302. }
  1303. static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
  1304. {
  1305. if (digbyp)
  1306. writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
  1307. if (bypass || digbyp)
  1308. writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
  1309. stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
  1310. stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
  1311. if (css)
  1312. writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
  1313. }
  1314. static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
  1315. {
  1316. stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
  1317. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
  1318. }
  1319. static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
  1320. {
  1321. stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
  1322. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
  1323. }
  1324. static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
  1325. {
  1326. u32 address = rcc + RCC_OCRDYR;
  1327. u32 val;
  1328. int ret;
  1329. clrsetbits_le32(rcc + RCC_HSICFGR,
  1330. RCC_HSICFGR_HSIDIV_MASK,
  1331. RCC_HSICFGR_HSIDIV_MASK & hsidiv);
  1332. ret = readl_poll_timeout(address, val,
  1333. val & RCC_OCRDYR_HSIDIVRDY,
  1334. TIMEOUT_200MS);
  1335. if (ret)
  1336. pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
  1337. address, readl(address));
  1338. return ret;
  1339. }
  1340. static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
  1341. {
  1342. u8 hsidiv;
  1343. u32 hsidivfreq = MAX_HSI_HZ;
  1344. for (hsidiv = 0; hsidiv < 4; hsidiv++,
  1345. hsidivfreq = hsidivfreq / 2)
  1346. if (hsidivfreq == hsifreq)
  1347. break;
  1348. if (hsidiv == 4) {
  1349. pr_err("clk-hsi frequency invalid");
  1350. return -1;
  1351. }
  1352. if (hsidiv > 0)
  1353. return stm32mp1_set_hsidiv(rcc, hsidiv);
  1354. return 0;
  1355. }
  1356. static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
  1357. {
  1358. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1359. clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
  1360. RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
  1361. RCC_PLLNCR_DIVREN,
  1362. RCC_PLLNCR_PLLON);
  1363. }
  1364. static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
  1365. {
  1366. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1367. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1368. u32 val;
  1369. int ret;
  1370. ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
  1371. TIMEOUT_200MS);
  1372. if (ret) {
  1373. pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
  1374. pll_id, pllxcr, readl(pllxcr));
  1375. return ret;
  1376. }
  1377. /* start the requested output */
  1378. setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
  1379. return 0;
  1380. }
  1381. static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
  1382. {
  1383. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1384. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1385. u32 val;
  1386. /* stop all output */
  1387. clrbits_le32(pllxcr,
  1388. RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
  1389. /* stop PLL */
  1390. clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
  1391. /* wait PLL stopped */
  1392. return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
  1393. TIMEOUT_200MS);
  1394. }
  1395. static void pll_config_output(struct stm32mp1_clk_priv *priv,
  1396. int pll_id, u32 *pllcfg)
  1397. {
  1398. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1399. fdt_addr_t rcc = priv->base;
  1400. u32 value;
  1401. value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
  1402. & RCC_PLLNCFGR2_DIVP_MASK;
  1403. value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
  1404. & RCC_PLLNCFGR2_DIVQ_MASK;
  1405. value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
  1406. & RCC_PLLNCFGR2_DIVR_MASK;
  1407. writel(value, rcc + pll[pll_id].pllxcfgr2);
  1408. }
  1409. static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
  1410. u32 *pllcfg, u32 fracv)
  1411. {
  1412. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1413. fdt_addr_t rcc = priv->base;
  1414. enum stm32mp1_plltype type = pll[pll_id].plltype;
  1415. int src;
  1416. ulong refclk;
  1417. u8 ifrge = 0;
  1418. u32 value;
  1419. src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
  1420. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
  1421. (pllcfg[PLLCFG_M] + 1);
  1422. if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
  1423. refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
  1424. debug("invalid refclk = %x\n", (u32)refclk);
  1425. return -EINVAL;
  1426. }
  1427. if (type == PLL_800 && refclk >= 8000000)
  1428. ifrge = 1;
  1429. value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
  1430. & RCC_PLLNCFGR1_DIVN_MASK;
  1431. value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
  1432. & RCC_PLLNCFGR1_DIVM_MASK;
  1433. value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
  1434. & RCC_PLLNCFGR1_IFRGE_MASK;
  1435. writel(value, rcc + pll[pll_id].pllxcfgr1);
  1436. /* fractional configuration: load sigma-delta modulator (SDM) */
  1437. /* Write into FRACV the new fractional value , and FRACLE to 0 */
  1438. writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
  1439. rcc + pll[pll_id].pllxfracr);
  1440. /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
  1441. setbits_le32(rcc + pll[pll_id].pllxfracr,
  1442. RCC_PLLNFRACR_FRACLE);
  1443. pll_config_output(priv, pll_id, pllcfg);
  1444. return 0;
  1445. }
  1446. static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
  1447. {
  1448. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1449. u32 pllxcsg;
  1450. pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
  1451. RCC_PLLNCSGR_MOD_PER_MASK) |
  1452. ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
  1453. RCC_PLLNCSGR_INC_STEP_MASK) |
  1454. ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
  1455. RCC_PLLNCSGR_SSCG_MODE_MASK);
  1456. writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
  1457. setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
  1458. }
  1459. static __maybe_unused int pll_set_rate(struct udevice *dev,
  1460. int pll_id,
  1461. int div_id,
  1462. unsigned long clk_rate)
  1463. {
  1464. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1465. unsigned int pllcfg[PLLCFG_NB];
  1466. ofnode plloff;
  1467. char name[12];
  1468. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1469. enum stm32mp1_plltype type = pll[pll_id].plltype;
  1470. int divm, divn, divy;
  1471. int ret;
  1472. ulong fck_ref;
  1473. u32 fracv;
  1474. u64 value;
  1475. if (div_id > _DIV_NB)
  1476. return -EINVAL;
  1477. sprintf(name, "st,pll@%d", pll_id);
  1478. plloff = dev_read_subnode(dev, name);
  1479. if (!ofnode_valid(plloff))
  1480. return -FDT_ERR_NOTFOUND;
  1481. ret = ofnode_read_u32_array(plloff, "cfg",
  1482. pllcfg, PLLCFG_NB);
  1483. if (ret < 0)
  1484. return -FDT_ERR_NOTFOUND;
  1485. fck_ref = pll_get_fref_ck(priv, pll_id);
  1486. divm = pllcfg[PLLCFG_M];
  1487. /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
  1488. divy = pllcfg[PLLCFG_P + div_id];
  1489. /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
  1490. * So same final result than PLL2 et 4
  1491. * with FRACV
  1492. * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
  1493. * / (DIVy + 1) * (DIVM + 1)
  1494. * value = (DIVN + 1) * 2^13 + FRACV / 2^13
  1495. * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
  1496. */
  1497. value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
  1498. value = lldiv(value, fck_ref);
  1499. divn = (value >> 13) - 1;
  1500. if (divn < DIVN_MIN ||
  1501. divn > stm32mp1_pll[type].divn_max) {
  1502. pr_err("divn invalid = %d", divn);
  1503. return -EINVAL;
  1504. }
  1505. fracv = value - ((divn + 1) << 13);
  1506. pllcfg[PLLCFG_N] = divn;
  1507. /* reconfigure PLL */
  1508. pll_stop(priv, pll_id);
  1509. pll_config(priv, pll_id, pllcfg, fracv);
  1510. pll_start(priv, pll_id);
  1511. pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
  1512. return 0;
  1513. }
  1514. static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
  1515. {
  1516. u32 address = priv->base + (clksrc >> 4);
  1517. u32 val;
  1518. int ret;
  1519. clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
  1520. ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
  1521. TIMEOUT_200MS);
  1522. if (ret)
  1523. pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
  1524. clksrc, address, readl(address));
  1525. return ret;
  1526. }
  1527. static void stgen_config(struct stm32mp1_clk_priv *priv)
  1528. {
  1529. int p;
  1530. u32 stgenc, cntfid0;
  1531. ulong rate;
  1532. stgenc = STM32_STGEN_BASE;
  1533. cntfid0 = readl(stgenc + STGENC_CNTFID0);
  1534. p = stm32mp1_clk_get_parent(priv, STGEN_K);
  1535. rate = stm32mp1_clk_get(priv, p);
  1536. if (cntfid0 != rate) {
  1537. u64 counter;
  1538. pr_debug("System Generic Counter (STGEN) update\n");
  1539. clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1540. counter = (u64)readl(stgenc + STGENC_CNTCVL);
  1541. counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
  1542. counter = lldiv(counter * (u64)rate, cntfid0);
  1543. writel((u32)counter, stgenc + STGENC_CNTCVL);
  1544. writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
  1545. writel(rate, stgenc + STGENC_CNTFID0);
  1546. setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1547. __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
  1548. /* need to update gd->arch.timer_rate_hz with new frequency */
  1549. timer_init();
  1550. }
  1551. }
  1552. static int set_clkdiv(unsigned int clkdiv, u32 address)
  1553. {
  1554. u32 val;
  1555. int ret;
  1556. clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
  1557. ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
  1558. TIMEOUT_200MS);
  1559. if (ret)
  1560. pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
  1561. clkdiv, address, readl(address));
  1562. return ret;
  1563. }
  1564. static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
  1565. u32 clksrc, u32 clkdiv)
  1566. {
  1567. u32 address = priv->base + (clksrc >> 4);
  1568. /*
  1569. * binding clksrc : bit15-4 offset
  1570. * bit3: disable
  1571. * bit2-0: MCOSEL[2:0]
  1572. */
  1573. if (clksrc & 0x8) {
  1574. clrbits_le32(address, RCC_MCOCFG_MCOON);
  1575. } else {
  1576. clrsetbits_le32(address,
  1577. RCC_MCOCFG_MCOSRC_MASK,
  1578. clksrc & RCC_MCOCFG_MCOSRC_MASK);
  1579. clrsetbits_le32(address,
  1580. RCC_MCOCFG_MCODIV_MASK,
  1581. clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
  1582. setbits_le32(address, RCC_MCOCFG_MCOON);
  1583. }
  1584. }
  1585. static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
  1586. unsigned int clksrc,
  1587. int lse_css)
  1588. {
  1589. u32 address = priv->base + RCC_BDCR;
  1590. if (readl(address) & RCC_BDCR_RTCCKEN)
  1591. goto skip_rtc;
  1592. if (clksrc == CLK_RTC_DISABLED)
  1593. goto skip_rtc;
  1594. clrsetbits_le32(address,
  1595. RCC_BDCR_RTCSRC_MASK,
  1596. clksrc << RCC_BDCR_RTCSRC_SHIFT);
  1597. setbits_le32(address, RCC_BDCR_RTCCKEN);
  1598. skip_rtc:
  1599. if (lse_css)
  1600. setbits_le32(address, RCC_BDCR_LSECSSON);
  1601. }
  1602. static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
  1603. {
  1604. u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
  1605. u32 value = pkcs & 0xF;
  1606. u32 mask = 0xF;
  1607. if (pkcs & BIT(31)) {
  1608. mask <<= 4;
  1609. value <<= 4;
  1610. }
  1611. clrsetbits_le32(address, mask, value);
  1612. }
  1613. static int stm32mp1_clktree(struct udevice *dev)
  1614. {
  1615. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1616. fdt_addr_t rcc = priv->base;
  1617. unsigned int clksrc[CLKSRC_NB];
  1618. unsigned int clkdiv[CLKDIV_NB];
  1619. unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
  1620. unsigned int pllfracv[_PLL_NB];
  1621. unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
  1622. bool pllcfg_valid[_PLL_NB];
  1623. bool pllcsg_set[_PLL_NB];
  1624. int ret;
  1625. int i, len;
  1626. int lse_css = 0;
  1627. const u32 *pkcs_cell;
  1628. /* check mandatory field */
  1629. ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
  1630. if (ret < 0) {
  1631. debug("field st,clksrc invalid: error %d\n", ret);
  1632. return -FDT_ERR_NOTFOUND;
  1633. }
  1634. ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
  1635. if (ret < 0) {
  1636. debug("field st,clkdiv invalid: error %d\n", ret);
  1637. return -FDT_ERR_NOTFOUND;
  1638. }
  1639. /* check mandatory field in each pll */
  1640. for (i = 0; i < _PLL_NB; i++) {
  1641. char name[12];
  1642. ofnode node;
  1643. sprintf(name, "st,pll@%d", i);
  1644. node = dev_read_subnode(dev, name);
  1645. pllcfg_valid[i] = ofnode_valid(node);
  1646. pllcsg_set[i] = false;
  1647. if (pllcfg_valid[i]) {
  1648. debug("DT for PLL %d @ %s\n", i, name);
  1649. ret = ofnode_read_u32_array(node, "cfg",
  1650. pllcfg[i], PLLCFG_NB);
  1651. if (ret < 0) {
  1652. debug("field cfg invalid: error %d\n", ret);
  1653. return -FDT_ERR_NOTFOUND;
  1654. }
  1655. pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
  1656. ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
  1657. PLLCSG_NB);
  1658. if (!ret) {
  1659. pllcsg_set[i] = true;
  1660. } else if (ret != -FDT_ERR_NOTFOUND) {
  1661. debug("invalid csg node for pll@%d res=%d\n",
  1662. i, ret);
  1663. return ret;
  1664. }
  1665. } else if (i == _PLL1) {
  1666. /* use OPP for PLL1 for A7 CPU */
  1667. debug("DT for PLL %d with OPP\n", i);
  1668. ret = stm32mp1_pll1_opp(priv,
  1669. clksrc[CLKSRC_PLL12],
  1670. pllcfg[i],
  1671. &pllfracv[i]);
  1672. if (ret) {
  1673. debug("PLL %d with OPP error = %d\n", i, ret);
  1674. return ret;
  1675. }
  1676. pllcfg_valid[i] = true;
  1677. }
  1678. }
  1679. debug("configuration MCO\n");
  1680. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
  1681. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
  1682. debug("switch ON osillator\n");
  1683. /*
  1684. * switch ON oscillator found in device-tree,
  1685. * HSI already ON after bootrom
  1686. */
  1687. if (priv->osc[_LSI])
  1688. stm32mp1_lsi_set(rcc, 1);
  1689. if (priv->osc[_LSE]) {
  1690. int bypass, digbyp;
  1691. u32 lsedrv;
  1692. struct udevice *dev = priv->osc_dev[_LSE];
  1693. bypass = dev_read_bool(dev, "st,bypass");
  1694. digbyp = dev_read_bool(dev, "st,digbypass");
  1695. lse_css = dev_read_bool(dev, "st,css");
  1696. lsedrv = dev_read_u32_default(dev, "st,drive",
  1697. LSEDRV_MEDIUM_HIGH);
  1698. stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
  1699. }
  1700. if (priv->osc[_HSE]) {
  1701. int bypass, digbyp, css;
  1702. struct udevice *dev = priv->osc_dev[_HSE];
  1703. bypass = dev_read_bool(dev, "st,bypass");
  1704. digbyp = dev_read_bool(dev, "st,digbypass");
  1705. css = dev_read_bool(dev, "st,css");
  1706. stm32mp1_hse_enable(rcc, bypass, digbyp, css);
  1707. }
  1708. /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
  1709. * => switch on CSI even if node is not present in device tree
  1710. */
  1711. stm32mp1_csi_set(rcc, 1);
  1712. /* come back to HSI */
  1713. debug("come back to HSI\n");
  1714. set_clksrc(priv, CLK_MPU_HSI);
  1715. set_clksrc(priv, CLK_AXI_HSI);
  1716. set_clksrc(priv, CLK_MCU_HSI);
  1717. debug("pll stop\n");
  1718. for (i = 0; i < _PLL_NB; i++)
  1719. pll_stop(priv, i);
  1720. /* configure HSIDIV */
  1721. debug("configure HSIDIV\n");
  1722. if (priv->osc[_HSI]) {
  1723. stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
  1724. stgen_config(priv);
  1725. }
  1726. /* select DIV */
  1727. debug("select DIV\n");
  1728. /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
  1729. writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
  1730. set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
  1731. set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
  1732. set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
  1733. set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
  1734. set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
  1735. set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
  1736. set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
  1737. /* no ready bit for RTC */
  1738. writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
  1739. /* configure PLLs source */
  1740. debug("configure PLLs source\n");
  1741. set_clksrc(priv, clksrc[CLKSRC_PLL12]);
  1742. set_clksrc(priv, clksrc[CLKSRC_PLL3]);
  1743. set_clksrc(priv, clksrc[CLKSRC_PLL4]);
  1744. /* configure and start PLLs */
  1745. debug("configure PLLs\n");
  1746. for (i = 0; i < _PLL_NB; i++) {
  1747. if (!pllcfg_valid[i])
  1748. continue;
  1749. debug("configure PLL %d\n", i);
  1750. pll_config(priv, i, pllcfg[i], pllfracv[i]);
  1751. if (pllcsg_set[i])
  1752. pll_csg(priv, i, pllcsg[i]);
  1753. pll_start(priv, i);
  1754. }
  1755. /* wait and start PLLs ouptut when ready */
  1756. for (i = 0; i < _PLL_NB; i++) {
  1757. if (!pllcfg_valid[i])
  1758. continue;
  1759. debug("output PLL %d\n", i);
  1760. pll_output(priv, i, pllcfg[i][PLLCFG_O]);
  1761. }
  1762. /* wait LSE ready before to use it */
  1763. if (priv->osc[_LSE])
  1764. stm32mp1_lse_wait(rcc);
  1765. /* configure with expected clock source */
  1766. debug("CLKSRC\n");
  1767. set_clksrc(priv, clksrc[CLKSRC_MPU]);
  1768. set_clksrc(priv, clksrc[CLKSRC_AXI]);
  1769. set_clksrc(priv, clksrc[CLKSRC_MCU]);
  1770. set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
  1771. /* configure PKCK */
  1772. debug("PKCK\n");
  1773. pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
  1774. if (pkcs_cell) {
  1775. bool ckper_disabled = false;
  1776. for (i = 0; i < len / sizeof(u32); i++) {
  1777. u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
  1778. if (pkcs == CLK_CKPER_DISABLED) {
  1779. ckper_disabled = true;
  1780. continue;
  1781. }
  1782. pkcs_config(priv, pkcs);
  1783. }
  1784. /* CKPER is source for some peripheral clock
  1785. * (FMC-NAND / QPSI-NOR) and switching source is allowed
  1786. * only if previous clock is still ON
  1787. * => deactivated CKPER only after switching clock
  1788. */
  1789. if (ckper_disabled)
  1790. pkcs_config(priv, CLK_CKPER_DISABLED);
  1791. }
  1792. /* STGEN clock source can change with CLK_STGEN_XXX */
  1793. stgen_config(priv);
  1794. debug("oscillator off\n");
  1795. /* switch OFF HSI if not found in device-tree */
  1796. if (!priv->osc[_HSI])
  1797. stm32mp1_hsi_set(rcc, 0);
  1798. /* Software Self-Refresh mode (SSR) during DDR initilialization */
  1799. clrsetbits_le32(priv->base + RCC_DDRITFCR,
  1800. RCC_DDRITFCR_DDRCKMOD_MASK,
  1801. RCC_DDRITFCR_DDRCKMOD_SSR <<
  1802. RCC_DDRITFCR_DDRCKMOD_SHIFT);
  1803. return 0;
  1804. }
  1805. #endif /* STM32MP1_CLOCK_TREE_INIT */
  1806. static int pll_set_output_rate(struct udevice *dev,
  1807. int pll_id,
  1808. int div_id,
  1809. unsigned long clk_rate)
  1810. {
  1811. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1812. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1813. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1814. int div;
  1815. ulong fvco;
  1816. if (div_id > _DIV_NB)
  1817. return -EINVAL;
  1818. fvco = pll_get_fvco(priv, pll_id);
  1819. if (fvco <= clk_rate)
  1820. div = 1;
  1821. else
  1822. div = DIV_ROUND_UP(fvco, clk_rate);
  1823. if (div > 128)
  1824. div = 128;
  1825. /* stop the requested output */
  1826. clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
  1827. /* change divider */
  1828. clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
  1829. RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
  1830. (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
  1831. /* start the requested output */
  1832. setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
  1833. return 0;
  1834. }
  1835. static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
  1836. {
  1837. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1838. int p;
  1839. switch (clk->id) {
  1840. #if defined(STM32MP1_CLOCK_TREE_INIT) && \
  1841. defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
  1842. case DDRPHYC:
  1843. break;
  1844. #endif
  1845. case LTDC_PX:
  1846. case DSI_PX:
  1847. break;
  1848. default:
  1849. pr_err("not supported");
  1850. return -EINVAL;
  1851. }
  1852. p = stm32mp1_clk_get_parent(priv, clk->id);
  1853. #ifdef DEBUG
  1854. debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
  1855. #endif
  1856. if (p < 0)
  1857. return -EINVAL;
  1858. switch (p) {
  1859. #if defined(STM32MP1_CLOCK_TREE_INIT) && \
  1860. defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
  1861. case _PLL2_R: /* DDRPHYC */
  1862. {
  1863. /* only for change DDR clock in interactive mode */
  1864. ulong result;
  1865. set_clksrc(priv, CLK_AXI_HSI);
  1866. result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
  1867. set_clksrc(priv, CLK_AXI_PLL2P);
  1868. return result;
  1869. }
  1870. #endif
  1871. case _PLL4_Q:
  1872. /* for LTDC_PX and DSI_PX case */
  1873. return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
  1874. }
  1875. return -EINVAL;
  1876. }
  1877. static void stm32mp1_osc_clk_init(const char *name,
  1878. struct stm32mp1_clk_priv *priv,
  1879. int index)
  1880. {
  1881. struct clk clk;
  1882. struct udevice *dev = NULL;
  1883. priv->osc[index] = 0;
  1884. clk.id = 0;
  1885. if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
  1886. if (clk_request(dev, &clk))
  1887. pr_err("%s request", name);
  1888. else
  1889. priv->osc[index] = clk_get_rate(&clk);
  1890. }
  1891. priv->osc_dev[index] = dev;
  1892. }
  1893. static void stm32mp1_osc_init(struct udevice *dev)
  1894. {
  1895. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1896. int i;
  1897. const char *name[NB_OSC] = {
  1898. [_LSI] = "clk-lsi",
  1899. [_LSE] = "clk-lse",
  1900. [_HSI] = "clk-hsi",
  1901. [_HSE] = "clk-hse",
  1902. [_CSI] = "clk-csi",
  1903. [_I2S_CKIN] = "i2s_ckin",
  1904. };
  1905. for (i = 0; i < NB_OSC; i++) {
  1906. stm32mp1_osc_clk_init(name[i], priv, i);
  1907. debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
  1908. }
  1909. }
  1910. static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
  1911. {
  1912. char buf[32];
  1913. int i, s, p;
  1914. printf("Clocks:\n");
  1915. for (i = 0; i < _PARENT_NB; i++) {
  1916. printf("- %s : %s MHz\n",
  1917. stm32mp1_clk_parent_name[i],
  1918. strmhz(buf, stm32mp1_clk_get(priv, i)));
  1919. }
  1920. printf("Source Clocks:\n");
  1921. for (i = 0; i < _PARENT_SEL_NB; i++) {
  1922. p = (readl(priv->base + priv->data->sel[i].offset) >>
  1923. priv->data->sel[i].src) & priv->data->sel[i].msk;
  1924. if (p < priv->data->sel[i].nb_parent) {
  1925. s = priv->data->sel[i].parent[p];
  1926. printf("- %s(%d) => parent %s(%d)\n",
  1927. stm32mp1_clk_parent_sel_name[i], i,
  1928. stm32mp1_clk_parent_name[s], s);
  1929. } else {
  1930. printf("- %s(%d) => parent index %d is invalid\n",
  1931. stm32mp1_clk_parent_sel_name[i], i, p);
  1932. }
  1933. }
  1934. }
  1935. #ifdef CONFIG_CMD_CLK
  1936. int soc_clk_dump(void)
  1937. {
  1938. struct udevice *dev;
  1939. struct stm32mp1_clk_priv *priv;
  1940. int ret;
  1941. ret = uclass_get_device_by_driver(UCLASS_CLK,
  1942. DM_GET_DRIVER(stm32mp1_clock),
  1943. &dev);
  1944. if (ret)
  1945. return ret;
  1946. priv = dev_get_priv(dev);
  1947. stm32mp1_clk_dump(priv);
  1948. return 0;
  1949. }
  1950. #endif
  1951. static int stm32mp1_clk_probe(struct udevice *dev)
  1952. {
  1953. int result = 0;
  1954. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1955. priv->base = dev_read_addr(dev->parent);
  1956. if (priv->base == FDT_ADDR_T_NONE)
  1957. return -EINVAL;
  1958. priv->data = (void *)&stm32mp1_data;
  1959. if (!priv->data->gate || !priv->data->sel ||
  1960. !priv->data->pll)
  1961. return -EINVAL;
  1962. stm32mp1_osc_init(dev);
  1963. #ifdef STM32MP1_CLOCK_TREE_INIT
  1964. /* clock tree init is done only one time, before relocation */
  1965. if (!(gd->flags & GD_FLG_RELOC))
  1966. result = stm32mp1_clktree(dev);
  1967. if (result)
  1968. printf("clock tree initialization failed (%d)\n", result);
  1969. #endif
  1970. #ifndef CONFIG_SPL_BUILD
  1971. #if defined(DEBUG)
  1972. /* display debug information for probe after relocation */
  1973. if (gd->flags & GD_FLG_RELOC)
  1974. stm32mp1_clk_dump(priv);
  1975. #endif
  1976. gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
  1977. gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
  1978. /* DDRPHYC father */
  1979. gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
  1980. #if defined(CONFIG_DISPLAY_CPUINFO)
  1981. if (gd->flags & GD_FLG_RELOC) {
  1982. char buf[32];
  1983. printf("Clocks:\n");
  1984. printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
  1985. printf("- MCU : %s MHz\n",
  1986. strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
  1987. printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
  1988. printf("- PER : %s MHz\n",
  1989. strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
  1990. printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
  1991. }
  1992. #endif /* CONFIG_DISPLAY_CPUINFO */
  1993. #endif
  1994. return result;
  1995. }
  1996. static const struct clk_ops stm32mp1_clk_ops = {
  1997. .enable = stm32mp1_clk_enable,
  1998. .disable = stm32mp1_clk_disable,
  1999. .get_rate = stm32mp1_clk_get_rate,
  2000. .set_rate = stm32mp1_clk_set_rate,
  2001. };
  2002. U_BOOT_DRIVER(stm32mp1_clock) = {
  2003. .name = "stm32mp1_clk",
  2004. .id = UCLASS_CLK,
  2005. .ops = &stm32mp1_clk_ops,
  2006. .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
  2007. .probe = stm32mp1_clk_probe,
  2008. };