stm32mp1.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <adc.h>
  7. #include <bootm.h>
  8. #include <clk.h>
  9. #include <config.h>
  10. #include <dm.h>
  11. #include <env.h>
  12. #include <env_internal.h>
  13. #include <fdt_support.h>
  14. #include <g_dnl.h>
  15. #include <generic-phy.h>
  16. #include <hang.h>
  17. #include <i2c.h>
  18. #include <init.h>
  19. #include <led.h>
  20. #include <log.h>
  21. #include <malloc.h>
  22. #include <misc.h>
  23. #include <mtd_node.h>
  24. #include <net.h>
  25. #include <netdev.h>
  26. #include <phy.h>
  27. #include <remoteproc.h>
  28. #include <reset.h>
  29. #include <syscon.h>
  30. #include <usb.h>
  31. #include <watchdog.h>
  32. #include <asm/io.h>
  33. #include <asm/gpio.h>
  34. #include <asm/arch/stm32.h>
  35. #include <asm/arch/sys_proto.h>
  36. #include <jffs2/load_kernel.h>
  37. #include <linux/bitops.h>
  38. #include <linux/delay.h>
  39. #include <linux/err.h>
  40. #include <linux/iopoll.h>
  41. #include <power/regulator.h>
  42. #include <usb/dwc2_udc.h>
  43. #include "../../st/common/stusb160x.h"
  44. /* SYSCFG registers */
  45. #define SYSCFG_BOOTR 0x00
  46. #define SYSCFG_PMCSETR 0x04
  47. #define SYSCFG_IOCTRLSETR 0x18
  48. #define SYSCFG_ICNR 0x1C
  49. #define SYSCFG_CMPCR 0x20
  50. #define SYSCFG_CMPENSETR 0x24
  51. #define SYSCFG_PMCCLRR 0x44
  52. #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
  53. #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
  54. #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
  55. #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
  56. #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
  57. #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
  58. #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
  59. #define SYSCFG_CMPCR_SW_CTRL BIT(1)
  60. #define SYSCFG_CMPCR_READY BIT(8)
  61. #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
  62. #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
  63. #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
  64. #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
  65. #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
  66. #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
  67. #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
  68. #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
  69. /*
  70. * Get a global data pointer
  71. */
  72. DECLARE_GLOBAL_DATA_PTR;
  73. #define USB_LOW_THRESHOLD_UV 200000
  74. #define USB_WARNING_LOW_THRESHOLD_UV 660000
  75. #define USB_START_LOW_THRESHOLD_UV 1230000
  76. #define USB_START_HIGH_THRESHOLD_UV 2150000
  77. int board_early_init_f(void)
  78. {
  79. /* nothing to do, only used in SPL */
  80. return 0;
  81. }
  82. int checkboard(void)
  83. {
  84. int ret;
  85. char *mode;
  86. u32 otp;
  87. struct udevice *dev;
  88. const char *fdt_compat;
  89. int fdt_compat_len;
  90. if (IS_ENABLED(CONFIG_TFABOOT))
  91. mode = "trusted";
  92. else
  93. mode = "basic";
  94. printf("Board: stm32mp1 in %s mode", mode);
  95. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  96. &fdt_compat_len);
  97. if (fdt_compat && fdt_compat_len)
  98. printf(" (%s)", fdt_compat);
  99. puts("\n");
  100. /* display the STMicroelectronics board identification */
  101. if (CONFIG_IS_ENABLED(CMD_STBOARD)) {
  102. ret = uclass_get_device_by_driver(UCLASS_MISC,
  103. DM_GET_DRIVER(stm32mp_bsec),
  104. &dev);
  105. if (!ret)
  106. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
  107. &otp, sizeof(otp));
  108. if (ret > 0 && otp)
  109. printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
  110. otp >> 16,
  111. (otp >> 12) & 0xF,
  112. (otp >> 4) & 0xF,
  113. ((otp >> 8) & 0xF) - 1 + 'A',
  114. otp & 0xF);
  115. }
  116. return 0;
  117. }
  118. static void board_key_check(void)
  119. {
  120. #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
  121. ofnode node;
  122. struct gpio_desc gpio;
  123. enum forced_boot_mode boot_mode = BOOT_NORMAL;
  124. node = ofnode_path("/config");
  125. if (!ofnode_valid(node)) {
  126. debug("%s: no /config node?\n", __func__);
  127. return;
  128. }
  129. #ifdef CONFIG_FASTBOOT
  130. if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
  131. &gpio, GPIOD_IS_IN)) {
  132. debug("%s: could not find a /config/st,fastboot-gpios\n",
  133. __func__);
  134. } else {
  135. if (dm_gpio_get_value(&gpio)) {
  136. puts("Fastboot key pressed, ");
  137. boot_mode = BOOT_FASTBOOT;
  138. }
  139. dm_gpio_free(NULL, &gpio);
  140. }
  141. #endif
  142. #ifdef CONFIG_CMD_STM32PROG
  143. if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
  144. &gpio, GPIOD_IS_IN)) {
  145. debug("%s: could not find a /config/st,stm32prog-gpios\n",
  146. __func__);
  147. } else {
  148. if (dm_gpio_get_value(&gpio)) {
  149. puts("STM32Programmer key pressed, ");
  150. boot_mode = BOOT_STM32PROG;
  151. }
  152. dm_gpio_free(NULL, &gpio);
  153. }
  154. #endif
  155. if (boot_mode != BOOT_NORMAL) {
  156. puts("entering download mode...\n");
  157. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  158. TAMP_BOOT_FORCED_MASK,
  159. boot_mode);
  160. }
  161. #endif
  162. }
  163. #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  164. #include <usb/dwc2_udc.h>
  165. int g_dnl_board_usb_cable_connected(void)
  166. {
  167. struct udevice *dwc2_udc_otg;
  168. int ret;
  169. /* if typec stusb160x is present, means DK1 or DK2 board */
  170. ret = stusb160x_cable_connected();
  171. if (ret >= 0)
  172. return ret;
  173. ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
  174. DM_GET_DRIVER(dwc2_udc_otg),
  175. &dwc2_udc_otg);
  176. if (!ret)
  177. debug("dwc2_udc_otg init failed\n");
  178. return dwc2_udc_B_session_valid(dwc2_udc_otg);
  179. }
  180. #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
  181. #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
  182. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  183. {
  184. if (!strcmp(name, "usb_dnl_dfu"))
  185. put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
  186. else if (!strcmp(name, "usb_dnl_fastboot"))
  187. put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
  188. &dev->idProduct);
  189. else
  190. put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
  191. return 0;
  192. }
  193. #endif /* CONFIG_USB_GADGET */
  194. static int get_led(struct udevice **dev, char *led_string)
  195. {
  196. char *led_name;
  197. int ret;
  198. led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
  199. if (!led_name) {
  200. pr_debug("%s: could not find %s config string\n",
  201. __func__, led_string);
  202. return -ENOENT;
  203. }
  204. ret = led_get_by_label(led_name, dev);
  205. if (ret) {
  206. debug("%s: get=%d\n", __func__, ret);
  207. return ret;
  208. }
  209. return 0;
  210. }
  211. static int setup_led(enum led_state_t cmd)
  212. {
  213. struct udevice *dev;
  214. int ret;
  215. if (!CONFIG_IS_ENABLED(LED))
  216. return 0;
  217. ret = get_led(&dev, "u-boot,boot-led");
  218. if (ret)
  219. return ret;
  220. ret = led_set_state(dev, cmd);
  221. return ret;
  222. }
  223. static void __maybe_unused led_error_blink(u32 nb_blink)
  224. {
  225. int ret;
  226. struct udevice *led;
  227. u32 i;
  228. if (!nb_blink)
  229. return;
  230. if (CONFIG_IS_ENABLED(LED)) {
  231. ret = get_led(&led, "u-boot,error-led");
  232. if (!ret) {
  233. /* make u-boot,error-led blinking */
  234. /* if U32_MAX and 125ms interval, for 17.02 years */
  235. for (i = 0; i < 2 * nb_blink; i++) {
  236. led_set_state(led, LEDST_TOGGLE);
  237. mdelay(125);
  238. WATCHDOG_RESET();
  239. }
  240. led_set_state(led, LEDST_ON);
  241. }
  242. }
  243. /* infinite: the boot process must be stopped */
  244. if (nb_blink == U32_MAX)
  245. hang();
  246. }
  247. #ifdef CONFIG_ADC
  248. static int board_check_usb_power(void)
  249. {
  250. struct ofnode_phandle_args adc_args;
  251. struct udevice *adc;
  252. ofnode node;
  253. unsigned int raw;
  254. int max_uV = 0;
  255. int min_uV = USB_START_HIGH_THRESHOLD_UV;
  256. int ret, uV, adc_count;
  257. u32 nb_blink;
  258. u8 i;
  259. node = ofnode_path("/config");
  260. if (!ofnode_valid(node)) {
  261. debug("%s: no /config node?\n", __func__);
  262. return -ENOENT;
  263. }
  264. /*
  265. * Retrieve the ADC channels devices and get measurement
  266. * for each of them
  267. */
  268. adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
  269. "#io-channel-cells");
  270. if (adc_count < 0) {
  271. if (adc_count == -ENOENT)
  272. return 0;
  273. pr_err("%s: can't find adc channel (%d)\n", __func__,
  274. adc_count);
  275. return adc_count;
  276. }
  277. for (i = 0; i < adc_count; i++) {
  278. if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
  279. "#io-channel-cells", 0, i,
  280. &adc_args)) {
  281. pr_debug("%s: can't find /config/st,adc_usb_pd\n",
  282. __func__);
  283. return 0;
  284. }
  285. ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
  286. &adc);
  287. if (ret) {
  288. pr_err("%s: Can't get adc device(%d)\n", __func__,
  289. ret);
  290. return ret;
  291. }
  292. ret = adc_channel_single_shot(adc->name, adc_args.args[0],
  293. &raw);
  294. if (ret) {
  295. pr_err("%s: single shot failed for %s[%d]!\n",
  296. __func__, adc->name, adc_args.args[0]);
  297. return ret;
  298. }
  299. /* Convert to uV */
  300. if (!adc_raw_to_uV(adc, raw, &uV)) {
  301. if (uV > max_uV)
  302. max_uV = uV;
  303. if (uV < min_uV)
  304. min_uV = uV;
  305. pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__,
  306. adc->name, adc_args.args[0], raw, uV);
  307. } else {
  308. pr_err("%s: Can't get uV value for %s[%d]\n",
  309. __func__, adc->name, adc_args.args[0]);
  310. }
  311. }
  312. /*
  313. * If highest value is inside 1.23 Volts and 2.10 Volts, that means
  314. * board is plugged on an USB-C 3A power supply and boot process can
  315. * continue.
  316. */
  317. if (max_uV > USB_START_LOW_THRESHOLD_UV &&
  318. max_uV <= USB_START_HIGH_THRESHOLD_UV &&
  319. min_uV <= USB_LOW_THRESHOLD_UV)
  320. return 0;
  321. pr_err("****************************************************\n");
  322. /*
  323. * If highest and lowest value are either both below
  324. * USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that
  325. * means USB TYPE-C is in unattached mode, this is an issue, make
  326. * u-boot,error-led blinking and stop boot process.
  327. */
  328. if ((max_uV > USB_LOW_THRESHOLD_UV &&
  329. min_uV > USB_LOW_THRESHOLD_UV) ||
  330. (max_uV <= USB_LOW_THRESHOLD_UV &&
  331. min_uV <= USB_LOW_THRESHOLD_UV)) {
  332. pr_err("* ERROR USB TYPE-C connection in unattached mode *\n");
  333. pr_err("* Check that USB TYPE-C cable is correctly plugged *\n");
  334. /* with 125ms interval, led will blink for 17.02 years ....*/
  335. nb_blink = U32_MAX;
  336. }
  337. if (max_uV > USB_LOW_THRESHOLD_UV &&
  338. max_uV <= USB_WARNING_LOW_THRESHOLD_UV &&
  339. min_uV <= USB_LOW_THRESHOLD_UV) {
  340. pr_err("* WARNING 500mA power supply detected *\n");
  341. nb_blink = 2;
  342. }
  343. if (max_uV > USB_WARNING_LOW_THRESHOLD_UV &&
  344. max_uV <= USB_START_LOW_THRESHOLD_UV &&
  345. min_uV <= USB_LOW_THRESHOLD_UV) {
  346. pr_err("* WARNING 1.5A power supply detected *\n");
  347. nb_blink = 3;
  348. }
  349. /*
  350. * If highest value is above 2.15 Volts that means that the USB TypeC
  351. * supplies more than 3 Amp, this is not compliant with TypeC specification
  352. */
  353. if (max_uV > USB_START_HIGH_THRESHOLD_UV) {
  354. pr_err("* USB TYPE-C charger not compliant with *\n");
  355. pr_err("* specification *\n");
  356. pr_err("****************************************************\n\n");
  357. /* with 125ms interval, led will blink for 17.02 years ....*/
  358. nb_blink = U32_MAX;
  359. } else {
  360. pr_err("* Current too low, use a 3A power supply! *\n");
  361. pr_err("****************************************************\n\n");
  362. }
  363. led_error_blink(nb_blink);
  364. return 0;
  365. }
  366. #endif /* CONFIG_ADC */
  367. static void sysconf_init(void)
  368. {
  369. #ifndef CONFIG_TFABOOT
  370. u8 *syscfg;
  371. #ifdef CONFIG_DM_REGULATOR
  372. struct udevice *pwr_dev;
  373. struct udevice *pwr_reg;
  374. struct udevice *dev;
  375. u32 otp = 0;
  376. #endif
  377. int ret;
  378. u32 bootr, val;
  379. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  380. /* interconnect update : select master using the port 1 */
  381. /* LTDC = AXI_M9 */
  382. /* GPU = AXI_M8 */
  383. /* today information is hardcoded in U-Boot */
  384. writel(BIT(9), syscfg + SYSCFG_ICNR);
  385. /* disable Pull-Down for boot pin connected to VDD */
  386. bootr = readl(syscfg + SYSCFG_BOOTR);
  387. bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
  388. bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
  389. writel(bootr, syscfg + SYSCFG_BOOTR);
  390. #ifdef CONFIG_DM_REGULATOR
  391. /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
  392. * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
  393. * The customer will have to disable this for low frequencies
  394. * or if AFMUX is selected but the function not used, typically for
  395. * TRACE. Otherwise, impact on power consumption.
  396. *
  397. * WARNING:
  398. * enabling High Speed mode while VDD>2.7V
  399. * with the OTP product_below_2v5 (OTP 18, BIT 13)
  400. * erroneously set to 1 can damage the IC!
  401. * => U-Boot set the register only if VDD < 2.7V (in DT)
  402. * but this value need to be consistent with board design
  403. */
  404. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  405. DM_GET_DRIVER(stm32mp_pwr_pmic),
  406. &pwr_dev);
  407. if (!ret) {
  408. ret = uclass_get_device_by_driver(UCLASS_MISC,
  409. DM_GET_DRIVER(stm32mp_bsec),
  410. &dev);
  411. if (ret) {
  412. pr_err("Can't find stm32mp_bsec driver\n");
  413. return;
  414. }
  415. ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
  416. if (ret > 0)
  417. otp = otp & BIT(13);
  418. /* get VDD = vdd-supply */
  419. ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
  420. &pwr_reg);
  421. /* check if VDD is Low Voltage */
  422. if (!ret) {
  423. if (regulator_get_value(pwr_reg) < 2700000) {
  424. writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
  425. SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
  426. SYSCFG_IOCTRLSETR_HSLVEN_ETH |
  427. SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
  428. SYSCFG_IOCTRLSETR_HSLVEN_SPI,
  429. syscfg + SYSCFG_IOCTRLSETR);
  430. if (!otp)
  431. pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
  432. } else {
  433. if (otp)
  434. pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
  435. }
  436. } else {
  437. debug("VDD unknown");
  438. }
  439. }
  440. #endif
  441. /* activate automatic I/O compensation
  442. * warning: need to ensure CSI enabled and ready in clock driver
  443. */
  444. writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
  445. /* poll until ready (1s timeout) */
  446. ret = readl_poll_timeout(syscfg + SYSCFG_CMPCR, val,
  447. val & SYSCFG_CMPCR_READY,
  448. 1000000);
  449. if (ret) {
  450. pr_err("SYSCFG: I/O compensation failed, timeout.\n");
  451. led_error_blink(10);
  452. }
  453. clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
  454. #endif
  455. }
  456. #ifdef CONFIG_DM_REGULATOR
  457. /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
  458. static int dk2_i2c1_fix(void)
  459. {
  460. ofnode node;
  461. struct gpio_desc hdmi, audio;
  462. int ret = 0;
  463. node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
  464. if (!ofnode_valid(node)) {
  465. pr_debug("%s: no hdmi-transmitter@39 ?\n", __func__);
  466. return -ENOENT;
  467. }
  468. if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
  469. &hdmi, GPIOD_IS_OUT)) {
  470. pr_debug("%s: could not find reset-gpios\n",
  471. __func__);
  472. return -ENOENT;
  473. }
  474. node = ofnode_path("/soc/i2c@40012000/cs42l51@4a");
  475. if (!ofnode_valid(node)) {
  476. pr_debug("%s: no cs42l51@4a ?\n", __func__);
  477. return -ENOENT;
  478. }
  479. if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
  480. &audio, GPIOD_IS_OUT)) {
  481. pr_debug("%s: could not find reset-gpios\n",
  482. __func__);
  483. return -ENOENT;
  484. }
  485. /* before power up, insure that HDMI and AUDIO IC is under reset */
  486. ret = dm_gpio_set_value(&hdmi, 1);
  487. if (ret) {
  488. pr_err("%s: can't set_value for hdmi_nrst gpio", __func__);
  489. goto error;
  490. }
  491. ret = dm_gpio_set_value(&audio, 1);
  492. if (ret) {
  493. pr_err("%s: can't set_value for audio_nrst gpio", __func__);
  494. goto error;
  495. }
  496. /* power-up audio IC */
  497. regulator_autoset_by_name("v1v8_audio", NULL);
  498. /* power-up HDMI IC */
  499. regulator_autoset_by_name("v1v2_hdmi", NULL);
  500. regulator_autoset_by_name("v3v3_hdmi", NULL);
  501. error:
  502. return ret;
  503. }
  504. static bool board_is_dk2(void)
  505. {
  506. if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
  507. of_machine_is_compatible("st,stm32mp157c-dk2"))
  508. return true;
  509. return false;
  510. }
  511. #endif
  512. static bool board_is_ev1(void)
  513. {
  514. if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
  515. (of_machine_is_compatible("st,stm32mp157a-ev1") ||
  516. of_machine_is_compatible("st,stm32mp157c-ev1") ||
  517. of_machine_is_compatible("st,stm32mp157d-ev1") ||
  518. of_machine_is_compatible("st,stm32mp157f-ev1")))
  519. return true;
  520. return false;
  521. }
  522. /* touchscreen driver: only used for pincontrol configuration */
  523. static const struct udevice_id goodix_ids[] = {
  524. { .compatible = "goodix,gt9147", },
  525. { }
  526. };
  527. U_BOOT_DRIVER(goodix) = {
  528. .name = "goodix",
  529. .id = UCLASS_NOP,
  530. .of_match = goodix_ids,
  531. };
  532. static void board_ev1_init(void)
  533. {
  534. struct udevice *dev;
  535. /* configure IRQ line on EV1 for touchscreen before LCD reset */
  536. uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(goodix), &dev);
  537. }
  538. /* board dependent setup after realloc */
  539. int board_init(void)
  540. {
  541. /* address of boot parameters */
  542. gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
  543. if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
  544. gpio_hog_probe_all();
  545. board_key_check();
  546. if (board_is_ev1())
  547. board_ev1_init();
  548. #ifdef CONFIG_DM_REGULATOR
  549. if (board_is_dk2())
  550. dk2_i2c1_fix();
  551. regulators_enable_boot_on(_DEBUG);
  552. #endif
  553. sysconf_init();
  554. if (CONFIG_IS_ENABLED(LED))
  555. led_default_state();
  556. setup_led(LEDST_ON);
  557. return 0;
  558. }
  559. int board_late_init(void)
  560. {
  561. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  562. const void *fdt_compat;
  563. int fdt_compat_len;
  564. int ret;
  565. u32 otp;
  566. struct udevice *dev;
  567. char buf[10];
  568. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  569. &fdt_compat_len);
  570. if (fdt_compat && fdt_compat_len) {
  571. if (strncmp(fdt_compat, "st,", 3) != 0) {
  572. env_set("board_name", fdt_compat);
  573. } else {
  574. char dtb_name[256];
  575. int buf_len = sizeof(dtb_name);
  576. env_set("board_name", fdt_compat + 3);
  577. strncpy(dtb_name, fdt_compat + 3, buf_len);
  578. buf_len -= strlen(fdt_compat + 3);
  579. strncat(dtb_name, ".dtb", buf_len);
  580. env_set("fdtfile", dtb_name);
  581. }
  582. }
  583. ret = uclass_get_device_by_driver(UCLASS_MISC,
  584. DM_GET_DRIVER(stm32mp_bsec),
  585. &dev);
  586. if (!ret)
  587. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
  588. &otp, sizeof(otp));
  589. if (!ret && otp) {
  590. snprintf(buf, sizeof(buf), "0x%04x", otp >> 16);
  591. env_set("board_id", buf);
  592. snprintf(buf, sizeof(buf), "0x%04x",
  593. ((otp >> 8) & 0xF) - 1 + 0xA);
  594. env_set("board_rev", buf);
  595. }
  596. #endif
  597. #ifdef CONFIG_ADC
  598. /* for DK1/DK2 boards */
  599. board_check_usb_power();
  600. #endif /* CONFIG_ADC */
  601. return 0;
  602. }
  603. void board_quiesce_devices(void)
  604. {
  605. setup_led(LEDST_OFF);
  606. }
  607. /* eth init function : weak called in eqos driver */
  608. int board_interface_eth_init(struct udevice *dev,
  609. phy_interface_t interface_type)
  610. {
  611. u8 *syscfg;
  612. u32 value;
  613. bool eth_clk_sel_reg = false;
  614. bool eth_ref_clk_sel_reg = false;
  615. /* Gigabit Ethernet 125MHz clock selection. */
  616. eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
  617. /* Ethernet 50Mhz RMII clock selection */
  618. eth_ref_clk_sel_reg =
  619. dev_read_bool(dev, "st,eth_ref_clk_sel");
  620. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  621. if (!syscfg)
  622. return -ENODEV;
  623. switch (interface_type) {
  624. case PHY_INTERFACE_MODE_MII:
  625. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  626. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  627. debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
  628. break;
  629. case PHY_INTERFACE_MODE_GMII:
  630. if (eth_clk_sel_reg)
  631. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  632. SYSCFG_PMCSETR_ETH_CLK_SEL;
  633. else
  634. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
  635. debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
  636. break;
  637. case PHY_INTERFACE_MODE_RMII:
  638. if (eth_ref_clk_sel_reg)
  639. value = SYSCFG_PMCSETR_ETH_SEL_RMII |
  640. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  641. else
  642. value = SYSCFG_PMCSETR_ETH_SEL_RMII;
  643. debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
  644. break;
  645. case PHY_INTERFACE_MODE_RGMII:
  646. case PHY_INTERFACE_MODE_RGMII_ID:
  647. case PHY_INTERFACE_MODE_RGMII_RXID:
  648. case PHY_INTERFACE_MODE_RGMII_TXID:
  649. if (eth_clk_sel_reg)
  650. value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
  651. SYSCFG_PMCSETR_ETH_CLK_SEL;
  652. else
  653. value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
  654. debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
  655. break;
  656. default:
  657. debug("%s: Do not manage %d interface\n",
  658. __func__, interface_type);
  659. /* Do not manage others interfaces */
  660. return -EINVAL;
  661. }
  662. /* clear and set ETH configuration bits */
  663. writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
  664. SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
  665. syscfg + SYSCFG_PMCCLRR);
  666. writel(value, syscfg + SYSCFG_PMCSETR);
  667. return 0;
  668. }
  669. enum env_location env_get_location(enum env_operation op, int prio)
  670. {
  671. u32 bootmode = get_bootmode();
  672. if (prio)
  673. return ENVL_UNKNOWN;
  674. switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
  675. #ifdef CONFIG_ENV_IS_IN_EXT4
  676. case BOOT_FLASH_SD:
  677. case BOOT_FLASH_EMMC:
  678. return ENVL_EXT4;
  679. #endif
  680. #ifdef CONFIG_ENV_IS_IN_UBI
  681. case BOOT_FLASH_NAND:
  682. case BOOT_FLASH_SPINAND:
  683. return ENVL_UBI;
  684. #endif
  685. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  686. case BOOT_FLASH_NOR:
  687. return ENVL_SPI_FLASH;
  688. #endif
  689. default:
  690. return ENVL_NOWHERE;
  691. }
  692. }
  693. #if defined(CONFIG_ENV_IS_IN_EXT4)
  694. const char *env_ext4_get_intf(void)
  695. {
  696. u32 bootmode = get_bootmode();
  697. switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
  698. case BOOT_FLASH_SD:
  699. case BOOT_FLASH_EMMC:
  700. return "mmc";
  701. default:
  702. return "";
  703. }
  704. }
  705. const char *env_ext4_get_dev_part(void)
  706. {
  707. static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"};
  708. u32 bootmode = get_bootmode();
  709. return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1];
  710. }
  711. #endif
  712. #if defined(CONFIG_OF_BOARD_SETUP)
  713. int ft_board_setup(void *blob, bd_t *bd)
  714. {
  715. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  716. struct node_info nodes[] = {
  717. { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, },
  718. { "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND},
  719. { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, },
  720. };
  721. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  722. #endif
  723. return 0;
  724. }
  725. #endif
  726. static void board_copro_image_process(ulong fw_image, size_t fw_size)
  727. {
  728. int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
  729. if (!rproc_is_initialized())
  730. if (rproc_init()) {
  731. printf("Remote Processor %d initialization failed\n",
  732. id);
  733. return;
  734. }
  735. ret = rproc_load(id, fw_image, fw_size);
  736. printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
  737. id, fw_image, fw_size, ret ? " Failed!" : " Success!");
  738. if (!ret)
  739. rproc_start(id);
  740. }
  741. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);