cpu.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <debug_uart.h>
  9. #include <env.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <misc.h>
  13. #include <net.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/bsec.h>
  16. #include <asm/arch/stm32.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <dm/device.h>
  19. #include <dm/uclass.h>
  20. #include <linux/bitops.h>
  21. /* RCC register */
  22. #define RCC_TZCR (STM32_RCC_BASE + 0x00)
  23. #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
  24. #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
  25. #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
  26. #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
  27. #define RCC_BDCR_VSWRST BIT(31)
  28. #define RCC_BDCR_RTCSRC GENMASK(17, 16)
  29. #define RCC_DBGCFGR_DBGCKEN BIT(8)
  30. /* Security register */
  31. #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
  32. #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
  33. #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
  34. #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
  35. #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
  36. #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
  37. #define PWR_CR1 (STM32_PWR_BASE + 0x00)
  38. #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
  39. #define PWR_CR1_DBP BIT(8)
  40. #define PWR_MCUCR_SBF BIT(6)
  41. /* DBGMCU register */
  42. #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
  43. #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
  44. #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
  45. #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
  46. #define DBGMCU_IDC_DEV_ID_SHIFT 0
  47. #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
  48. #define DBGMCU_IDC_REV_ID_SHIFT 16
  49. /* GPIOZ registers */
  50. #define GPIOZ_SECCFGR 0x54004030
  51. /* boot interface from Bootrom
  52. * - boot instance = bit 31:16
  53. * - boot device = bit 15:0
  54. */
  55. #define BOOTROM_PARAM_ADDR 0x2FFC0078
  56. #define BOOTROM_MODE_MASK GENMASK(15, 0)
  57. #define BOOTROM_MODE_SHIFT 0
  58. #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
  59. #define BOOTROM_INSTANCE_SHIFT 16
  60. /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
  61. #define RPN_SHIFT 0
  62. #define RPN_MASK GENMASK(7, 0)
  63. /* Package = bit 27:29 of OTP16
  64. * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
  65. * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
  66. * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
  67. * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
  68. * - others: Reserved
  69. */
  70. #define PKG_SHIFT 27
  71. #define PKG_MASK GENMASK(2, 0)
  72. /*
  73. * early TLB into the .data section so that it not get cleared
  74. * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
  75. */
  76. u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
  77. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  78. #ifndef CONFIG_TFABOOT
  79. static void security_init(void)
  80. {
  81. /* Disable the backup domain write protection */
  82. /* the protection is enable at each reset by hardware */
  83. /* And must be disable by software */
  84. setbits_le32(PWR_CR1, PWR_CR1_DBP);
  85. while (!(readl(PWR_CR1) & PWR_CR1_DBP))
  86. ;
  87. /* If RTC clock isn't enable so this is a cold boot then we need
  88. * to reset the backup domain
  89. */
  90. if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
  91. setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  92. while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
  93. ;
  94. clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  95. }
  96. /* allow non secure access in Write/Read for all peripheral */
  97. writel(GENMASK(25, 0), ETZPC_DECPROT0);
  98. /* Open SYSRAM for no secure access */
  99. writel(0x0, ETZPC_TZMA1_SIZE);
  100. /* enable TZC1 TZC2 clock */
  101. writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
  102. /* Region 0 set to no access by default */
  103. /* bit 0 / 16 => nsaid0 read/write Enable
  104. * bit 1 / 17 => nsaid1 read/write Enable
  105. * ...
  106. * bit 15 / 31 => nsaid15 read/write Enable
  107. */
  108. writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
  109. /* bit 30 / 31 => Secure Global Enable : write/read */
  110. /* bit 0 / 1 => Region Enable for filter 0/1 */
  111. writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
  112. /* Enable Filter 0 and 1 */
  113. setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
  114. /* RCC trust zone deactivated */
  115. writel(0x0, RCC_TZCR);
  116. /* TAMP: deactivate the internal tamper
  117. * Bit 23 ITAMP8E: monotonic counter overflow
  118. * Bit 20 ITAMP5E: RTC calendar overflow
  119. * Bit 19 ITAMP4E: HSE monitoring
  120. * Bit 18 ITAMP3E: LSE monitoring
  121. * Bit 16 ITAMP1E: RTC power domain supply monitoring
  122. */
  123. writel(0x0, TAMP_CR1);
  124. /* GPIOZ: deactivate the security */
  125. writel(BIT(0), RCC_MP_AHB5ENSETR);
  126. writel(0x0, GPIOZ_SECCFGR);
  127. }
  128. #endif /* CONFIG_TFABOOT */
  129. /*
  130. * Debug init
  131. */
  132. static void dbgmcu_init(void)
  133. {
  134. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  135. /*
  136. * Freeze IWDG2 if Cortex-A7 is in debug mode
  137. * done in TF-A for TRUSTED boot and
  138. * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
  139. */
  140. if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable())
  141. setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
  142. }
  143. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  144. #if !defined(CONFIG_TFABOOT) && \
  145. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  146. /* get bootmode from ROM code boot context: saved in TAMP register */
  147. static void update_bootmode(void)
  148. {
  149. u32 boot_mode;
  150. u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
  151. u32 bootrom_device, bootrom_instance;
  152. /* enable TAMP clock = RTCAPBEN */
  153. writel(BIT(8), RCC_MP_APB5ENSETR);
  154. /* read bootrom context */
  155. bootrom_device =
  156. (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
  157. bootrom_instance =
  158. (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
  159. boot_mode =
  160. ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
  161. ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
  162. BOOT_INSTANCE_MASK);
  163. /* save the boot mode in TAMP backup register */
  164. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  165. TAMP_BOOT_MODE_MASK,
  166. boot_mode << TAMP_BOOT_MODE_SHIFT);
  167. }
  168. #endif
  169. u32 get_bootmode(void)
  170. {
  171. /* read bootmode from TAMP backup register */
  172. return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
  173. TAMP_BOOT_MODE_SHIFT;
  174. }
  175. /*
  176. * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
  177. * MMU/TLB is updated in enable_caches() for U-Boot after relocation
  178. * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
  179. */
  180. static void early_enable_caches(void)
  181. {
  182. /* I-cache is already enabled in start.S: cpu_init_cp15 */
  183. if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  184. return;
  185. gd->arch.tlb_size = PGTABLE_SIZE;
  186. gd->arch.tlb_addr = (unsigned long)&early_tlb;
  187. dcache_enable();
  188. if (IS_ENABLED(CONFIG_SPL_BUILD))
  189. mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
  190. STM32_SYSRAM_SIZE,
  191. DCACHE_DEFAULT_OPTION);
  192. else
  193. mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
  194. DCACHE_DEFAULT_OPTION);
  195. }
  196. /*
  197. * Early system init
  198. */
  199. int arch_cpu_init(void)
  200. {
  201. u32 boot_mode;
  202. early_enable_caches();
  203. /* early armv7 timer init: needed for polling */
  204. timer_init();
  205. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  206. dbgmcu_init();
  207. #ifndef CONFIG_TFABOOT
  208. security_init();
  209. update_bootmode();
  210. #endif
  211. /* Reset Coprocessor state unless it wakes up from Standby power mode */
  212. if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
  213. writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
  214. writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
  215. }
  216. #endif
  217. boot_mode = get_bootmode();
  218. if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
  219. gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
  220. #if defined(CONFIG_DEBUG_UART) && \
  221. !defined(CONFIG_TFABOOT) && \
  222. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  223. else
  224. debug_uart_init();
  225. #endif
  226. return 0;
  227. }
  228. void enable_caches(void)
  229. {
  230. /* I-cache is already enabled in start.S: icache_enable() not needed */
  231. /* deactivate the data cache, early enabled in arch_cpu_init() */
  232. dcache_disable();
  233. /*
  234. * update MMU after relocation and enable the data cache
  235. * warning: the TLB location udpated in board_f.c::reserve_mmu
  236. */
  237. dcache_enable();
  238. }
  239. static u32 read_idc(void)
  240. {
  241. /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
  242. if (bsec_dbgswenable()) {
  243. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  244. return readl(DBGMCU_IDC);
  245. }
  246. if (CONFIG_IS_ENABLED(STM32MP15x))
  247. return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
  248. else
  249. return 0x0;
  250. }
  251. u32 get_cpu_dev(void)
  252. {
  253. return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
  254. }
  255. u32 get_cpu_rev(void)
  256. {
  257. return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
  258. }
  259. static u32 get_otp(int index, int shift, int mask)
  260. {
  261. int ret;
  262. struct udevice *dev;
  263. u32 otp = 0;
  264. ret = uclass_get_device_by_driver(UCLASS_MISC,
  265. DM_GET_DRIVER(stm32mp_bsec),
  266. &dev);
  267. if (!ret)
  268. ret = misc_read(dev, STM32_BSEC_SHADOW(index),
  269. &otp, sizeof(otp));
  270. return (otp >> shift) & mask;
  271. }
  272. /* Get Device Part Number (RPN) from OTP */
  273. static u32 get_cpu_rpn(void)
  274. {
  275. return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
  276. }
  277. u32 get_cpu_type(void)
  278. {
  279. return (get_cpu_dev() << 16) | get_cpu_rpn();
  280. }
  281. /* Get Package options from OTP */
  282. u32 get_cpu_package(void)
  283. {
  284. return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
  285. }
  286. void get_soc_name(char name[SOC_NAME_SIZE])
  287. {
  288. char *cpu_s, *cpu_r, *pkg;
  289. /* MPUs Part Numbers */
  290. switch (get_cpu_type()) {
  291. case CPU_STM32MP157Fxx:
  292. cpu_s = "157F";
  293. break;
  294. case CPU_STM32MP157Dxx:
  295. cpu_s = "157D";
  296. break;
  297. case CPU_STM32MP157Cxx:
  298. cpu_s = "157C";
  299. break;
  300. case CPU_STM32MP157Axx:
  301. cpu_s = "157A";
  302. break;
  303. case CPU_STM32MP153Fxx:
  304. cpu_s = "153F";
  305. break;
  306. case CPU_STM32MP153Dxx:
  307. cpu_s = "153D";
  308. break;
  309. case CPU_STM32MP153Cxx:
  310. cpu_s = "153C";
  311. break;
  312. case CPU_STM32MP153Axx:
  313. cpu_s = "153A";
  314. break;
  315. case CPU_STM32MP151Fxx:
  316. cpu_s = "151F";
  317. break;
  318. case CPU_STM32MP151Dxx:
  319. cpu_s = "151D";
  320. break;
  321. case CPU_STM32MP151Cxx:
  322. cpu_s = "151C";
  323. break;
  324. case CPU_STM32MP151Axx:
  325. cpu_s = "151A";
  326. break;
  327. default:
  328. cpu_s = "????";
  329. break;
  330. }
  331. /* Package */
  332. switch (get_cpu_package()) {
  333. case PKG_AA_LBGA448:
  334. pkg = "AA";
  335. break;
  336. case PKG_AB_LBGA354:
  337. pkg = "AB";
  338. break;
  339. case PKG_AC_TFBGA361:
  340. pkg = "AC";
  341. break;
  342. case PKG_AD_TFBGA257:
  343. pkg = "AD";
  344. break;
  345. default:
  346. pkg = "??";
  347. break;
  348. }
  349. /* REVISION */
  350. switch (get_cpu_rev()) {
  351. case CPU_REVA:
  352. cpu_r = "A";
  353. break;
  354. case CPU_REVB:
  355. cpu_r = "B";
  356. break;
  357. case CPU_REVZ:
  358. cpu_r = "Z";
  359. break;
  360. default:
  361. cpu_r = "?";
  362. break;
  363. }
  364. snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
  365. }
  366. #if defined(CONFIG_DISPLAY_CPUINFO)
  367. int print_cpuinfo(void)
  368. {
  369. char name[SOC_NAME_SIZE];
  370. get_soc_name(name);
  371. printf("CPU: %s\n", name);
  372. return 0;
  373. }
  374. #endif /* CONFIG_DISPLAY_CPUINFO */
  375. static void setup_boot_mode(void)
  376. {
  377. const u32 serial_addr[] = {
  378. STM32_USART1_BASE,
  379. STM32_USART2_BASE,
  380. STM32_USART3_BASE,
  381. STM32_UART4_BASE,
  382. STM32_UART5_BASE,
  383. STM32_USART6_BASE,
  384. STM32_UART7_BASE,
  385. STM32_UART8_BASE
  386. };
  387. char cmd[60];
  388. u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
  389. u32 boot_mode =
  390. (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
  391. unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
  392. u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
  393. struct udevice *dev;
  394. int alias;
  395. pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
  396. __func__, boot_ctx, boot_mode, instance, forced_mode);
  397. switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
  398. case BOOT_SERIAL_UART:
  399. if (instance > ARRAY_SIZE(serial_addr))
  400. break;
  401. /* serial : search associated alias in devicetree */
  402. sprintf(cmd, "serial@%x", serial_addr[instance]);
  403. if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
  404. break;
  405. if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
  406. dev_of_offset(dev), &alias))
  407. break;
  408. sprintf(cmd, "%d", alias);
  409. env_set("boot_device", "serial");
  410. env_set("boot_instance", cmd);
  411. /* restore console on uart when not used */
  412. if (gd->cur_serial_dev != dev) {
  413. gd->flags &= ~(GD_FLG_SILENT |
  414. GD_FLG_DISABLE_CONSOLE);
  415. printf("serial boot with console enabled!\n");
  416. }
  417. break;
  418. case BOOT_SERIAL_USB:
  419. env_set("boot_device", "usb");
  420. env_set("boot_instance", "0");
  421. break;
  422. case BOOT_FLASH_SD:
  423. case BOOT_FLASH_EMMC:
  424. sprintf(cmd, "%d", instance);
  425. env_set("boot_device", "mmc");
  426. env_set("boot_instance", cmd);
  427. break;
  428. case BOOT_FLASH_NAND:
  429. env_set("boot_device", "nand");
  430. env_set("boot_instance", "0");
  431. break;
  432. case BOOT_FLASH_SPINAND:
  433. env_set("boot_device", "spi-nand");
  434. env_set("boot_instance", "0");
  435. break;
  436. case BOOT_FLASH_NOR:
  437. env_set("boot_device", "nor");
  438. env_set("boot_instance", "0");
  439. break;
  440. default:
  441. pr_debug("unexpected boot mode = %x\n", boot_mode);
  442. break;
  443. }
  444. switch (forced_mode) {
  445. case BOOT_FASTBOOT:
  446. printf("Enter fastboot!\n");
  447. env_set("preboot", "env set preboot; fastboot 0");
  448. break;
  449. case BOOT_STM32PROG:
  450. env_set("boot_device", "usb");
  451. env_set("boot_instance", "0");
  452. break;
  453. case BOOT_UMS_MMC0:
  454. case BOOT_UMS_MMC1:
  455. case BOOT_UMS_MMC2:
  456. printf("Enter UMS!\n");
  457. instance = forced_mode - BOOT_UMS_MMC0;
  458. sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
  459. env_set("preboot", cmd);
  460. break;
  461. case BOOT_RECOVERY:
  462. env_set("preboot", "env set preboot; run altbootcmd");
  463. break;
  464. case BOOT_NORMAL:
  465. break;
  466. default:
  467. pr_debug("unexpected forced boot mode = %x\n", forced_mode);
  468. break;
  469. }
  470. /* clear TAMP for next reboot */
  471. clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
  472. }
  473. /*
  474. * If there is no MAC address in the environment, then it will be initialized
  475. * (silently) from the value in the OTP.
  476. */
  477. __weak int setup_mac_address(void)
  478. {
  479. #if defined(CONFIG_NET)
  480. int ret;
  481. int i;
  482. u32 otp[2];
  483. uchar enetaddr[6];
  484. struct udevice *dev;
  485. /* MAC already in environment */
  486. if (eth_env_get_enetaddr("ethaddr", enetaddr))
  487. return 0;
  488. ret = uclass_get_device_by_driver(UCLASS_MISC,
  489. DM_GET_DRIVER(stm32mp_bsec),
  490. &dev);
  491. if (ret)
  492. return ret;
  493. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
  494. otp, sizeof(otp));
  495. if (ret < 0)
  496. return ret;
  497. for (i = 0; i < 6; i++)
  498. enetaddr[i] = ((uint8_t *)&otp)[i];
  499. if (!is_valid_ethaddr(enetaddr)) {
  500. pr_err("invalid MAC address in OTP %pM\n", enetaddr);
  501. return -EINVAL;
  502. }
  503. pr_debug("OTP MAC address = %pM\n", enetaddr);
  504. ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
  505. if (!ret)
  506. pr_err("Failed to set mac address %pM from OTP: %d\n",
  507. enetaddr, ret);
  508. #endif
  509. return 0;
  510. }
  511. static int setup_serial_number(void)
  512. {
  513. char serial_string[25];
  514. u32 otp[3] = {0, 0, 0 };
  515. struct udevice *dev;
  516. int ret;
  517. if (env_get("serial#"))
  518. return 0;
  519. ret = uclass_get_device_by_driver(UCLASS_MISC,
  520. DM_GET_DRIVER(stm32mp_bsec),
  521. &dev);
  522. if (ret)
  523. return ret;
  524. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
  525. otp, sizeof(otp));
  526. if (ret < 0)
  527. return ret;
  528. sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
  529. env_set("serial#", serial_string);
  530. return 0;
  531. }
  532. int arch_misc_init(void)
  533. {
  534. setup_boot_mode();
  535. setup_mac_address();
  536. setup_serial_number();
  537. return 0;
  538. }