stm32mp15xx-dhcom-u-boot.dtsi 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019 Marek Vasut <marex@denx.de>
  4. */
  5. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  6. #include "stm32mp15-u-boot.dtsi"
  7. #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  8. #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  9. #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  10. / {
  11. aliases {
  12. i2c1 = &i2c2;
  13. i2c3 = &i2c4;
  14. i2c4 = &i2c5;
  15. mmc0 = &sdmmc1;
  16. mmc1 = &sdmmc2;
  17. spi0 = &qspi;
  18. usb0 = &usbotg_hs;
  19. };
  20. config {
  21. u-boot,boot-led = "heartbeat";
  22. u-boot,error-led = "error";
  23. st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  24. st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  25. dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
  26. dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
  27. };
  28. led {
  29. red {
  30. label = "error";
  31. gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  32. default-state = "off";
  33. status = "okay";
  34. };
  35. blue {
  36. default-state = "on";
  37. };
  38. };
  39. /* This is actually on FMC2, but we do not have bus driver for that */
  40. ksz8851: ks8851mll@64000000 {
  41. compatible = "micrel,ks8851-mll";
  42. reg = <0x64000000 0x20000>;
  43. };
  44. };
  45. &gpiof {
  46. snor-nwp {
  47. gpio-hog;
  48. gpios = <7 0>;
  49. output-high;
  50. line-name = "spi-nor-nwp";
  51. };
  52. };
  53. &i2c4 {
  54. u-boot,dm-pre-reloc;
  55. };
  56. &i2c4_pins_a {
  57. u-boot,dm-pre-reloc;
  58. pins {
  59. u-boot,dm-pre-reloc;
  60. };
  61. };
  62. &pinctrl {
  63. /* These should bound to FMC2 bus driver, but we do not have one */
  64. pinctrl-0 = <&fmc_pins_b>;
  65. pinctrl-1 = <&fmc_sleep_pins_b>;
  66. pinctrl-names = "default", "sleep";
  67. fmc_pins_b: fmc-0 {
  68. pins1 {
  69. pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
  70. <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
  71. <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
  72. <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
  73. <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
  74. <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
  75. <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
  76. <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
  77. <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
  78. <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
  79. <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
  80. <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
  81. <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
  82. <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
  83. <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
  84. <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
  85. <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
  86. <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
  87. <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
  88. <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
  89. <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
  90. bias-disable;
  91. drive-push-pull;
  92. slew-rate = <3>;
  93. };
  94. };
  95. fmc_sleep_pins_b: fmc-sleep-0 {
  96. pins {
  97. pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
  98. <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
  99. <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
  100. <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
  101. <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
  102. <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
  103. <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
  104. <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
  105. <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
  106. <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
  107. <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
  108. <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
  109. <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
  110. <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
  111. <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
  112. <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
  113. <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
  114. <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
  115. <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
  116. <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
  117. <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
  118. };
  119. };
  120. };
  121. &pmic {
  122. u-boot,dm-pre-reloc;
  123. };
  124. &flash0 {
  125. u-boot,dm-spl;
  126. };
  127. &qspi {
  128. u-boot,dm-spl;
  129. };
  130. &qspi_clk_pins_a {
  131. u-boot,dm-spl;
  132. pins {
  133. u-boot,dm-spl;
  134. };
  135. };
  136. &qspi_bk1_pins_a {
  137. u-boot,dm-spl;
  138. pins1 {
  139. u-boot,dm-spl;
  140. };
  141. pins2 {
  142. u-boot,dm-spl;
  143. };
  144. };
  145. &qspi_bk2_pins_a {
  146. u-boot,dm-spl;
  147. pins1 {
  148. u-boot,dm-spl;
  149. };
  150. pins2 {
  151. u-boot,dm-spl;
  152. };
  153. };
  154. &rcc {
  155. st,clksrc = <
  156. CLK_MPU_PLL1P
  157. CLK_AXI_PLL2P
  158. CLK_MCU_PLL3P
  159. CLK_PLL12_HSE
  160. CLK_PLL3_HSE
  161. CLK_PLL4_HSE
  162. CLK_RTC_LSE
  163. CLK_MCO1_DISABLED
  164. CLK_MCO2_DISABLED
  165. >;
  166. st,clkdiv = <
  167. 1 /*MPU*/
  168. 0 /*AXI*/
  169. 0 /*MCU*/
  170. 1 /*APB1*/
  171. 1 /*APB2*/
  172. 1 /*APB3*/
  173. 1 /*APB4*/
  174. 2 /*APB5*/
  175. 23 /*RTC*/
  176. 0 /*MCO1*/
  177. 0 /*MCO2*/
  178. >;
  179. st,pkcs = <
  180. CLK_CKPER_HSE
  181. CLK_FMC_ACLK
  182. CLK_QSPI_ACLK
  183. CLK_ETH_PLL4P
  184. CLK_SDMMC12_PLL4P
  185. CLK_DSI_DSIPLL
  186. CLK_STGEN_HSE
  187. CLK_USBPHY_HSE
  188. CLK_SPI2S1_PLL3Q
  189. CLK_SPI2S23_PLL3Q
  190. CLK_SPI45_HSI
  191. CLK_SPI6_HSI
  192. CLK_I2C46_HSI
  193. CLK_SDMMC3_PLL4P
  194. CLK_USBO_USBPHY
  195. CLK_ADC_CKPER
  196. CLK_CEC_LSE
  197. CLK_I2C12_HSI
  198. CLK_I2C35_HSI
  199. CLK_UART1_HSI
  200. CLK_UART24_HSI
  201. CLK_UART35_HSI
  202. CLK_UART6_HSI
  203. CLK_UART78_HSI
  204. CLK_SPDIF_PLL4P
  205. CLK_FDCAN_PLL4R
  206. CLK_SAI1_PLL3Q
  207. CLK_SAI2_PLL3Q
  208. CLK_SAI3_PLL3Q
  209. CLK_SAI4_PLL3Q
  210. CLK_RNG1_LSI
  211. CLK_RNG2_LSI
  212. CLK_LPTIM1_PCLK1
  213. CLK_LPTIM23_PCLK3
  214. CLK_LPTIM45_LSE
  215. >;
  216. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  217. pll2: st,pll@1 {
  218. compatible = "st,stm32mp1-pll";
  219. reg = <1>;
  220. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  221. frac = < 0x1400 >;
  222. u-boot,dm-pre-reloc;
  223. };
  224. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  225. pll3: st,pll@2 {
  226. compatible = "st,stm32mp1-pll";
  227. reg = <2>;
  228. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  229. frac = < 0x1a04 >;
  230. u-boot,dm-pre-reloc;
  231. };
  232. /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
  233. pll4: st,pll@3 {
  234. compatible = "st,stm32mp1-pll";
  235. reg = <3>;
  236. cfg = < 1 49 11 11 11 PQR(1,1,1) >;
  237. u-boot,dm-pre-reloc;
  238. };
  239. };
  240. &sdmmc1 {
  241. u-boot,dm-spl;
  242. broken-cd;
  243. /delete-property/ cd-gpios;
  244. /delete-property/ disable-wp;
  245. };
  246. &sdmmc1_b4_pins_a {
  247. u-boot,dm-spl;
  248. pins1 {
  249. u-boot,dm-spl;
  250. };
  251. pins2 {
  252. u-boot,dm-spl;
  253. };
  254. };
  255. &sdmmc1_dir_pins_a {
  256. u-boot,dm-spl;
  257. pins1 {
  258. u-boot,dm-spl;
  259. };
  260. pins2 {
  261. u-boot,dm-spl;
  262. };
  263. };
  264. &sdmmc2 {
  265. u-boot,dm-spl;
  266. };
  267. &sdmmc2_b4_pins_a {
  268. u-boot,dm-spl;
  269. pins {
  270. u-boot,dm-spl;
  271. };
  272. };
  273. &sdmmc2_d47_pins_a {
  274. u-boot,dm-spl;
  275. pins {
  276. u-boot,dm-spl;
  277. };
  278. };
  279. &uart4 {
  280. u-boot,dm-pre-reloc;
  281. };
  282. &uart4_pins_a {
  283. u-boot,dm-pre-reloc;
  284. pins1 {
  285. u-boot,dm-pre-reloc;
  286. };
  287. pins2 {
  288. u-boot,dm-pre-reloc;
  289. /* pull-up on rx to avoid floating level */
  290. bias-pull-up;
  291. };
  292. };