stm32mp157c-ed1-u-boot.dtsi 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  6. #include "stm32mp15-u-boot.dtsi"
  7. #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  8. / {
  9. aliases {
  10. i2c3 = &i2c4;
  11. mmc0 = &sdmmc1;
  12. mmc1 = &sdmmc2;
  13. };
  14. config {
  15. u-boot,boot-led = "heartbeat";
  16. u-boot,error-led = "error";
  17. st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  18. st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  19. };
  20. firmware {
  21. optee {
  22. compatible = "linaro,optee-tz";
  23. method = "smc";
  24. };
  25. };
  26. reserved-memory {
  27. optee@fe000000 {
  28. reg = <0xfe000000 0x02000000>;
  29. no-map;
  30. };
  31. };
  32. led {
  33. red {
  34. label = "error";
  35. gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  36. default-state = "off";
  37. status = "okay";
  38. };
  39. };
  40. };
  41. &clk_hse {
  42. st,digbypass;
  43. };
  44. &i2c4 {
  45. u-boot,dm-pre-reloc;
  46. };
  47. &i2c4_pins_a {
  48. u-boot,dm-pre-reloc;
  49. pins {
  50. u-boot,dm-pre-reloc;
  51. };
  52. };
  53. &pmic {
  54. u-boot,dm-pre-reloc;
  55. };
  56. &rcc {
  57. st,clksrc = <
  58. CLK_MPU_PLL1P
  59. CLK_AXI_PLL2P
  60. CLK_MCU_PLL3P
  61. CLK_PLL12_HSE
  62. CLK_PLL3_HSE
  63. CLK_PLL4_HSE
  64. CLK_RTC_LSE
  65. CLK_MCO1_DISABLED
  66. CLK_MCO2_DISABLED
  67. >;
  68. st,clkdiv = <
  69. 1 /*MPU*/
  70. 0 /*AXI*/
  71. 0 /*MCU*/
  72. 1 /*APB1*/
  73. 1 /*APB2*/
  74. 1 /*APB3*/
  75. 1 /*APB4*/
  76. 2 /*APB5*/
  77. 23 /*RTC*/
  78. 0 /*MCO1*/
  79. 0 /*MCO2*/
  80. >;
  81. st,pkcs = <
  82. CLK_CKPER_HSE
  83. CLK_FMC_ACLK
  84. CLK_QSPI_ACLK
  85. CLK_ETH_DISABLED
  86. CLK_SDMMC12_PLL4P
  87. CLK_DSI_DSIPLL
  88. CLK_STGEN_HSE
  89. CLK_USBPHY_HSE
  90. CLK_SPI2S1_PLL3Q
  91. CLK_SPI2S23_PLL3Q
  92. CLK_SPI45_HSI
  93. CLK_SPI6_HSI
  94. CLK_I2C46_HSI
  95. CLK_SDMMC3_PLL4P
  96. CLK_USBO_USBPHY
  97. CLK_ADC_CKPER
  98. CLK_CEC_LSE
  99. CLK_I2C12_HSI
  100. CLK_I2C35_HSI
  101. CLK_UART1_HSI
  102. CLK_UART24_HSI
  103. CLK_UART35_HSI
  104. CLK_UART6_HSI
  105. CLK_UART78_HSI
  106. CLK_SPDIF_PLL4P
  107. CLK_FDCAN_PLL4R
  108. CLK_SAI1_PLL3Q
  109. CLK_SAI2_PLL3Q
  110. CLK_SAI3_PLL3Q
  111. CLK_SAI4_PLL3Q
  112. CLK_RNG1_LSI
  113. CLK_RNG2_LSI
  114. CLK_LPTIM1_PCLK1
  115. CLK_LPTIM23_PCLK3
  116. CLK_LPTIM45_LSE
  117. >;
  118. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  119. pll2: st,pll@1 {
  120. compatible = "st,stm32mp1-pll";
  121. reg = <1>;
  122. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  123. frac = < 0x1400 >;
  124. u-boot,dm-pre-reloc;
  125. };
  126. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  127. pll3: st,pll@2 {
  128. compatible = "st,stm32mp1-pll";
  129. reg = <2>;
  130. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  131. frac = < 0x1a04 >;
  132. u-boot,dm-pre-reloc;
  133. };
  134. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  135. pll4: st,pll@3 {
  136. compatible = "st,stm32mp1-pll";
  137. reg = <3>;
  138. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  139. u-boot,dm-pre-reloc;
  140. };
  141. };
  142. &sdmmc1 {
  143. u-boot,dm-spl;
  144. broken-cd;
  145. /delete-property/ cd-gpios;
  146. };
  147. &sdmmc1_b4_pins_a {
  148. u-boot,dm-spl;
  149. pins1 {
  150. u-boot,dm-spl;
  151. };
  152. pins2 {
  153. u-boot,dm-spl;
  154. };
  155. };
  156. &sdmmc1_dir_pins_a {
  157. u-boot,dm-spl;
  158. pins1 {
  159. u-boot,dm-spl;
  160. };
  161. pins2 {
  162. u-boot,dm-spl;
  163. };
  164. };
  165. &sdmmc2 {
  166. u-boot,dm-spl;
  167. };
  168. &sdmmc2_b4_pins_a {
  169. u-boot,dm-spl;
  170. pins1 {
  171. u-boot,dm-spl;
  172. };
  173. pins2 {
  174. u-boot,dm-spl;
  175. };
  176. };
  177. &sdmmc2_d47_pins_a {
  178. u-boot,dm-spl;
  179. pins {
  180. u-boot,dm-spl;
  181. };
  182. };
  183. &uart4 {
  184. u-boot,dm-pre-reloc;
  185. };
  186. &uart4_pins_a {
  187. u-boot,dm-pre-reloc;
  188. pins1 {
  189. u-boot,dm-pre-reloc;
  190. };
  191. pins2 {
  192. u-boot,dm-pre-reloc;
  193. /* pull-up on rx to avoid floating level */
  194. bias-pull-up;
  195. };
  196. };