stm32mp151.dtsi 40 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
  4. * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
  5. */
  6. #include <dt-bindings/interrupt-controller/arm-gic.h>
  7. #include <dt-bindings/clock/stm32mp1-clks.h>
  8. #include <dt-bindings/reset/stm32mp1-resets.h>
  9. / {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. cpus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. cpu0: cpu@0 {
  16. compatible = "arm,cortex-a7";
  17. clock-frequency = <650000000>;
  18. device_type = "cpu";
  19. reg = <0>;
  20. operating-points-v2 = <&cpu0_opp_table>;
  21. nvmem-cells = <&part_number_otp>;
  22. nvmem-cell-names = "part_number";
  23. };
  24. };
  25. cpu0_opp_table: cpu0-opp-table {
  26. compatible = "operating-points-v2";
  27. opp-shared;
  28. opp-650000000 {
  29. opp-hz = /bits/ 64 <650000000>;
  30. opp-microvolt = <1200000>;
  31. opp-supported-hw = <0x1>;
  32. };
  33. opp-800000000 {
  34. opp-hz = /bits/ 64 <800000000>;
  35. opp-microvolt = <1350000>;
  36. opp-supported-hw = <0x2>;
  37. };
  38. };
  39. psci {
  40. compatible = "arm,psci-1.0";
  41. method = "smc";
  42. cpu_off = <0x84000002>;
  43. cpu_on = <0x84000003>;
  44. };
  45. intc: interrupt-controller@a0021000 {
  46. compatible = "arm,cortex-a7-gic";
  47. #interrupt-cells = <3>;
  48. interrupt-controller;
  49. reg = <0xa0021000 0x1000>,
  50. <0xa0022000 0x2000>;
  51. };
  52. timer {
  53. compatible = "arm,armv7-timer";
  54. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  55. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  56. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  57. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  58. interrupt-parent = <&intc>;
  59. };
  60. clocks {
  61. clk_hse: clk-hse {
  62. #clock-cells = <0>;
  63. compatible = "fixed-clock";
  64. clock-frequency = <24000000>;
  65. };
  66. clk_hsi: clk-hsi {
  67. #clock-cells = <0>;
  68. compatible = "fixed-clock";
  69. clock-frequency = <64000000>;
  70. };
  71. clk_lse: clk-lse {
  72. #clock-cells = <0>;
  73. compatible = "fixed-clock";
  74. clock-frequency = <32768>;
  75. };
  76. clk_lsi: clk-lsi {
  77. #clock-cells = <0>;
  78. compatible = "fixed-clock";
  79. clock-frequency = <32000>;
  80. };
  81. clk_csi: clk-csi {
  82. #clock-cells = <0>;
  83. compatible = "fixed-clock";
  84. clock-frequency = <4000000>;
  85. };
  86. };
  87. thermal-zones {
  88. cpu_thermal: cpu-thermal {
  89. polling-delay-passive = <0>;
  90. polling-delay = <0>;
  91. thermal-sensors = <&dts>;
  92. trips {
  93. cpu_alert1: cpu-alert1 {
  94. temperature = <85000>;
  95. hysteresis = <0>;
  96. type = "passive";
  97. };
  98. cpu-crit {
  99. temperature = <120000>;
  100. hysteresis = <0>;
  101. type = "critical";
  102. };
  103. };
  104. cooling-maps {
  105. };
  106. };
  107. };
  108. booster: regulator-booster {
  109. compatible = "st,stm32mp1-booster";
  110. st,syscfg = <&syscfg>;
  111. status = "disabled";
  112. };
  113. reboot {
  114. compatible = "syscon-reboot";
  115. regmap = <&rcc>;
  116. offset = <0x404>;
  117. mask = <0x1>;
  118. };
  119. soc {
  120. compatible = "simple-bus";
  121. #address-cells = <1>;
  122. #size-cells = <1>;
  123. interrupt-parent = <&intc>;
  124. ranges;
  125. timers2: timer@40000000 {
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. compatible = "st,stm32-timers";
  129. reg = <0x40000000 0x400>;
  130. clocks = <&rcc TIM2_K>;
  131. clock-names = "int";
  132. dmas = <&dmamux1 18 0x400 0x1>,
  133. <&dmamux1 19 0x400 0x1>,
  134. <&dmamux1 20 0x400 0x1>,
  135. <&dmamux1 21 0x400 0x1>,
  136. <&dmamux1 22 0x400 0x1>;
  137. dma-names = "ch1", "ch2", "ch3", "ch4", "up";
  138. status = "disabled";
  139. pwm {
  140. compatible = "st,stm32-pwm";
  141. #pwm-cells = <3>;
  142. status = "disabled";
  143. };
  144. timer@1 {
  145. compatible = "st,stm32h7-timer-trigger";
  146. reg = <1>;
  147. status = "disabled";
  148. };
  149. counter {
  150. compatible = "st,stm32-timer-counter";
  151. status = "disabled";
  152. };
  153. };
  154. timers3: timer@40001000 {
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. compatible = "st,stm32-timers";
  158. reg = <0x40001000 0x400>;
  159. clocks = <&rcc TIM3_K>;
  160. clock-names = "int";
  161. dmas = <&dmamux1 23 0x400 0x1>,
  162. <&dmamux1 24 0x400 0x1>,
  163. <&dmamux1 25 0x400 0x1>,
  164. <&dmamux1 26 0x400 0x1>,
  165. <&dmamux1 27 0x400 0x1>,
  166. <&dmamux1 28 0x400 0x1>;
  167. dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
  168. status = "disabled";
  169. pwm {
  170. compatible = "st,stm32-pwm";
  171. #pwm-cells = <3>;
  172. status = "disabled";
  173. };
  174. timer@2 {
  175. compatible = "st,stm32h7-timer-trigger";
  176. reg = <2>;
  177. status = "disabled";
  178. };
  179. counter {
  180. compatible = "st,stm32-timer-counter";
  181. status = "disabled";
  182. };
  183. };
  184. timers4: timer@40002000 {
  185. #address-cells = <1>;
  186. #size-cells = <0>;
  187. compatible = "st,stm32-timers";
  188. reg = <0x40002000 0x400>;
  189. clocks = <&rcc TIM4_K>;
  190. clock-names = "int";
  191. dmas = <&dmamux1 29 0x400 0x1>,
  192. <&dmamux1 30 0x400 0x1>,
  193. <&dmamux1 31 0x400 0x1>,
  194. <&dmamux1 32 0x400 0x1>;
  195. dma-names = "ch1", "ch2", "ch3", "ch4";
  196. status = "disabled";
  197. pwm {
  198. compatible = "st,stm32-pwm";
  199. #pwm-cells = <3>;
  200. status = "disabled";
  201. };
  202. timer@3 {
  203. compatible = "st,stm32h7-timer-trigger";
  204. reg = <3>;
  205. status = "disabled";
  206. };
  207. counter {
  208. compatible = "st,stm32-timer-counter";
  209. status = "disabled";
  210. };
  211. };
  212. timers5: timer@40003000 {
  213. #address-cells = <1>;
  214. #size-cells = <0>;
  215. compatible = "st,stm32-timers";
  216. reg = <0x40003000 0x400>;
  217. clocks = <&rcc TIM5_K>;
  218. clock-names = "int";
  219. dmas = <&dmamux1 55 0x400 0x1>,
  220. <&dmamux1 56 0x400 0x1>,
  221. <&dmamux1 57 0x400 0x1>,
  222. <&dmamux1 58 0x400 0x1>,
  223. <&dmamux1 59 0x400 0x1>,
  224. <&dmamux1 60 0x400 0x1>;
  225. dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
  226. status = "disabled";
  227. pwm {
  228. compatible = "st,stm32-pwm";
  229. #pwm-cells = <3>;
  230. status = "disabled";
  231. };
  232. timer@4 {
  233. compatible = "st,stm32h7-timer-trigger";
  234. reg = <4>;
  235. status = "disabled";
  236. };
  237. counter {
  238. compatible = "st,stm32-timer-counter";
  239. status = "disabled";
  240. };
  241. };
  242. timers6: timer@40004000 {
  243. #address-cells = <1>;
  244. #size-cells = <0>;
  245. compatible = "st,stm32-timers";
  246. reg = <0x40004000 0x400>;
  247. clocks = <&rcc TIM6_K>;
  248. clock-names = "int";
  249. dmas = <&dmamux1 69 0x400 0x1>;
  250. dma-names = "up";
  251. status = "disabled";
  252. timer@5 {
  253. compatible = "st,stm32h7-timer-trigger";
  254. reg = <5>;
  255. status = "disabled";
  256. };
  257. };
  258. timers7: timer@40005000 {
  259. #address-cells = <1>;
  260. #size-cells = <0>;
  261. compatible = "st,stm32-timers";
  262. reg = <0x40005000 0x400>;
  263. clocks = <&rcc TIM7_K>;
  264. clock-names = "int";
  265. dmas = <&dmamux1 70 0x400 0x1>;
  266. dma-names = "up";
  267. status = "disabled";
  268. timer@6 {
  269. compatible = "st,stm32h7-timer-trigger";
  270. reg = <6>;
  271. status = "disabled";
  272. };
  273. };
  274. timers12: timer@40006000 {
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. compatible = "st,stm32-timers";
  278. reg = <0x40006000 0x400>;
  279. clocks = <&rcc TIM12_K>;
  280. clock-names = "int";
  281. status = "disabled";
  282. pwm {
  283. compatible = "st,stm32-pwm";
  284. #pwm-cells = <3>;
  285. status = "disabled";
  286. };
  287. timer@11 {
  288. compatible = "st,stm32h7-timer-trigger";
  289. reg = <11>;
  290. status = "disabled";
  291. };
  292. };
  293. timers13: timer@40007000 {
  294. #address-cells = <1>;
  295. #size-cells = <0>;
  296. compatible = "st,stm32-timers";
  297. reg = <0x40007000 0x400>;
  298. clocks = <&rcc TIM13_K>;
  299. clock-names = "int";
  300. status = "disabled";
  301. pwm {
  302. compatible = "st,stm32-pwm";
  303. #pwm-cells = <3>;
  304. status = "disabled";
  305. };
  306. timer@12 {
  307. compatible = "st,stm32h7-timer-trigger";
  308. reg = <12>;
  309. status = "disabled";
  310. };
  311. };
  312. timers14: timer@40008000 {
  313. #address-cells = <1>;
  314. #size-cells = <0>;
  315. compatible = "st,stm32-timers";
  316. reg = <0x40008000 0x400>;
  317. clocks = <&rcc TIM14_K>;
  318. clock-names = "int";
  319. status = "disabled";
  320. pwm {
  321. compatible = "st,stm32-pwm";
  322. #pwm-cells = <3>;
  323. status = "disabled";
  324. };
  325. timer@13 {
  326. compatible = "st,stm32h7-timer-trigger";
  327. reg = <13>;
  328. status = "disabled";
  329. };
  330. };
  331. lptimer1: timer@40009000 {
  332. #address-cells = <1>;
  333. #size-cells = <0>;
  334. compatible = "st,stm32-lptimer";
  335. reg = <0x40009000 0x400>;
  336. clocks = <&rcc LPTIM1_K>;
  337. clock-names = "mux";
  338. status = "disabled";
  339. pwm {
  340. compatible = "st,stm32-pwm-lp";
  341. #pwm-cells = <3>;
  342. status = "disabled";
  343. };
  344. trigger@0 {
  345. compatible = "st,stm32-lptimer-trigger";
  346. reg = <0>;
  347. status = "disabled";
  348. };
  349. counter {
  350. compatible = "st,stm32-lptimer-counter";
  351. status = "disabled";
  352. };
  353. };
  354. spi2: spi@4000b000 {
  355. #address-cells = <1>;
  356. #size-cells = <0>;
  357. compatible = "st,stm32h7-spi";
  358. reg = <0x4000b000 0x400>;
  359. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  360. clocks = <&rcc SPI2_K>;
  361. resets = <&rcc SPI2_R>;
  362. dmas = <&dmamux1 39 0x400 0x05>,
  363. <&dmamux1 40 0x400 0x05>;
  364. dma-names = "rx", "tx";
  365. status = "disabled";
  366. };
  367. i2s2: audio-controller@4000b000 {
  368. compatible = "st,stm32h7-i2s";
  369. #sound-dai-cells = <0>;
  370. reg = <0x4000b000 0x400>;
  371. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  372. dmas = <&dmamux1 39 0x400 0x01>,
  373. <&dmamux1 40 0x400 0x01>;
  374. dma-names = "rx", "tx";
  375. status = "disabled";
  376. };
  377. spi3: spi@4000c000 {
  378. #address-cells = <1>;
  379. #size-cells = <0>;
  380. compatible = "st,stm32h7-spi";
  381. reg = <0x4000c000 0x400>;
  382. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  383. clocks = <&rcc SPI3_K>;
  384. resets = <&rcc SPI3_R>;
  385. dmas = <&dmamux1 61 0x400 0x05>,
  386. <&dmamux1 62 0x400 0x05>;
  387. dma-names = "rx", "tx";
  388. status = "disabled";
  389. };
  390. i2s3: audio-controller@4000c000 {
  391. compatible = "st,stm32h7-i2s";
  392. #sound-dai-cells = <0>;
  393. reg = <0x4000c000 0x400>;
  394. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  395. dmas = <&dmamux1 61 0x400 0x01>,
  396. <&dmamux1 62 0x400 0x01>;
  397. dma-names = "rx", "tx";
  398. status = "disabled";
  399. };
  400. spdifrx: audio-controller@4000d000 {
  401. compatible = "st,stm32h7-spdifrx";
  402. #sound-dai-cells = <0>;
  403. reg = <0x4000d000 0x400>;
  404. clocks = <&rcc SPDIF_K>;
  405. clock-names = "kclk";
  406. interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  407. dmas = <&dmamux1 93 0x400 0x01>,
  408. <&dmamux1 94 0x400 0x01>;
  409. dma-names = "rx", "rx-ctrl";
  410. status = "disabled";
  411. };
  412. usart2: serial@4000e000 {
  413. compatible = "st,stm32h7-uart";
  414. reg = <0x4000e000 0x400>;
  415. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  416. clocks = <&rcc USART2_K>;
  417. status = "disabled";
  418. };
  419. usart3: serial@4000f000 {
  420. compatible = "st,stm32h7-uart";
  421. reg = <0x4000f000 0x400>;
  422. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  423. clocks = <&rcc USART3_K>;
  424. status = "disabled";
  425. };
  426. uart4: serial@40010000 {
  427. compatible = "st,stm32h7-uart";
  428. reg = <0x40010000 0x400>;
  429. interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  430. clocks = <&rcc UART4_K>;
  431. status = "disabled";
  432. };
  433. uart5: serial@40011000 {
  434. compatible = "st,stm32h7-uart";
  435. reg = <0x40011000 0x400>;
  436. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  437. clocks = <&rcc UART5_K>;
  438. status = "disabled";
  439. };
  440. i2c1: i2c@40012000 {
  441. compatible = "st,stm32f7-i2c";
  442. reg = <0x40012000 0x400>;
  443. interrupt-names = "event", "error";
  444. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
  445. <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  446. clocks = <&rcc I2C1_K>;
  447. resets = <&rcc I2C1_R>;
  448. #address-cells = <1>;
  449. #size-cells = <0>;
  450. wakeup-source;
  451. status = "disabled";
  452. };
  453. i2c2: i2c@40013000 {
  454. compatible = "st,stm32f7-i2c";
  455. reg = <0x40013000 0x400>;
  456. interrupt-names = "event", "error";
  457. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  458. <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  459. clocks = <&rcc I2C2_K>;
  460. resets = <&rcc I2C2_R>;
  461. #address-cells = <1>;
  462. #size-cells = <0>;
  463. wakeup-source;
  464. status = "disabled";
  465. };
  466. i2c3: i2c@40014000 {
  467. compatible = "st,stm32f7-i2c";
  468. reg = <0x40014000 0x400>;
  469. interrupt-names = "event", "error";
  470. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  471. <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  472. clocks = <&rcc I2C3_K>;
  473. resets = <&rcc I2C3_R>;
  474. #address-cells = <1>;
  475. #size-cells = <0>;
  476. wakeup-source;
  477. status = "disabled";
  478. };
  479. i2c5: i2c@40015000 {
  480. compatible = "st,stm32f7-i2c";
  481. reg = <0x40015000 0x400>;
  482. interrupt-names = "event", "error";
  483. interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
  484. <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  485. clocks = <&rcc I2C5_K>;
  486. resets = <&rcc I2C5_R>;
  487. #address-cells = <1>;
  488. #size-cells = <0>;
  489. wakeup-source;
  490. status = "disabled";
  491. };
  492. cec: cec@40016000 {
  493. compatible = "st,stm32-cec";
  494. reg = <0x40016000 0x400>;
  495. interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  496. clocks = <&rcc CEC_K>, <&clk_lse>;
  497. clock-names = "cec", "hdmi-cec";
  498. status = "disabled";
  499. };
  500. dac: dac@40017000 {
  501. compatible = "st,stm32h7-dac-core";
  502. reg = <0x40017000 0x400>;
  503. clocks = <&rcc DAC12>;
  504. clock-names = "pclk";
  505. #address-cells = <1>;
  506. #size-cells = <0>;
  507. status = "disabled";
  508. dac1: dac@1 {
  509. compatible = "st,stm32-dac";
  510. #io-channels-cells = <1>;
  511. reg = <1>;
  512. status = "disabled";
  513. };
  514. dac2: dac@2 {
  515. compatible = "st,stm32-dac";
  516. #io-channels-cells = <1>;
  517. reg = <2>;
  518. status = "disabled";
  519. };
  520. };
  521. uart7: serial@40018000 {
  522. compatible = "st,stm32h7-uart";
  523. reg = <0x40018000 0x400>;
  524. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  525. clocks = <&rcc UART7_K>;
  526. status = "disabled";
  527. };
  528. uart8: serial@40019000 {
  529. compatible = "st,stm32h7-uart";
  530. reg = <0x40019000 0x400>;
  531. interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  532. clocks = <&rcc UART8_K>;
  533. status = "disabled";
  534. };
  535. timers1: timer@44000000 {
  536. #address-cells = <1>;
  537. #size-cells = <0>;
  538. compatible = "st,stm32-timers";
  539. reg = <0x44000000 0x400>;
  540. clocks = <&rcc TIM1_K>;
  541. clock-names = "int";
  542. dmas = <&dmamux1 11 0x400 0x1>,
  543. <&dmamux1 12 0x400 0x1>,
  544. <&dmamux1 13 0x400 0x1>,
  545. <&dmamux1 14 0x400 0x1>,
  546. <&dmamux1 15 0x400 0x1>,
  547. <&dmamux1 16 0x400 0x1>,
  548. <&dmamux1 17 0x400 0x1>;
  549. dma-names = "ch1", "ch2", "ch3", "ch4",
  550. "up", "trig", "com";
  551. status = "disabled";
  552. pwm {
  553. compatible = "st,stm32-pwm";
  554. #pwm-cells = <3>;
  555. status = "disabled";
  556. };
  557. timer@0 {
  558. compatible = "st,stm32h7-timer-trigger";
  559. reg = <0>;
  560. status = "disabled";
  561. };
  562. counter {
  563. compatible = "st,stm32-timer-counter";
  564. status = "disabled";
  565. };
  566. };
  567. timers8: timer@44001000 {
  568. #address-cells = <1>;
  569. #size-cells = <0>;
  570. compatible = "st,stm32-timers";
  571. reg = <0x44001000 0x400>;
  572. clocks = <&rcc TIM8_K>;
  573. clock-names = "int";
  574. dmas = <&dmamux1 47 0x400 0x1>,
  575. <&dmamux1 48 0x400 0x1>,
  576. <&dmamux1 49 0x400 0x1>,
  577. <&dmamux1 50 0x400 0x1>,
  578. <&dmamux1 51 0x400 0x1>,
  579. <&dmamux1 52 0x400 0x1>,
  580. <&dmamux1 53 0x400 0x1>;
  581. dma-names = "ch1", "ch2", "ch3", "ch4",
  582. "up", "trig", "com";
  583. status = "disabled";
  584. pwm {
  585. compatible = "st,stm32-pwm";
  586. #pwm-cells = <3>;
  587. status = "disabled";
  588. };
  589. timer@7 {
  590. compatible = "st,stm32h7-timer-trigger";
  591. reg = <7>;
  592. status = "disabled";
  593. };
  594. counter {
  595. compatible = "st,stm32-timer-counter";
  596. status = "disabled";
  597. };
  598. };
  599. usart6: serial@44003000 {
  600. compatible = "st,stm32h7-uart";
  601. reg = <0x44003000 0x400>;
  602. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  603. clocks = <&rcc USART6_K>;
  604. status = "disabled";
  605. };
  606. spi1: spi@44004000 {
  607. #address-cells = <1>;
  608. #size-cells = <0>;
  609. compatible = "st,stm32h7-spi";
  610. reg = <0x44004000 0x400>;
  611. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  612. clocks = <&rcc SPI1_K>;
  613. resets = <&rcc SPI1_R>;
  614. dmas = <&dmamux1 37 0x400 0x05>,
  615. <&dmamux1 38 0x400 0x05>;
  616. dma-names = "rx", "tx";
  617. status = "disabled";
  618. };
  619. i2s1: audio-controller@44004000 {
  620. compatible = "st,stm32h7-i2s";
  621. #sound-dai-cells = <0>;
  622. reg = <0x44004000 0x400>;
  623. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  624. dmas = <&dmamux1 37 0x400 0x01>,
  625. <&dmamux1 38 0x400 0x01>;
  626. dma-names = "rx", "tx";
  627. status = "disabled";
  628. };
  629. spi4: spi@44005000 {
  630. #address-cells = <1>;
  631. #size-cells = <0>;
  632. compatible = "st,stm32h7-spi";
  633. reg = <0x44005000 0x400>;
  634. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  635. clocks = <&rcc SPI4_K>;
  636. resets = <&rcc SPI4_R>;
  637. dmas = <&dmamux1 83 0x400 0x05>,
  638. <&dmamux1 84 0x400 0x05>;
  639. dma-names = "rx", "tx";
  640. status = "disabled";
  641. };
  642. timers15: timer@44006000 {
  643. #address-cells = <1>;
  644. #size-cells = <0>;
  645. compatible = "st,stm32-timers";
  646. reg = <0x44006000 0x400>;
  647. clocks = <&rcc TIM15_K>;
  648. clock-names = "int";
  649. dmas = <&dmamux1 105 0x400 0x1>,
  650. <&dmamux1 106 0x400 0x1>,
  651. <&dmamux1 107 0x400 0x1>,
  652. <&dmamux1 108 0x400 0x1>;
  653. dma-names = "ch1", "up", "trig", "com";
  654. status = "disabled";
  655. pwm {
  656. compatible = "st,stm32-pwm";
  657. #pwm-cells = <3>;
  658. status = "disabled";
  659. };
  660. timer@14 {
  661. compatible = "st,stm32h7-timer-trigger";
  662. reg = <14>;
  663. status = "disabled";
  664. };
  665. };
  666. timers16: timer@44007000 {
  667. #address-cells = <1>;
  668. #size-cells = <0>;
  669. compatible = "st,stm32-timers";
  670. reg = <0x44007000 0x400>;
  671. clocks = <&rcc TIM16_K>;
  672. clock-names = "int";
  673. dmas = <&dmamux1 109 0x400 0x1>,
  674. <&dmamux1 110 0x400 0x1>;
  675. dma-names = "ch1", "up";
  676. status = "disabled";
  677. pwm {
  678. compatible = "st,stm32-pwm";
  679. #pwm-cells = <3>;
  680. status = "disabled";
  681. };
  682. timer@15 {
  683. compatible = "st,stm32h7-timer-trigger";
  684. reg = <15>;
  685. status = "disabled";
  686. };
  687. };
  688. timers17: timer@44008000 {
  689. #address-cells = <1>;
  690. #size-cells = <0>;
  691. compatible = "st,stm32-timers";
  692. reg = <0x44008000 0x400>;
  693. clocks = <&rcc TIM17_K>;
  694. clock-names = "int";
  695. dmas = <&dmamux1 111 0x400 0x1>,
  696. <&dmamux1 112 0x400 0x1>;
  697. dma-names = "ch1", "up";
  698. status = "disabled";
  699. pwm {
  700. compatible = "st,stm32-pwm";
  701. #pwm-cells = <3>;
  702. status = "disabled";
  703. };
  704. timer@16 {
  705. compatible = "st,stm32h7-timer-trigger";
  706. reg = <16>;
  707. status = "disabled";
  708. };
  709. };
  710. spi5: spi@44009000 {
  711. #address-cells = <1>;
  712. #size-cells = <0>;
  713. compatible = "st,stm32h7-spi";
  714. reg = <0x44009000 0x400>;
  715. interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  716. clocks = <&rcc SPI5_K>;
  717. resets = <&rcc SPI5_R>;
  718. dmas = <&dmamux1 85 0x400 0x05>,
  719. <&dmamux1 86 0x400 0x05>;
  720. dma-names = "rx", "tx";
  721. status = "disabled";
  722. };
  723. sai1: sai@4400a000 {
  724. compatible = "st,stm32h7-sai";
  725. #address-cells = <1>;
  726. #size-cells = <1>;
  727. ranges = <0 0x4400a000 0x400>;
  728. reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
  729. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  730. resets = <&rcc SAI1_R>;
  731. status = "disabled";
  732. sai1a: audio-controller@4400a004 {
  733. #sound-dai-cells = <0>;
  734. compatible = "st,stm32-sai-sub-a";
  735. reg = <0x4 0x1c>;
  736. clocks = <&rcc SAI1_K>;
  737. clock-names = "sai_ck";
  738. dmas = <&dmamux1 87 0x400 0x01>;
  739. status = "disabled";
  740. };
  741. sai1b: audio-controller@4400a024 {
  742. #sound-dai-cells = <0>;
  743. compatible = "st,stm32-sai-sub-b";
  744. reg = <0x24 0x1c>;
  745. clocks = <&rcc SAI1_K>;
  746. clock-names = "sai_ck";
  747. dmas = <&dmamux1 88 0x400 0x01>;
  748. status = "disabled";
  749. };
  750. };
  751. sai2: sai@4400b000 {
  752. compatible = "st,stm32h7-sai";
  753. #address-cells = <1>;
  754. #size-cells = <1>;
  755. ranges = <0 0x4400b000 0x400>;
  756. reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
  757. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  758. resets = <&rcc SAI2_R>;
  759. status = "disabled";
  760. sai2a: audio-controller@4400b004 {
  761. #sound-dai-cells = <0>;
  762. compatible = "st,stm32-sai-sub-a";
  763. reg = <0x4 0x1c>;
  764. clocks = <&rcc SAI2_K>;
  765. clock-names = "sai_ck";
  766. dmas = <&dmamux1 89 0x400 0x01>;
  767. status = "disabled";
  768. };
  769. sai2b: audio-controller@4400b024 {
  770. #sound-dai-cells = <0>;
  771. compatible = "st,stm32-sai-sub-b";
  772. reg = <0x24 0x1c>;
  773. clocks = <&rcc SAI2_K>;
  774. clock-names = "sai_ck";
  775. dmas = <&dmamux1 90 0x400 0x01>;
  776. status = "disabled";
  777. };
  778. };
  779. sai3: sai@4400c000 {
  780. compatible = "st,stm32h7-sai";
  781. #address-cells = <1>;
  782. #size-cells = <1>;
  783. ranges = <0 0x4400c000 0x400>;
  784. reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
  785. interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  786. resets = <&rcc SAI3_R>;
  787. status = "disabled";
  788. sai3a: audio-controller@4400c004 {
  789. #sound-dai-cells = <0>;
  790. compatible = "st,stm32-sai-sub-a";
  791. reg = <0x04 0x1c>;
  792. clocks = <&rcc SAI3_K>;
  793. clock-names = "sai_ck";
  794. dmas = <&dmamux1 113 0x400 0x01>;
  795. status = "disabled";
  796. };
  797. sai3b: audio-controller@4400c024 {
  798. #sound-dai-cells = <0>;
  799. compatible = "st,stm32-sai-sub-b";
  800. reg = <0x24 0x1c>;
  801. clocks = <&rcc SAI3_K>;
  802. clock-names = "sai_ck";
  803. dmas = <&dmamux1 114 0x400 0x01>;
  804. status = "disabled";
  805. };
  806. };
  807. dfsdm: dfsdm@4400d000 {
  808. compatible = "st,stm32mp1-dfsdm";
  809. reg = <0x4400d000 0x800>;
  810. clocks = <&rcc DFSDM_K>;
  811. clock-names = "dfsdm";
  812. #address-cells = <1>;
  813. #size-cells = <0>;
  814. status = "disabled";
  815. dfsdm0: filter@0 {
  816. compatible = "st,stm32-dfsdm-adc";
  817. #io-channel-cells = <1>;
  818. reg = <0>;
  819. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  820. dmas = <&dmamux1 101 0x400 0x01>;
  821. dma-names = "rx";
  822. status = "disabled";
  823. };
  824. dfsdm1: filter@1 {
  825. compatible = "st,stm32-dfsdm-adc";
  826. #io-channel-cells = <1>;
  827. reg = <1>;
  828. interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  829. dmas = <&dmamux1 102 0x400 0x01>;
  830. dma-names = "rx";
  831. status = "disabled";
  832. };
  833. dfsdm2: filter@2 {
  834. compatible = "st,stm32-dfsdm-adc";
  835. #io-channel-cells = <1>;
  836. reg = <2>;
  837. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  838. dmas = <&dmamux1 103 0x400 0x01>;
  839. dma-names = "rx";
  840. status = "disabled";
  841. };
  842. dfsdm3: filter@3 {
  843. compatible = "st,stm32-dfsdm-adc";
  844. #io-channel-cells = <1>;
  845. reg = <3>;
  846. interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  847. dmas = <&dmamux1 104 0x400 0x01>;
  848. dma-names = "rx";
  849. status = "disabled";
  850. };
  851. dfsdm4: filter@4 {
  852. compatible = "st,stm32-dfsdm-adc";
  853. #io-channel-cells = <1>;
  854. reg = <4>;
  855. interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  856. dmas = <&dmamux1 91 0x400 0x01>;
  857. dma-names = "rx";
  858. status = "disabled";
  859. };
  860. dfsdm5: filter@5 {
  861. compatible = "st,stm32-dfsdm-adc";
  862. #io-channel-cells = <1>;
  863. reg = <5>;
  864. interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
  865. dmas = <&dmamux1 92 0x400 0x01>;
  866. dma-names = "rx";
  867. status = "disabled";
  868. };
  869. };
  870. dma1: dma-controller@48000000 {
  871. compatible = "st,stm32-dma";
  872. reg = <0x48000000 0x400>;
  873. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  874. <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  875. <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  876. <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  877. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  878. <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  879. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  880. <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  881. clocks = <&rcc DMA1>;
  882. resets = <&rcc DMA1_R>;
  883. #dma-cells = <4>;
  884. st,mem2mem;
  885. dma-requests = <8>;
  886. };
  887. dma2: dma-controller@48001000 {
  888. compatible = "st,stm32-dma";
  889. reg = <0x48001000 0x400>;
  890. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  891. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  892. <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  893. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  894. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  895. <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  896. <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
  897. <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  898. clocks = <&rcc DMA2>;
  899. resets = <&rcc DMA2_R>;
  900. #dma-cells = <4>;
  901. st,mem2mem;
  902. dma-requests = <8>;
  903. };
  904. dmamux1: dma-router@48002000 {
  905. compatible = "st,stm32h7-dmamux";
  906. reg = <0x48002000 0x1c>;
  907. #dma-cells = <3>;
  908. dma-requests = <128>;
  909. dma-masters = <&dma1 &dma2>;
  910. dma-channels = <16>;
  911. clocks = <&rcc DMAMUX>;
  912. resets = <&rcc DMAMUX_R>;
  913. };
  914. adc: adc@48003000 {
  915. compatible = "st,stm32mp1-adc-core";
  916. reg = <0x48003000 0x400>;
  917. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  918. <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  919. clocks = <&rcc ADC12>, <&rcc ADC12_K>;
  920. clock-names = "bus", "adc";
  921. interrupt-controller;
  922. st,syscfg = <&syscfg>;
  923. #interrupt-cells = <1>;
  924. #address-cells = <1>;
  925. #size-cells = <0>;
  926. status = "disabled";
  927. adc1: adc@0 {
  928. compatible = "st,stm32mp1-adc";
  929. #io-channel-cells = <1>;
  930. reg = <0x0>;
  931. interrupt-parent = <&adc>;
  932. interrupts = <0>;
  933. dmas = <&dmamux1 9 0x400 0x01>;
  934. dma-names = "rx";
  935. status = "disabled";
  936. };
  937. adc2: adc@100 {
  938. compatible = "st,stm32mp1-adc";
  939. #io-channel-cells = <1>;
  940. reg = <0x100>;
  941. interrupt-parent = <&adc>;
  942. interrupts = <1>;
  943. dmas = <&dmamux1 10 0x400 0x01>;
  944. dma-names = "rx";
  945. status = "disabled";
  946. };
  947. };
  948. sdmmc3: sdmmc@48004000 {
  949. compatible = "arm,pl18x", "arm,primecell";
  950. arm,primecell-periphid = <0x10153180>;
  951. reg = <0x48004000 0x400>;
  952. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
  953. interrupt-names = "cmd_irq";
  954. clocks = <&rcc SDMMC3_K>;
  955. clock-names = "apb_pclk";
  956. resets = <&rcc SDMMC3_R>;
  957. cap-sd-highspeed;
  958. cap-mmc-highspeed;
  959. max-frequency = <120000000>;
  960. status = "disabled";
  961. };
  962. usbotg_hs: usb-otg@49000000 {
  963. compatible = "st,stm32mp15-hsotg", "snps,dwc2";
  964. reg = <0x49000000 0x10000>;
  965. clocks = <&rcc USBO_K>;
  966. clock-names = "otg";
  967. resets = <&rcc USBO_R>;
  968. reset-names = "dwc2";
  969. interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  970. g-rx-fifo-size = <256>;
  971. g-np-tx-fifo-size = <32>;
  972. g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
  973. dr_mode = "otg";
  974. usb33d-supply = <&usb33>;
  975. status = "disabled";
  976. };
  977. hwspinlock: hwspinlock@4c000000 {
  978. compatible = "st,stm32-hwspinlock";
  979. #hwlock-cells = <1>;
  980. reg = <0x4c000000 0x400>;
  981. clocks = <&rcc HSEM>;
  982. clock-names = "hwspinlock";
  983. };
  984. ipcc: mailbox@4c001000 {
  985. compatible = "st,stm32mp1-ipcc";
  986. #mbox-cells = <1>;
  987. reg = <0x4c001000 0x400>;
  988. st,proc-id = <0>;
  989. interrupts-extended =
  990. <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  991. <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  992. <&exti 61 1>;
  993. interrupt-names = "rx", "tx", "wakeup";
  994. clocks = <&rcc IPCC>;
  995. wakeup-source;
  996. status = "disabled";
  997. };
  998. dcmi: dcmi@4c006000 {
  999. compatible = "st,stm32-dcmi";
  1000. reg = <0x4c006000 0x400>;
  1001. interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
  1002. resets = <&rcc CAMITF_R>;
  1003. clocks = <&rcc DCMI>;
  1004. clock-names = "mclk";
  1005. dmas = <&dmamux1 75 0x400 0x0d>;
  1006. dma-names = "tx";
  1007. status = "disabled";
  1008. };
  1009. rcc: rcc@50000000 {
  1010. compatible = "st,stm32mp1-rcc", "syscon";
  1011. reg = <0x50000000 0x1000>;
  1012. #clock-cells = <1>;
  1013. #reset-cells = <1>;
  1014. };
  1015. pwr_regulators: pwr@50001000 {
  1016. compatible = "st,stm32mp1,pwr-reg";
  1017. reg = <0x50001000 0x10>;
  1018. reg11: reg11 {
  1019. regulator-name = "reg11";
  1020. regulator-min-microvolt = <1100000>;
  1021. regulator-max-microvolt = <1100000>;
  1022. };
  1023. reg18: reg18 {
  1024. regulator-name = "reg18";
  1025. regulator-min-microvolt = <1800000>;
  1026. regulator-max-microvolt = <1800000>;
  1027. };
  1028. usb33: usb33 {
  1029. regulator-name = "usb33";
  1030. regulator-min-microvolt = <3300000>;
  1031. regulator-max-microvolt = <3300000>;
  1032. };
  1033. };
  1034. exti: interrupt-controller@5000d000 {
  1035. compatible = "st,stm32mp1-exti", "syscon";
  1036. interrupt-controller;
  1037. #interrupt-cells = <2>;
  1038. reg = <0x5000d000 0x400>;
  1039. };
  1040. syscfg: syscon@50020000 {
  1041. compatible = "st,stm32mp157-syscfg", "syscon";
  1042. reg = <0x50020000 0x400>;
  1043. clocks = <&rcc SYSCFG>;
  1044. };
  1045. lptimer2: timer@50021000 {
  1046. #address-cells = <1>;
  1047. #size-cells = <0>;
  1048. compatible = "st,stm32-lptimer";
  1049. reg = <0x50021000 0x400>;
  1050. clocks = <&rcc LPTIM2_K>;
  1051. clock-names = "mux";
  1052. status = "disabled";
  1053. pwm {
  1054. compatible = "st,stm32-pwm-lp";
  1055. #pwm-cells = <3>;
  1056. status = "disabled";
  1057. };
  1058. trigger@1 {
  1059. compatible = "st,stm32-lptimer-trigger";
  1060. reg = <1>;
  1061. status = "disabled";
  1062. };
  1063. counter {
  1064. compatible = "st,stm32-lptimer-counter";
  1065. status = "disabled";
  1066. };
  1067. };
  1068. lptimer3: timer@50022000 {
  1069. #address-cells = <1>;
  1070. #size-cells = <0>;
  1071. compatible = "st,stm32-lptimer";
  1072. reg = <0x50022000 0x400>;
  1073. clocks = <&rcc LPTIM3_K>;
  1074. clock-names = "mux";
  1075. status = "disabled";
  1076. pwm {
  1077. compatible = "st,stm32-pwm-lp";
  1078. #pwm-cells = <3>;
  1079. status = "disabled";
  1080. };
  1081. trigger@2 {
  1082. compatible = "st,stm32-lptimer-trigger";
  1083. reg = <2>;
  1084. status = "disabled";
  1085. };
  1086. };
  1087. lptimer4: timer@50023000 {
  1088. compatible = "st,stm32-lptimer";
  1089. reg = <0x50023000 0x400>;
  1090. clocks = <&rcc LPTIM4_K>;
  1091. clock-names = "mux";
  1092. status = "disabled";
  1093. pwm {
  1094. compatible = "st,stm32-pwm-lp";
  1095. #pwm-cells = <3>;
  1096. status = "disabled";
  1097. };
  1098. };
  1099. lptimer5: timer@50024000 {
  1100. compatible = "st,stm32-lptimer";
  1101. reg = <0x50024000 0x400>;
  1102. clocks = <&rcc LPTIM5_K>;
  1103. clock-names = "mux";
  1104. status = "disabled";
  1105. pwm {
  1106. compatible = "st,stm32-pwm-lp";
  1107. #pwm-cells = <3>;
  1108. status = "disabled";
  1109. };
  1110. };
  1111. vrefbuf: vrefbuf@50025000 {
  1112. compatible = "st,stm32-vrefbuf";
  1113. reg = <0x50025000 0x8>;
  1114. regulator-min-microvolt = <1500000>;
  1115. regulator-max-microvolt = <2500000>;
  1116. clocks = <&rcc VREF>;
  1117. status = "disabled";
  1118. };
  1119. sai4: sai@50027000 {
  1120. compatible = "st,stm32h7-sai";
  1121. #address-cells = <1>;
  1122. #size-cells = <1>;
  1123. ranges = <0 0x50027000 0x400>;
  1124. reg = <0x50027000 0x4>, <0x500273f0 0x10>;
  1125. interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  1126. resets = <&rcc SAI4_R>;
  1127. status = "disabled";
  1128. sai4a: audio-controller@50027004 {
  1129. #sound-dai-cells = <0>;
  1130. compatible = "st,stm32-sai-sub-a";
  1131. reg = <0x04 0x1c>;
  1132. clocks = <&rcc SAI4_K>;
  1133. clock-names = "sai_ck";
  1134. dmas = <&dmamux1 99 0x400 0x01>;
  1135. status = "disabled";
  1136. };
  1137. sai4b: audio-controller@50027024 {
  1138. #sound-dai-cells = <0>;
  1139. compatible = "st,stm32-sai-sub-b";
  1140. reg = <0x24 0x1c>;
  1141. clocks = <&rcc SAI4_K>;
  1142. clock-names = "sai_ck";
  1143. dmas = <&dmamux1 100 0x400 0x01>;
  1144. status = "disabled";
  1145. };
  1146. };
  1147. dts: thermal@50028000 {
  1148. compatible = "st,stm32-thermal";
  1149. reg = <0x50028000 0x100>;
  1150. interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
  1151. clocks = <&rcc TMPSENS>;
  1152. clock-names = "pclk";
  1153. #thermal-sensor-cells = <0>;
  1154. status = "disabled";
  1155. };
  1156. hash1: hash@54002000 {
  1157. compatible = "st,stm32f756-hash";
  1158. reg = <0x54002000 0x400>;
  1159. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  1160. clocks = <&rcc HASH1>;
  1161. resets = <&rcc HASH1_R>;
  1162. dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
  1163. dma-names = "in";
  1164. dma-maxburst = <2>;
  1165. status = "disabled";
  1166. };
  1167. rng1: rng@54003000 {
  1168. compatible = "st,stm32-rng";
  1169. reg = <0x54003000 0x400>;
  1170. clocks = <&rcc RNG1_K>;
  1171. resets = <&rcc RNG1_R>;
  1172. status = "disabled";
  1173. };
  1174. mdma1: dma-controller@58000000 {
  1175. compatible = "st,stm32h7-mdma";
  1176. reg = <0x58000000 0x1000>;
  1177. interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  1178. clocks = <&rcc MDMA>;
  1179. resets = <&rcc MDMA_R>;
  1180. #dma-cells = <5>;
  1181. dma-channels = <32>;
  1182. dma-requests = <48>;
  1183. };
  1184. fmc: nand-controller@58002000 {
  1185. compatible = "st,stm32mp15-fmc2";
  1186. reg = <0x58002000 0x1000>,
  1187. <0x80000000 0x1000>,
  1188. <0x88010000 0x1000>,
  1189. <0x88020000 0x1000>,
  1190. <0x81000000 0x1000>,
  1191. <0x89010000 0x1000>,
  1192. <0x89020000 0x1000>;
  1193. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  1194. dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
  1195. <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
  1196. <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
  1197. dma-names = "tx", "rx", "ecc";
  1198. clocks = <&rcc FMC_K>;
  1199. resets = <&rcc FMC_R>;
  1200. status = "disabled";
  1201. };
  1202. qspi: spi@58003000 {
  1203. compatible = "st,stm32f469-qspi";
  1204. reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
  1205. reg-names = "qspi", "qspi_mm";
  1206. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
  1207. dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
  1208. <&mdma1 22 0x10 0x100008 0x0 0x0>;
  1209. dma-names = "tx", "rx";
  1210. clocks = <&rcc QSPI_K>;
  1211. resets = <&rcc QSPI_R>;
  1212. status = "disabled";
  1213. };
  1214. sdmmc1: sdmmc@58005000 {
  1215. compatible = "arm,pl18x", "arm,primecell";
  1216. arm,primecell-periphid = <0x10153180>;
  1217. reg = <0x58005000 0x1000>;
  1218. interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  1219. interrupt-names = "cmd_irq";
  1220. clocks = <&rcc SDMMC1_K>;
  1221. clock-names = "apb_pclk";
  1222. resets = <&rcc SDMMC1_R>;
  1223. cap-sd-highspeed;
  1224. cap-mmc-highspeed;
  1225. max-frequency = <120000000>;
  1226. status = "disabled";
  1227. };
  1228. sdmmc2: sdmmc@58007000 {
  1229. compatible = "arm,pl18x", "arm,primecell";
  1230. arm,primecell-periphid = <0x10153180>;
  1231. reg = <0x58007000 0x1000>;
  1232. interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
  1233. interrupt-names = "cmd_irq";
  1234. clocks = <&rcc SDMMC2_K>;
  1235. clock-names = "apb_pclk";
  1236. resets = <&rcc SDMMC2_R>;
  1237. cap-sd-highspeed;
  1238. cap-mmc-highspeed;
  1239. max-frequency = <120000000>;
  1240. status = "disabled";
  1241. };
  1242. crc1: crc@58009000 {
  1243. compatible = "st,stm32f7-crc";
  1244. reg = <0x58009000 0x400>;
  1245. clocks = <&rcc CRC1>;
  1246. status = "disabled";
  1247. };
  1248. stmmac_axi_config_0: stmmac-axi-config {
  1249. snps,wr_osr_lmt = <0x7>;
  1250. snps,rd_osr_lmt = <0x7>;
  1251. snps,blen = <0 0 0 0 16 8 4>;
  1252. };
  1253. ethernet0: ethernet@5800a000 {
  1254. compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
  1255. reg = <0x5800a000 0x2000>;
  1256. reg-names = "stmmaceth";
  1257. interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  1258. interrupt-names = "macirq";
  1259. clock-names = "stmmaceth",
  1260. "mac-clk-tx",
  1261. "mac-clk-rx",
  1262. "eth-ck",
  1263. "ethstp",
  1264. "syscfg-clk";
  1265. clocks = <&rcc ETHMAC>,
  1266. <&rcc ETHTX>,
  1267. <&rcc ETHRX>,
  1268. <&rcc ETHCK_K>,
  1269. <&rcc ETHSTP>,
  1270. <&rcc SYSCFG>;
  1271. st,syscon = <&syscfg 0x4>;
  1272. snps,mixed-burst;
  1273. snps,pbl = <2>;
  1274. snps,en-tx-lpi-clockgating;
  1275. snps,axi-config = <&stmmac_axi_config_0>;
  1276. snps,tso;
  1277. status = "disabled";
  1278. };
  1279. usbh_ohci: usbh-ohci@5800c000 {
  1280. compatible = "generic-ohci";
  1281. reg = <0x5800c000 0x1000>;
  1282. clocks = <&rcc USBH>;
  1283. resets = <&rcc USBH_R>;
  1284. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  1285. status = "disabled";
  1286. };
  1287. usbh_ehci: usbh-ehci@5800d000 {
  1288. compatible = "generic-ehci";
  1289. reg = <0x5800d000 0x1000>;
  1290. clocks = <&rcc USBH>;
  1291. resets = <&rcc USBH_R>;
  1292. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  1293. companion = <&usbh_ohci>;
  1294. status = "disabled";
  1295. };
  1296. ltdc: display-controller@5a001000 {
  1297. compatible = "st,stm32-ltdc";
  1298. reg = <0x5a001000 0x400>;
  1299. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
  1300. <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  1301. clocks = <&rcc LTDC_PX>;
  1302. clock-names = "lcd";
  1303. resets = <&rcc LTDC_R>;
  1304. status = "disabled";
  1305. };
  1306. iwdg2: watchdog@5a002000 {
  1307. compatible = "st,stm32mp1-iwdg";
  1308. reg = <0x5a002000 0x400>;
  1309. clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
  1310. clock-names = "pclk", "lsi";
  1311. status = "disabled";
  1312. };
  1313. usbphyc: usbphyc@5a006000 {
  1314. #address-cells = <1>;
  1315. #size-cells = <0>;
  1316. compatible = "st,stm32mp1-usbphyc";
  1317. reg = <0x5a006000 0x1000>;
  1318. clocks = <&rcc USBPHY_K>;
  1319. resets = <&rcc USBPHY_R>;
  1320. vdda1v1-supply = <&reg11>;
  1321. vdda1v8-supply = <&reg18>;
  1322. status = "disabled";
  1323. usbphyc_port0: usb-phy@0 {
  1324. #phy-cells = <0>;
  1325. reg = <0>;
  1326. };
  1327. usbphyc_port1: usb-phy@1 {
  1328. #phy-cells = <1>;
  1329. reg = <1>;
  1330. };
  1331. };
  1332. usart1: serial@5c000000 {
  1333. compatible = "st,stm32h7-uart";
  1334. reg = <0x5c000000 0x400>;
  1335. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  1336. clocks = <&rcc USART1_K>;
  1337. status = "disabled";
  1338. };
  1339. spi6: spi@5c001000 {
  1340. #address-cells = <1>;
  1341. #size-cells = <0>;
  1342. compatible = "st,stm32h7-spi";
  1343. reg = <0x5c001000 0x400>;
  1344. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  1345. clocks = <&rcc SPI6_K>;
  1346. resets = <&rcc SPI6_R>;
  1347. dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
  1348. <&mdma1 35 0x0 0x40002 0x0 0x0>;
  1349. dma-names = "rx", "tx";
  1350. status = "disabled";
  1351. };
  1352. i2c4: i2c@5c002000 {
  1353. compatible = "st,stm32f7-i2c";
  1354. reg = <0x5c002000 0x400>;
  1355. interrupt-names = "event", "error";
  1356. interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  1357. <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  1358. clocks = <&rcc I2C4_K>;
  1359. resets = <&rcc I2C4_R>;
  1360. #address-cells = <1>;
  1361. #size-cells = <0>;
  1362. wakeup-source;
  1363. status = "disabled";
  1364. };
  1365. rtc: rtc@5c004000 {
  1366. compatible = "st,stm32mp1-rtc";
  1367. reg = <0x5c004000 0x400>;
  1368. clocks = <&rcc RTCAPB>, <&rcc RTC>;
  1369. clock-names = "pclk", "rtc_ck";
  1370. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  1371. status = "disabled";
  1372. };
  1373. bsec: efuse@5c005000 {
  1374. compatible = "st,stm32mp15-bsec";
  1375. reg = <0x5c005000 0x400>;
  1376. #address-cells = <1>;
  1377. #size-cells = <1>;
  1378. part_number_otp: part_number_otp@4 {
  1379. reg = <0x4 0x1>;
  1380. };
  1381. ts_cal1: calib@5c {
  1382. reg = <0x5c 0x2>;
  1383. };
  1384. ts_cal2: calib@5e {
  1385. reg = <0x5e 0x2>;
  1386. };
  1387. };
  1388. i2c6: i2c@5c009000 {
  1389. compatible = "st,stm32f7-i2c";
  1390. reg = <0x5c009000 0x400>;
  1391. interrupt-names = "event", "error";
  1392. interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
  1393. <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
  1394. clocks = <&rcc I2C6_K>;
  1395. resets = <&rcc I2C6_R>;
  1396. #address-cells = <1>;
  1397. #size-cells = <0>;
  1398. wakeup-source;
  1399. status = "disabled";
  1400. };
  1401. /*
  1402. * Break node order to solve dependency probe issue between
  1403. * pinctrl and exti.
  1404. */
  1405. pinctrl: pin-controller@50002000 {
  1406. #address-cells = <1>;
  1407. #size-cells = <1>;
  1408. compatible = "st,stm32mp157-pinctrl";
  1409. ranges = <0 0x50002000 0xa400>;
  1410. interrupt-parent = <&exti>;
  1411. st,syscfg = <&exti 0x60 0xff>;
  1412. hwlocks = <&hwspinlock 0>;
  1413. pins-are-numbered;
  1414. gpioa: gpio@50002000 {
  1415. gpio-controller;
  1416. #gpio-cells = <2>;
  1417. interrupt-controller;
  1418. #interrupt-cells = <2>;
  1419. reg = <0x0 0x400>;
  1420. clocks = <&rcc GPIOA>;
  1421. st,bank-name = "GPIOA";
  1422. status = "disabled";
  1423. };
  1424. gpiob: gpio@50003000 {
  1425. gpio-controller;
  1426. #gpio-cells = <2>;
  1427. interrupt-controller;
  1428. #interrupt-cells = <2>;
  1429. reg = <0x1000 0x400>;
  1430. clocks = <&rcc GPIOB>;
  1431. st,bank-name = "GPIOB";
  1432. status = "disabled";
  1433. };
  1434. gpioc: gpio@50004000 {
  1435. gpio-controller;
  1436. #gpio-cells = <2>;
  1437. interrupt-controller;
  1438. #interrupt-cells = <2>;
  1439. reg = <0x2000 0x400>;
  1440. clocks = <&rcc GPIOC>;
  1441. st,bank-name = "GPIOC";
  1442. status = "disabled";
  1443. };
  1444. gpiod: gpio@50005000 {
  1445. gpio-controller;
  1446. #gpio-cells = <2>;
  1447. interrupt-controller;
  1448. #interrupt-cells = <2>;
  1449. reg = <0x3000 0x400>;
  1450. clocks = <&rcc GPIOD>;
  1451. st,bank-name = "GPIOD";
  1452. status = "disabled";
  1453. };
  1454. gpioe: gpio@50006000 {
  1455. gpio-controller;
  1456. #gpio-cells = <2>;
  1457. interrupt-controller;
  1458. #interrupt-cells = <2>;
  1459. reg = <0x4000 0x400>;
  1460. clocks = <&rcc GPIOE>;
  1461. st,bank-name = "GPIOE";
  1462. status = "disabled";
  1463. };
  1464. gpiof: gpio@50007000 {
  1465. gpio-controller;
  1466. #gpio-cells = <2>;
  1467. interrupt-controller;
  1468. #interrupt-cells = <2>;
  1469. reg = <0x5000 0x400>;
  1470. clocks = <&rcc GPIOF>;
  1471. st,bank-name = "GPIOF";
  1472. status = "disabled";
  1473. };
  1474. gpiog: gpio@50008000 {
  1475. gpio-controller;
  1476. #gpio-cells = <2>;
  1477. interrupt-controller;
  1478. #interrupt-cells = <2>;
  1479. reg = <0x6000 0x400>;
  1480. clocks = <&rcc GPIOG>;
  1481. st,bank-name = "GPIOG";
  1482. status = "disabled";
  1483. };
  1484. gpioh: gpio@50009000 {
  1485. gpio-controller;
  1486. #gpio-cells = <2>;
  1487. interrupt-controller;
  1488. #interrupt-cells = <2>;
  1489. reg = <0x7000 0x400>;
  1490. clocks = <&rcc GPIOH>;
  1491. st,bank-name = "GPIOH";
  1492. status = "disabled";
  1493. };
  1494. gpioi: gpio@5000a000 {
  1495. gpio-controller;
  1496. #gpio-cells = <2>;
  1497. interrupt-controller;
  1498. #interrupt-cells = <2>;
  1499. reg = <0x8000 0x400>;
  1500. clocks = <&rcc GPIOI>;
  1501. st,bank-name = "GPIOI";
  1502. status = "disabled";
  1503. };
  1504. gpioj: gpio@5000b000 {
  1505. gpio-controller;
  1506. #gpio-cells = <2>;
  1507. interrupt-controller;
  1508. #interrupt-cells = <2>;
  1509. reg = <0x9000 0x400>;
  1510. clocks = <&rcc GPIOJ>;
  1511. st,bank-name = "GPIOJ";
  1512. status = "disabled";
  1513. };
  1514. gpiok: gpio@5000c000 {
  1515. gpio-controller;
  1516. #gpio-cells = <2>;
  1517. interrupt-controller;
  1518. #interrupt-cells = <2>;
  1519. reg = <0xa000 0x400>;
  1520. clocks = <&rcc GPIOK>;
  1521. st,bank-name = "GPIOK";
  1522. status = "disabled";
  1523. };
  1524. };
  1525. pinctrl_z: pin-controller-z@54004000 {
  1526. #address-cells = <1>;
  1527. #size-cells = <1>;
  1528. compatible = "st,stm32mp157-z-pinctrl";
  1529. ranges = <0 0x54004000 0x400>;
  1530. pins-are-numbered;
  1531. interrupt-parent = <&exti>;
  1532. st,syscfg = <&exti 0x60 0xff>;
  1533. hwlocks = <&hwspinlock 0>;
  1534. gpioz: gpio@54004000 {
  1535. gpio-controller;
  1536. #gpio-cells = <2>;
  1537. interrupt-controller;
  1538. #interrupt-cells = <2>;
  1539. reg = <0 0x400>;
  1540. clocks = <&rcc GPIOZ>;
  1541. st,bank-name = "GPIOZ";
  1542. st,bank-ioport = <11>;
  1543. status = "disabled";
  1544. };
  1545. };
  1546. };
  1547. mlahb: ahb {
  1548. compatible = "st,mlahb", "simple-bus";
  1549. #address-cells = <1>;
  1550. #size-cells = <1>;
  1551. ranges;
  1552. dma-ranges = <0x00000000 0x38000000 0x10000>,
  1553. <0x10000000 0x10000000 0x60000>,
  1554. <0x30000000 0x30000000 0x60000>;
  1555. m4_rproc: m4@10000000 {
  1556. compatible = "st,stm32mp1-m4";
  1557. reg = <0x10000000 0x40000>,
  1558. <0x30000000 0x40000>,
  1559. <0x38000000 0x10000>;
  1560. resets = <&rcc MCU_R>;
  1561. st,syscfg-holdboot = <&rcc 0x10C 0x1>;
  1562. st,syscfg-tz = <&rcc 0x000 0x1>;
  1563. status = "disabled";
  1564. };
  1565. };
  1566. };