stm32mp15-u-boot.dtsi 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. / {
  6. aliases {
  7. gpio0 = &gpioa;
  8. gpio1 = &gpiob;
  9. gpio2 = &gpioc;
  10. gpio3 = &gpiod;
  11. gpio4 = &gpioe;
  12. gpio5 = &gpiof;
  13. gpio6 = &gpiog;
  14. gpio7 = &gpioh;
  15. gpio8 = &gpioi;
  16. gpio9 = &gpioj;
  17. gpio10 = &gpiok;
  18. gpio25 = &gpioz;
  19. pinctrl0 = &pinctrl;
  20. pinctrl1 = &pinctrl_z;
  21. };
  22. clocks {
  23. u-boot,dm-pre-reloc;
  24. };
  25. /* need PSCI for sysreset during board_f */
  26. psci {
  27. u-boot,dm-pre-proper;
  28. };
  29. reboot {
  30. u-boot,dm-pre-reloc;
  31. };
  32. soc {
  33. u-boot,dm-pre-reloc;
  34. ddr: ddr@5a003000 {
  35. u-boot,dm-pre-reloc;
  36. compatible = "st,stm32mp1-ddr";
  37. reg = <0x5A003000 0x550
  38. 0x5A004000 0x234>;
  39. clocks = <&rcc AXIDCG>,
  40. <&rcc DDRC1>,
  41. <&rcc DDRC2>,
  42. <&rcc DDRPHYC>,
  43. <&rcc DDRCAPB>,
  44. <&rcc DDRPHYCAPB>;
  45. clock-names = "axidcg",
  46. "ddrc1",
  47. "ddrc2",
  48. "ddrphyc",
  49. "ddrcapb",
  50. "ddrphycapb";
  51. status = "okay";
  52. };
  53. };
  54. };
  55. &bsec {
  56. u-boot,dm-pre-reloc;
  57. };
  58. &clk_csi {
  59. u-boot,dm-pre-reloc;
  60. };
  61. &clk_hsi {
  62. u-boot,dm-pre-reloc;
  63. };
  64. &clk_hse {
  65. u-boot,dm-pre-reloc;
  66. };
  67. &clk_lsi {
  68. u-boot,dm-pre-reloc;
  69. };
  70. &clk_lse {
  71. u-boot,dm-pre-reloc;
  72. };
  73. &cpu0_opp_table {
  74. u-boot,dm-spl;
  75. opp-650000000 {
  76. u-boot,dm-spl;
  77. };
  78. opp-800000000 {
  79. u-boot,dm-spl;
  80. };
  81. };
  82. &gpioa {
  83. u-boot,dm-pre-reloc;
  84. };
  85. &gpiob {
  86. u-boot,dm-pre-reloc;
  87. };
  88. &gpioc {
  89. u-boot,dm-pre-reloc;
  90. };
  91. &gpiod {
  92. u-boot,dm-pre-reloc;
  93. };
  94. &gpioe {
  95. u-boot,dm-pre-reloc;
  96. };
  97. &gpiof {
  98. u-boot,dm-pre-reloc;
  99. };
  100. &gpiog {
  101. u-boot,dm-pre-reloc;
  102. };
  103. &gpioh {
  104. u-boot,dm-pre-reloc;
  105. };
  106. &gpioi {
  107. u-boot,dm-pre-reloc;
  108. };
  109. &gpioj {
  110. u-boot,dm-pre-reloc;
  111. };
  112. &gpiok {
  113. u-boot,dm-pre-reloc;
  114. };
  115. &gpioz {
  116. u-boot,dm-pre-reloc;
  117. };
  118. &iwdg2 {
  119. u-boot,dm-pre-reloc;
  120. };
  121. /* pre-reloc probe = reserve video frame buffer in video_reserve() */
  122. &ltdc {
  123. u-boot,dm-pre-proper;
  124. };
  125. &pinctrl {
  126. u-boot,dm-pre-reloc;
  127. };
  128. &pinctrl_z {
  129. u-boot,dm-pre-reloc;
  130. };
  131. &pwr_regulators {
  132. u-boot,dm-pre-reloc;
  133. };
  134. &rcc {
  135. u-boot,dm-pre-reloc;
  136. #address-cells = <1>;
  137. #size-cells = <0>;
  138. };
  139. &sdmmc1 {
  140. compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
  141. };
  142. &sdmmc2 {
  143. compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
  144. };
  145. &sdmmc3 {
  146. compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
  147. };
  148. &usbotg_hs {
  149. compatible = "st,stm32mp1-hsotg", "snps,dwc2";
  150. };