w83c553f.c 6.0 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
  25. * write protection (for flash) in function 0 of the chip.
  26. * Enabling function 1 (IDE controller of the chip.
  27. */
  28. #include <common.h>
  29. #include <config.h>
  30. #ifdef CFG_WINBOND_83C553
  31. #include <asm/io.h>
  32. #include <pci.h>
  33. #include <w83c553f.h>
  34. #define out8(addr,val) do { \
  35. out_8((u8*) (addr),(val)); udelay(1); \
  36. } while (0)
  37. #define out16(addr,val) do { \
  38. out_be16((u16*) (addr),(val)); udelay(1); \
  39. } while (0)
  40. extern uint ide_bus_offset[CFG_IDE_MAXBUS];
  41. void initialise_pic(void);
  42. void initialise_dma(void);
  43. void initialise_w83c553f(void)
  44. {
  45. pci_dev_t devbusfn;
  46. unsigned char reg8;
  47. unsigned short reg16;
  48. unsigned int reg32;
  49. devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
  50. if (devbusfn == -1)
  51. {
  52. printf("Error: Cannot find W83C553F controller on any PCI bus.");
  53. return;
  54. }
  55. pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
  56. reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  57. pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
  58. pci_read_config_byte(devbusfn, WINBOND_IPADCR, &reg8);
  59. /* 16 MB ISA memory space */
  60. reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
  61. reg8 &= ~IPADCR_MBE512;
  62. pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
  63. pci_read_config_byte(devbusfn, WINBOND_CSCR, &reg8);
  64. /* switch off BIOS write protection */
  65. reg8 |= CSCR_UBIOSCSE;
  66. reg8 &= ~CSCR_BIOSWP;
  67. pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
  68. /*
  69. * Interrupt routing:
  70. * - IDE -> IRQ 9/0
  71. * - INTA -> IRQ 10
  72. * - INTB -> IRQ 11
  73. * - INTC -> IRQ 14
  74. * - INTD -> IRQ 15
  75. */
  76. pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
  77. pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
  78. /*
  79. * Read IDE bus offsets from function 1 device.
  80. * We must unmask the LSB indicating that ist is an IO address.
  81. */
  82. devbusfn |= PCI_BDF(0,0,1);
  83. /*
  84. * Switch off legacy IRQ for IDE and IDE port 1.
  85. */
  86. pci_write_config_byte(devbusfn, 0x09, 0x8F);
  87. pci_read_config_dword(devbusfn, WINDOND_IDECSR, &reg32);
  88. reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
  89. pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
  90. pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
  91. ide_bus_offset[0] &= ~1;
  92. #if CFG_IDE_MAXBUS > 1
  93. pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
  94. ide_bus_offset[1] &= ~1;
  95. #endif
  96. /*
  97. * Enable function 1, IDE -> busmastering and IO space access
  98. */
  99. pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
  100. reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
  101. pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
  102. /*
  103. * Initialise ISA interrupt controller
  104. */
  105. initialise_pic();
  106. /*
  107. * Initialise DMA controller
  108. */
  109. initialise_dma();
  110. }
  111. void initialise_pic(void)
  112. {
  113. out8(W83C553F_PIC1_ICW1, 0x11);
  114. out8(W83C553F_PIC1_ICW2, 0x08);
  115. out8(W83C553F_PIC1_ICW3, 0x04);
  116. out8(W83C553F_PIC1_ICW4, 0x01);
  117. out8(W83C553F_PIC1_OCW1, 0xfb);
  118. out8(W83C553F_PIC1_ELC, 0x20);
  119. out8(W83C553F_PIC2_ICW1, 0x11);
  120. out8(W83C553F_PIC2_ICW2, 0x08);
  121. out8(W83C553F_PIC2_ICW3, 0x02);
  122. out8(W83C553F_PIC2_ICW4, 0x01);
  123. out8(W83C553F_PIC2_OCW1, 0xff);
  124. out8(W83C553F_PIC2_ELC, 0xce);
  125. out8(W83C553F_TMR1_CMOD, 0x74);
  126. out8(W83C553F_PIC2_OCW1, 0x20);
  127. out8(W83C553F_PIC1_OCW1, 0x20);
  128. out8(W83C553F_PIC2_OCW1, 0x2b);
  129. out8(W83C553F_PIC1_OCW1, 0x2b);
  130. }
  131. void initialise_dma(void)
  132. {
  133. unsigned int channel;
  134. unsigned int rvalue1, rvalue2;
  135. /* perform a H/W reset of the devices */
  136. out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
  137. out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
  138. /* initialise all channels to a sane state */
  139. for (channel = 0; channel < 4; channel++) {
  140. /*
  141. * dependent upon the channel, setup the specifics:
  142. *
  143. * demand
  144. * address-increment
  145. * autoinitialize-disable
  146. * verify-transfer
  147. */
  148. switch (channel) {
  149. case 0:
  150. rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
  151. rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
  152. break;
  153. case 1:
  154. rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
  155. rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
  156. break;
  157. case 2:
  158. rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
  159. rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
  160. break;
  161. case 3:
  162. rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
  163. rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
  164. break;
  165. default:
  166. rvalue1 = 0x00;
  167. rvalue2 = 0x00;
  168. break;
  169. }
  170. /* write to write mode registers */
  171. out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
  172. out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
  173. }
  174. /* enable all channels */
  175. out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
  176. out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
  177. /*
  178. * initialize the global DMA configuration
  179. *
  180. * DACK# active low
  181. * DREQ active high
  182. * fixed priority
  183. * channel group enable
  184. */
  185. out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
  186. out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
  187. }
  188. #endif /* CFG_WINBOND_83C553 */