eepro100.c 22 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <malloc.h>
  25. #include <net.h>
  26. #include <asm/io.h>
  27. #include <pci.h>
  28. #undef DEBUG
  29. #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
  30. defined(CONFIG_EEPRO100)
  31. /* Ethernet chip registers.
  32. */
  33. #define SCBStatus 0 /* Rx/Command Unit Status *Word* */
  34. #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
  35. #define SCBCmd 2 /* Rx/Command Unit Command *Word* */
  36. #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
  37. #define SCBPointer 4 /* General purpose pointer. */
  38. #define SCBPort 8 /* Misc. commands and operands. */
  39. #define SCBflash 12 /* Flash memory control. */
  40. #define SCBeeprom 14 /* EEPROM memory control. */
  41. #define SCBCtrlMDI 16 /* MDI interface control. */
  42. #define SCBEarlyRx 20 /* Early receive byte count. */
  43. #define SCBGenControl 28 /* 82559 General Control Register */
  44. #define SCBGenStatus 29 /* 82559 General Status register */
  45. /* 82559 SCB status word defnitions
  46. */
  47. #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
  48. #define SCB_STATUS_FR 0x4000 /* frame received */
  49. #define SCB_STATUS_CNA 0x2000 /* CU left active state */
  50. #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
  51. #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
  52. #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
  53. #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
  54. #define SCB_INTACK_MASK 0xFD00 /* all the above */
  55. #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
  56. #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
  57. /* System control block commands
  58. */
  59. /* CU Commands */
  60. #define CU_NOP 0x0000
  61. #define CU_START 0x0010
  62. #define CU_RESUME 0x0020
  63. #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
  64. #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
  65. #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
  66. #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
  67. /* RUC Commands */
  68. #define RUC_NOP 0x0000
  69. #define RUC_START 0x0001
  70. #define RUC_RESUME 0x0002
  71. #define RUC_ABORT 0x0004
  72. #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
  73. #define RUC_RESUMENR 0x0007
  74. #define CU_CMD_MASK 0x00f0
  75. #define RU_CMD_MASK 0x0007
  76. #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
  77. #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
  78. #define CU_STATUS_MASK 0x00C0
  79. #define RU_STATUS_MASK 0x003C
  80. #define RU_STATUS_IDLE (0<<2)
  81. #define RU_STATUS_SUS (1<<2)
  82. #define RU_STATUS_NORES (2<<2)
  83. #define RU_STATUS_READY (4<<2)
  84. #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
  85. #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
  86. #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
  87. /* 82559 Port interface commands.
  88. */
  89. #define I82559_RESET 0x00000000 /* Software reset */
  90. #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
  91. #define I82559_SELECTIVE_RESET 0x00000002
  92. #define I82559_DUMP 0x00000003
  93. #define I82559_DUMP_WAKEUP 0x00000007
  94. /* 82559 Eeprom interface.
  95. */
  96. #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
  97. #define EE_CS 0x02 /* EEPROM chip select. */
  98. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  99. #define EE_WRITE_0 0x01
  100. #define EE_WRITE_1 0x05
  101. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  102. #define EE_ENB (0x4800 | EE_CS)
  103. #define EE_CMD_BITS 3
  104. #define EE_DATA_BITS 16
  105. /* The EEPROM commands include the alway-set leading bit.
  106. */
  107. #define EE_EWENB_CMD (4 << addr_len)
  108. #define EE_WRITE_CMD (5 << addr_len)
  109. #define EE_READ_CMD (6 << addr_len)
  110. #define EE_ERASE_CMD (7 << addr_len)
  111. /* Receive frame descriptors.
  112. */
  113. struct RxFD {
  114. volatile u16 status;
  115. volatile u16 control;
  116. volatile u32 link; /* struct RxFD * */
  117. volatile u32 rx_buf_addr; /* void * */
  118. volatile u32 count;
  119. volatile u8 data[PKTSIZE_ALIGN];
  120. };
  121. #define RFD_STATUS_C 0x8000 /* completion of received frame */
  122. #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
  123. #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
  124. #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
  125. #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
  126. #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
  127. #define RFD_COUNT_MASK 0x3fff
  128. #define RFD_COUNT_F 0x4000
  129. #define RFD_COUNT_EOF 0x8000
  130. #define RFD_RX_CRC 0x0800 /* crc error */
  131. #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
  132. #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
  133. #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
  134. #define RFD_RX_SHORT 0x0080 /* short frame error */
  135. #define RFD_RX_LENGTH 0x0020
  136. #define RFD_RX_ERROR 0x0010 /* receive error */
  137. #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
  138. #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
  139. #define RFD_RX_TCO 0x0001 /* TCO indication */
  140. /* Transmit frame descriptors
  141. */
  142. struct TxFD { /* Transmit frame descriptor set. */
  143. volatile u16 status;
  144. volatile u16 command;
  145. volatile u32 link; /* void * */
  146. volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
  147. volatile s32 count;
  148. volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
  149. volatile s32 tx_buf_size0; /* Length of Tx frame. */
  150. volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
  151. volatile s32 tx_buf_size1; /* Length of Tx frame. */
  152. };
  153. #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
  154. #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
  155. #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
  156. #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
  157. #define TxCB_CMD_S 0x4000 /* suspend on completion */
  158. #define TxCB_CMD_EL 0x8000 /* last command block in CBL */
  159. #define TxCB_COUNT_MASK 0x3fff
  160. #define TxCB_COUNT_EOF 0x8000
  161. /* The Speedo3 Rx and Tx frame/buffer descriptors.
  162. */
  163. struct descriptor { /* A generic descriptor. */
  164. volatile u16 status;
  165. volatile u16 command;
  166. volatile u32 link; /* struct descriptor * */
  167. unsigned char params[0];
  168. };
  169. #define CFG_CMD_EL 0x8000
  170. #define CFG_CMD_SUSPEND 0x4000
  171. #define CFG_CMD_INT 0x2000
  172. #define CFG_CMD_IAS 0x0001 /* individual address setup */
  173. #define CFG_CMD_CONFIGURE 0x0002 /* configure */
  174. #define CFG_STATUS_C 0x8000
  175. #define CFG_STATUS_OK 0x2000
  176. /* Misc.
  177. */
  178. #define NUM_RX_DESC PKTBUFSRX
  179. #define NUM_TX_DESC 1 /* Number of TX descriptors */
  180. #define TOUT_LOOP 1000000
  181. #define ETH_ALEN 6
  182. static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
  183. static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
  184. static int rx_next; /* RX descriptor ring pointer */
  185. static int tx_next; /* TX descriptor ring pointer */
  186. static int tx_threshold;
  187. /*
  188. * The parameters for a CmdConfigure operation.
  189. * There are so many options that it would be difficult to document
  190. * each bit. We mostly use the default or recommended settings.
  191. */
  192. static const char i82557_config_cmd[] = {
  193. 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
  194. 0, 0x2E, 0, 0x60, 0,
  195. 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
  196. 0x3f, 0x05,
  197. };
  198. static const char i82558_config_cmd[] = {
  199. 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
  200. 0, 0x2E, 0, 0x60, 0x08, 0x88,
  201. 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
  202. 0x31, 0x05,
  203. };
  204. static void init_rx_ring (struct eth_device *dev);
  205. static void purge_tx_ring (struct eth_device *dev);
  206. static void read_hw_addr (struct eth_device *dev, bd_t * bis);
  207. static int eepro100_init (struct eth_device *dev, bd_t * bis);
  208. static int eepro100_send (struct eth_device *dev, volatile void *packet,
  209. int length);
  210. static int eepro100_recv (struct eth_device *dev);
  211. static void eepro100_halt (struct eth_device *dev);
  212. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
  213. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  214. static inline int INW (struct eth_device *dev, u_long addr)
  215. {
  216. return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
  217. }
  218. static inline void OUTW (struct eth_device *dev, int command, u_long addr)
  219. {
  220. *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
  221. }
  222. static inline void OUTL (struct eth_device *dev, int command, u_long addr)
  223. {
  224. *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
  225. }
  226. /* Wait for the chip get the command.
  227. */
  228. static int wait_for_eepro100 (struct eth_device *dev)
  229. {
  230. int i;
  231. for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
  232. if (i >= TOUT_LOOP) {
  233. return 0;
  234. }
  235. }
  236. return 1;
  237. }
  238. static struct pci_device_id supported[] = {
  239. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
  240. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
  241. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
  242. {}
  243. };
  244. int eepro100_initialize (bd_t * bis)
  245. {
  246. pci_dev_t devno;
  247. int card_number = 0;
  248. struct eth_device *dev;
  249. u32 iobase, status;
  250. int idx = 0;
  251. while (1) {
  252. /* Find PCI device
  253. */
  254. if ((devno = pci_find_devices (supported, idx++)) < 0) {
  255. break;
  256. }
  257. pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
  258. iobase &= ~0xf;
  259. #ifdef DEBUG
  260. printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
  261. iobase);
  262. #endif
  263. pci_write_config_dword (devno,
  264. PCI_COMMAND,
  265. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  266. /* Check if I/O accesses and Bus Mastering are enabled.
  267. */
  268. pci_read_config_dword (devno, PCI_COMMAND, &status);
  269. if (!(status & PCI_COMMAND_MEMORY)) {
  270. printf ("Error: Can not enable MEM access.\n");
  271. continue;
  272. }
  273. if (!(status & PCI_COMMAND_MASTER)) {
  274. printf ("Error: Can not enable Bus Mastering.\n");
  275. continue;
  276. }
  277. dev = (struct eth_device *) malloc (sizeof *dev);
  278. sprintf (dev->name, "i82559#%d", card_number);
  279. dev->iobase = bus_to_phys (iobase);
  280. dev->priv = (void *) devno;
  281. dev->init = eepro100_init;
  282. dev->halt = eepro100_halt;
  283. dev->send = eepro100_send;
  284. dev->recv = eepro100_recv;
  285. eth_register (dev);
  286. card_number++;
  287. /* Set the latency timer for value.
  288. */
  289. pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
  290. udelay (10 * 1000);
  291. read_hw_addr (dev, bis);
  292. }
  293. return card_number;
  294. }
  295. static int eepro100_init (struct eth_device *dev, bd_t * bis)
  296. {
  297. int i, status = 0;
  298. int tx_cur;
  299. struct descriptor *ias_cmd, *cfg_cmd;
  300. /* Reset the ethernet controller
  301. */
  302. OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
  303. udelay (20);
  304. OUTL (dev, I82559_RESET, SCBPort);
  305. udelay (20);
  306. if (!wait_for_eepro100 (dev)) {
  307. printf ("Error: Can not reset ethernet controller.\n");
  308. goto Done;
  309. }
  310. OUTL (dev, 0, SCBPointer);
  311. OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
  312. if (!wait_for_eepro100 (dev)) {
  313. printf ("Error: Can not reset ethernet controller.\n");
  314. goto Done;
  315. }
  316. OUTL (dev, 0, SCBPointer);
  317. OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
  318. /* Initialize Rx and Tx rings.
  319. */
  320. init_rx_ring (dev);
  321. purge_tx_ring (dev);
  322. /* Tell the adapter where the RX ring is located.
  323. */
  324. if (!wait_for_eepro100 (dev)) {
  325. printf ("Error: Can not reset ethernet controller.\n");
  326. goto Done;
  327. }
  328. OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
  329. OUTW (dev, SCB_M | RUC_START, SCBCmd);
  330. /* Send the Configure frame */
  331. tx_cur = tx_next;
  332. tx_next = ((tx_next + 1) % NUM_TX_DESC);
  333. cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
  334. cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
  335. cfg_cmd->status = 0;
  336. cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  337. memcpy (cfg_cmd->params, i82558_config_cmd,
  338. sizeof (i82558_config_cmd));
  339. if (!wait_for_eepro100 (dev)) {
  340. printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n");
  341. goto Done;
  342. }
  343. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  344. OUTW (dev, SCB_M | CU_START, SCBCmd);
  345. for (i = 0;
  346. !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
  347. i++) {
  348. if (i >= TOUT_LOOP) {
  349. printf ("%s: Tx error buffer not ready\n", dev->name);
  350. goto Done;
  351. }
  352. }
  353. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
  354. printf ("TX error status = 0x%08X\n",
  355. le16_to_cpu (tx_ring[tx_cur].status));
  356. goto Done;
  357. }
  358. /* Send the Individual Address Setup frame
  359. */
  360. tx_cur = tx_next;
  361. tx_next = ((tx_next + 1) % NUM_TX_DESC);
  362. ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
  363. ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS));
  364. ias_cmd->status = 0;
  365. ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  366. memcpy (ias_cmd->params, dev->enetaddr, 6);
  367. /* Tell the adapter where the TX ring is located.
  368. */
  369. if (!wait_for_eepro100 (dev)) {
  370. printf ("Error: Can not reset ethernet controller.\n");
  371. goto Done;
  372. }
  373. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  374. OUTW (dev, SCB_M | CU_START, SCBCmd);
  375. for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
  376. i++) {
  377. if (i >= TOUT_LOOP) {
  378. printf ("%s: Tx error buffer not ready\n",
  379. dev->name);
  380. goto Done;
  381. }
  382. }
  383. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
  384. printf ("TX error status = 0x%08X\n",
  385. le16_to_cpu (tx_ring[tx_cur].status));
  386. goto Done;
  387. }
  388. status = 1;
  389. Done:
  390. return status;
  391. }
  392. static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
  393. {
  394. int i, status = -1;
  395. int tx_cur;
  396. if (length <= 0) {
  397. printf ("%s: bad packet size: %d\n", dev->name, length);
  398. goto Done;
  399. }
  400. tx_cur = tx_next;
  401. tx_next = (tx_next + 1) % NUM_TX_DESC;
  402. tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
  403. TxCB_CMD_SF |
  404. TxCB_CMD_S |
  405. TxCB_CMD_EL );
  406. tx_ring[tx_cur].status = 0;
  407. tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
  408. tx_ring[tx_cur].link =
  409. cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  410. tx_ring[tx_cur].tx_desc_addr =
  411. cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
  412. tx_ring[tx_cur].tx_buf_addr0 =
  413. cpu_to_le32 (phys_to_bus ((u_long) packet));
  414. tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
  415. if (!wait_for_eepro100 (dev)) {
  416. printf ("%s: Tx error ethernet controller not ready.\n",
  417. dev->name);
  418. goto Done;
  419. }
  420. /* Send the packet.
  421. */
  422. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  423. OUTW (dev, SCB_M | CU_START, SCBCmd);
  424. for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
  425. i++) {
  426. if (i >= TOUT_LOOP) {
  427. printf ("%s: Tx error buffer not ready\n", dev->name);
  428. goto Done;
  429. }
  430. }
  431. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
  432. printf ("TX error status = 0x%08X\n",
  433. le16_to_cpu (tx_ring[tx_cur].status));
  434. goto Done;
  435. }
  436. status = length;
  437. Done:
  438. return status;
  439. }
  440. static int eepro100_recv (struct eth_device *dev)
  441. {
  442. u16 status, stat;
  443. int rx_prev, length = 0;
  444. stat = INW (dev, SCBStatus);
  445. OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
  446. for (;;) {
  447. status = le16_to_cpu (rx_ring[rx_next].status);
  448. if (!(status & RFD_STATUS_C)) {
  449. break;
  450. }
  451. /* Valid frame status.
  452. */
  453. if ((status & RFD_STATUS_OK)) {
  454. /* A valid frame received.
  455. */
  456. length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
  457. /* Pass the packet up to the protocol
  458. * layers.
  459. */
  460. NetReceive (rx_ring[rx_next].data, length);
  461. } else {
  462. /* There was an error.
  463. */
  464. printf ("RX error status = 0x%08X\n", status);
  465. }
  466. rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
  467. rx_ring[rx_next].status = 0;
  468. rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
  469. rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
  470. rx_ring[rx_prev].control = 0;
  471. /* Update entry information.
  472. */
  473. rx_next = (rx_next + 1) % NUM_RX_DESC;
  474. }
  475. if (stat & SCB_STATUS_RNR) {
  476. printf ("%s: Receiver is not ready, restart it !\n", dev->name);
  477. /* Reinitialize Rx ring.
  478. */
  479. init_rx_ring (dev);
  480. if (!wait_for_eepro100 (dev)) {
  481. printf ("Error: Can not restart ethernet controller.\n");
  482. goto Done;
  483. }
  484. OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
  485. OUTW (dev, SCB_M | RUC_START, SCBCmd);
  486. }
  487. Done:
  488. return length;
  489. }
  490. static void eepro100_halt (struct eth_device *dev)
  491. {
  492. /* Reset the ethernet controller
  493. */
  494. OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
  495. udelay (20);
  496. OUTL (dev, I82559_RESET, SCBPort);
  497. udelay (20);
  498. if (!wait_for_eepro100 (dev)) {
  499. printf ("Error: Can not reset ethernet controller.\n");
  500. goto Done;
  501. }
  502. OUTL (dev, 0, SCBPointer);
  503. OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
  504. if (!wait_for_eepro100 (dev)) {
  505. printf ("Error: Can not reset ethernet controller.\n");
  506. goto Done;
  507. }
  508. OUTL (dev, 0, SCBPointer);
  509. OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
  510. Done:
  511. return;
  512. }
  513. /* SROM Read.
  514. */
  515. static int read_eeprom (struct eth_device *dev, int location, int addr_len)
  516. {
  517. unsigned short retval = 0;
  518. int read_cmd = location | EE_READ_CMD;
  519. int i;
  520. OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
  521. OUTW (dev, EE_ENB, SCBeeprom);
  522. /* Shift the read command bits out. */
  523. for (i = 12; i >= 0; i--) {
  524. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  525. OUTW (dev, EE_ENB | dataval, SCBeeprom);
  526. udelay (1);
  527. OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  528. udelay (1);
  529. }
  530. OUTW (dev, EE_ENB, SCBeeprom);
  531. for (i = 15; i >= 0; i--) {
  532. OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
  533. udelay (1);
  534. retval = (retval << 1) |
  535. ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
  536. OUTW (dev, EE_ENB, SCBeeprom);
  537. udelay (1);
  538. }
  539. /* Terminate the EEPROM access. */
  540. OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
  541. return retval;
  542. }
  543. #ifdef CONFIG_EEPRO100_SROM_WRITE
  544. int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
  545. {
  546. unsigned short dataval;
  547. int enable_cmd = 0x3f | EE_EWENB_CMD;
  548. int write_cmd = location | EE_WRITE_CMD;
  549. int i;
  550. unsigned long datalong, tmplong;
  551. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  552. udelay(1);
  553. OUTW(dev, EE_ENB, SCBeeprom);
  554. /* Shift the enable command bits out. */
  555. for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
  556. {
  557. dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  558. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  559. udelay(1);
  560. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  561. udelay(1);
  562. }
  563. OUTW(dev, EE_ENB, SCBeeprom);
  564. udelay(1);
  565. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  566. udelay(1);
  567. OUTW(dev, EE_ENB, SCBeeprom);
  568. /* Shift the write command bits out. */
  569. for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
  570. {
  571. dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  572. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  573. udelay(1);
  574. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  575. udelay(1);
  576. }
  577. /* Write the data */
  578. datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
  579. for (i = 0; i< EE_DATA_BITS; i++)
  580. {
  581. /* Extract and move data bit to bit DI */
  582. dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
  583. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  584. udelay(1);
  585. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  586. udelay(1);
  587. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  588. udelay(1);
  589. datalong = datalong << 1; /* Adjust significant data bit*/
  590. }
  591. /* Finish up command (toggle CS) */
  592. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  593. udelay(1); /* delay for more than 250 ns */
  594. OUTW(dev, EE_ENB, SCBeeprom);
  595. /* Wait for programming ready (D0 = 1) */
  596. tmplong = 10;
  597. do
  598. {
  599. dataval = INW(dev, SCBeeprom);
  600. if (dataval & EE_DATA_READ)
  601. break;
  602. udelay(10000);
  603. }
  604. while (-- tmplong);
  605. if (tmplong == 0)
  606. {
  607. printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
  608. return -1;
  609. }
  610. /* Terminate the EEPROM access. */
  611. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  612. return 0;
  613. }
  614. #endif
  615. static void init_rx_ring (struct eth_device *dev)
  616. {
  617. int i;
  618. for (i = 0; i < NUM_RX_DESC; i++) {
  619. rx_ring[i].status = 0;
  620. rx_ring[i].control =
  621. (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
  622. rx_ring[i].link =
  623. cpu_to_le32 (phys_to_bus
  624. ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
  625. rx_ring[i].rx_buf_addr = 0xffffffff;
  626. rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
  627. }
  628. rx_next = 0;
  629. }
  630. static void purge_tx_ring (struct eth_device *dev)
  631. {
  632. int i;
  633. tx_next = 0;
  634. tx_threshold = 0x01208000;
  635. for (i = 0; i < NUM_TX_DESC; i++) {
  636. tx_ring[i].status = 0;
  637. tx_ring[i].command = 0;
  638. tx_ring[i].link = 0;
  639. tx_ring[i].tx_desc_addr = 0;
  640. tx_ring[i].count = 0;
  641. tx_ring[i].tx_buf_addr0 = 0;
  642. tx_ring[i].tx_buf_size0 = 0;
  643. tx_ring[i].tx_buf_addr1 = 0;
  644. tx_ring[i].tx_buf_size1 = 0;
  645. }
  646. }
  647. static void read_hw_addr (struct eth_device *dev, bd_t * bis)
  648. {
  649. u16 eeprom[0x40];
  650. u16 sum = 0;
  651. int i, j;
  652. int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
  653. for (j = 0, i = 0; i < 0x40; i++) {
  654. u16 value = read_eeprom (dev, i, addr_len);
  655. eeprom[i] = value;
  656. sum += value;
  657. if (i < 3) {
  658. dev->enetaddr[j++] = value;
  659. dev->enetaddr[j++] = value >> 8;
  660. }
  661. }
  662. if (sum != 0xBABA) {
  663. memset (dev->enetaddr, 0, ETH_ALEN);
  664. #ifdef DEBUG
  665. printf ("%s: Invalid EEPROM checksum %#4.4x, "
  666. "check settings before activating this device!\n",
  667. dev->name, sum);
  668. #endif
  669. }
  670. }
  671. #endif