cpu.c 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239
  1. /*
  2. * (C) Copyright 2001
  3. * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * cpu.c
  25. *
  26. * CPU specific code
  27. *
  28. * written or collected and sometimes rewritten by
  29. * Magnus Damm <damm@bitsmart.com>
  30. *
  31. * minor modifications by
  32. * Wolfgang Denk <wd@denx.de>
  33. *
  34. * more modifications by
  35. * Josh Huber <huber@mclx.com>
  36. * added support for the 74xx series of cpus
  37. * added support for the 7xx series of cpus
  38. * made the code a little less hard-coded, and more auto-detectish
  39. */
  40. #include <common.h>
  41. #include <command.h>
  42. #include <74xx_7xx.h>
  43. #include <asm/cache.h>
  44. cpu_t
  45. get_cpu_type(void)
  46. {
  47. uint pvr = get_pvr();
  48. cpu_t type;
  49. type = CPU_UNKNOWN;
  50. switch (PVR_VER(pvr)) {
  51. case 0x000c:
  52. type = CPU_7400;
  53. break;
  54. case 0x0008:
  55. type = CPU_750;
  56. if (((pvr >> 8) & 0xff) == 0x01) {
  57. type = CPU_750CX; /* old CX (80100 and 8010x?)*/
  58. } else if (((pvr >> 8) & 0xff) == 0x22) {
  59. type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */
  60. } else if (((pvr >> 8) & 0xff) == 0x33) {
  61. type = CPU_750CX; /* CXe (83311) */
  62. } else if (((pvr >> 12) & 0xF) == 0x3) {
  63. type = CPU_755;
  64. }
  65. break;
  66. case 0x800C:
  67. type = CPU_7410;
  68. break;
  69. case 0x8000:
  70. type = CPU_7450;
  71. break;
  72. default:
  73. break;
  74. }
  75. return type;
  76. }
  77. /* ------------------------------------------------------------------------- */
  78. #if !defined(CONFIG_BAB7xx)
  79. int checkcpu (void)
  80. {
  81. DECLARE_GLOBAL_DATA_PTR;
  82. uint type = get_cpu_type();
  83. uint pvr = get_pvr();
  84. ulong clock = gd->cpu_clk;
  85. char buf[32];
  86. char *str;
  87. puts ("CPU: ");
  88. switch (type) {
  89. case CPU_750CX:
  90. printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"",
  91. (pvr>>8) & 0xf,
  92. pvr & 0xf);
  93. goto PR_CLK;
  94. case CPU_750:
  95. str = "750";
  96. break;
  97. case CPU_755:
  98. str = "755";
  99. break;
  100. case CPU_7400:
  101. str = "MPC7400";
  102. break;
  103. case CPU_7410:
  104. str = "MPC7410";
  105. break;
  106. case CPU_7450:
  107. str = "MPC7450";
  108. break;
  109. default:
  110. printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
  111. return -1;
  112. }
  113. printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF);
  114. PR_CLK:
  115. printf (" @ %s MHz\n", strmhz(buf, clock));
  116. return (0);
  117. }
  118. #endif
  119. /* these two functions are unimplemented currently [josh] */
  120. /* ------------------------------------------------------------------------- */
  121. /* L1 i-cache */
  122. int
  123. checkicache(void)
  124. {
  125. return 0; /* XXX */
  126. }
  127. /* ------------------------------------------------------------------------- */
  128. /* L1 d-cache */
  129. int
  130. checkdcache(void)
  131. {
  132. return 0; /* XXX */
  133. }
  134. /* ------------------------------------------------------------------------- */
  135. static inline void
  136. soft_restart(unsigned long addr)
  137. {
  138. /* SRR0 has system reset vector, SRR1 has default MSR value */
  139. /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
  140. __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
  141. __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
  142. __asm__ __volatile__ ("mtspr 27, 4");
  143. __asm__ __volatile__ ("rfi");
  144. while(1); /* not reached */
  145. }
  146. #if !defined(CONFIG_PCIPPC2) && \
  147. !defined(CONFIG_BAB7xx) && \
  148. !defined(CONFIG_ELPPC)
  149. /* no generic way to do board reset. simply call soft_reset. */
  150. void
  151. do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  152. {
  153. ulong addr;
  154. /* flush and disable I/D cache */
  155. __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
  156. __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
  157. __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
  158. __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
  159. __asm__ __volatile__ ("sync");
  160. __asm__ __volatile__ ("mtspr 1008, 4");
  161. __asm__ __volatile__ ("isync");
  162. __asm__ __volatile__ ("sync");
  163. __asm__ __volatile__ ("mtspr 1008, 5");
  164. __asm__ __volatile__ ("isync");
  165. __asm__ __volatile__ ("sync");
  166. #ifdef CFG_RESET_ADDRESS
  167. addr = CFG_RESET_ADDRESS;
  168. #else
  169. /*
  170. * note: when CFG_MONITOR_BASE points to a RAM address,
  171. * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
  172. * address. Better pick an address known to be invalid on your
  173. * system and assign it to CFG_RESET_ADDRESS.
  174. */
  175. addr = CFG_MONITOR_BASE - sizeof (ulong);
  176. #endif
  177. soft_restart(addr);
  178. while(1); /* not reached */
  179. }
  180. #endif
  181. /* ------------------------------------------------------------------------- */
  182. /*
  183. * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
  184. */
  185. unsigned long
  186. get_tbclk (void)
  187. {
  188. return CFG_BUS_HZ / 4;
  189. }
  190. /* ------------------------------------------------------------------------- */
  191. #if defined(CONFIG_WATCHDOG)
  192. #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
  193. void
  194. watchdog_reset(void)
  195. {
  196. }
  197. #endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
  198. #endif /* CONFIG_WATCHDOG */
  199. /* ------------------------------------------------------------------------- */