cpu.c 10 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Marvell Semiconductor <www.marvell.com>
  4. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <netdev.h>
  10. #include <asm/cache.h>
  11. #include <u-boot/md5.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/kirkwood.h>
  15. #include <hush.h>
  16. #define BUFLEN 16
  17. void reset_cpu(unsigned long ignored)
  18. {
  19. struct kwcpu_registers *cpureg =
  20. (struct kwcpu_registers *)KW_CPU_REG_BASE;
  21. writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  22. &cpureg->rstoutn_mask);
  23. writel(readl(&cpureg->sys_soft_rst) | 1,
  24. &cpureg->sys_soft_rst);
  25. while (1) ;
  26. }
  27. /*
  28. * Generates Ramdom hex number reading some time varient system registers
  29. * and using md5 algorithm
  30. */
  31. unsigned char get_random_hex(void)
  32. {
  33. int i;
  34. u32 inbuf[BUFLEN];
  35. u8 outbuf[BUFLEN];
  36. /*
  37. * in case of 88F6281/88F6282/88F6192 A0,
  38. * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
  39. * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
  40. * reserved regs and does not have names at this moment
  41. * (no errata available)
  42. */
  43. writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
  44. for (i = 0; i < BUFLEN; i++) {
  45. inbuf[i] = readl(KW_REG_UNDOC_0x1470);
  46. }
  47. md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
  48. return outbuf[outbuf[7] % 0x0f];
  49. }
  50. /*
  51. * Window Size
  52. * Used with the Base register to set the address window size and location.
  53. * Must be programmed from LSB to MSB as sequence of ones followed by
  54. * sequence of zeros. The number of ones specifies the size of the window in
  55. * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
  56. * NOTE: A value of 0x0 specifies 64-KByte size.
  57. */
  58. unsigned int kw_winctrl_calcsize(unsigned int sizeval)
  59. {
  60. int i;
  61. unsigned int j = 0;
  62. u32 val = sizeval >> 1;
  63. for (i = 0; val >= 0x10000; i++) {
  64. j |= (1 << i);
  65. val = val >> 1;
  66. }
  67. return (0x0000ffff & j);
  68. }
  69. /*
  70. * kw_config_adr_windows - Configure address Windows
  71. *
  72. * There are 8 address windows supported by Kirkwood Soc to addess different
  73. * devices. Each window can be configured for size, BAR and remap addr
  74. * Below configuration is standard for most of the cases
  75. *
  76. * If remap function not used, remap_lo must be set as base
  77. *
  78. * Reference Documentation:
  79. * Mbus-L to Mbus Bridge Registers Configuration.
  80. * (Sec 25.1 and 25.3 of Datasheet)
  81. */
  82. int kw_config_adr_windows(void)
  83. {
  84. struct kwwin_registers *winregs =
  85. (struct kwwin_registers *)KW_CPU_WIN_BASE;
  86. /* Window 0: PCIE MEM address space */
  87. writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
  88. KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
  89. writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
  90. writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
  91. writel(0x0, &winregs[0].remap_hi);
  92. /* Window 1: PCIE IO address space */
  93. writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
  94. KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
  95. writel(KW_DEFADR_PCI_IO, &winregs[1].base);
  96. writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
  97. writel(0x0, &winregs[1].remap_hi);
  98. /* Window 2: NAND Flash address space */
  99. writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
  100. KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
  101. writel(KW_DEFADR_NANDF, &winregs[2].base);
  102. writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
  103. writel(0x0, &winregs[2].remap_hi);
  104. /* Window 3: SPI Flash address space */
  105. writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
  106. KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
  107. writel(KW_DEFADR_SPIF, &winregs[3].base);
  108. writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
  109. writel(0x0, &winregs[3].remap_hi);
  110. /* Window 4: BOOT Memory address space */
  111. writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
  112. KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
  113. writel(KW_DEFADR_BOOTROM, &winregs[4].base);
  114. /* Window 5: Security SRAM address space */
  115. writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
  116. KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
  117. writel(KW_DEFADR_SASRAM, &winregs[5].base);
  118. /* Window 6-7: Disabled */
  119. writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
  120. writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
  121. return 0;
  122. }
  123. /*
  124. * kw_config_gpio - GPIO configuration
  125. */
  126. void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
  127. {
  128. struct kwgpio_registers *gpio0reg =
  129. (struct kwgpio_registers *)KW_GPIO0_BASE;
  130. struct kwgpio_registers *gpio1reg =
  131. (struct kwgpio_registers *)KW_GPIO1_BASE;
  132. /* Init GPIOS to default values as per board requirement */
  133. writel(gpp0_oe_val, &gpio0reg->dout);
  134. writel(gpp1_oe_val, &gpio1reg->dout);
  135. writel(gpp0_oe, &gpio0reg->oe);
  136. writel(gpp1_oe, &gpio1reg->oe);
  137. }
  138. /*
  139. * kw_config_mpp - Multi-Purpose Pins Functionality configuration
  140. *
  141. * Each MPP can be configured to different functionality through
  142. * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
  143. *
  144. * There are maximum 64 Multi-Pourpose Pins on Kirkwood
  145. * Each MPP functionality can be configuration by a 4bit value
  146. * of MPP control reg, the value and associated functionality depends
  147. * upon used SoC varient
  148. */
  149. int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
  150. u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
  151. {
  152. u32 *mppreg = (u32 *) KW_MPP_BASE;
  153. /* program mpp registers */
  154. writel(mpp0_7, &mppreg[0]);
  155. writel(mpp8_15, &mppreg[1]);
  156. writel(mpp16_23, &mppreg[2]);
  157. writel(mpp24_31, &mppreg[3]);
  158. writel(mpp32_39, &mppreg[4]);
  159. writel(mpp40_47, &mppreg[5]);
  160. writel(mpp48_55, &mppreg[6]);
  161. return 0;
  162. }
  163. /*
  164. * SYSRSTn Duration Counter Support
  165. *
  166. * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
  167. * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
  168. * The SYSRSTn duration counter is useful for implementing a manufacturer
  169. * or factory reset. Upon a long reset assertion that is greater than a
  170. * pre-configured environment variable value for sysrstdelay,
  171. * The counter value is stored in the SYSRSTn Length Counter Register
  172. * The counter is based on the 25-MHz reference clock (40ns)
  173. * It is a 29-bit counter, yielding a maximum counting duration of
  174. * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
  175. * it remains at this value until counter reset is triggered by setting
  176. * bit 31 of KW_REG_SYSRST_CNT
  177. */
  178. static void kw_sysrst_action(void)
  179. {
  180. int ret;
  181. char *s = getenv("sysrstcmd");
  182. if (!s) {
  183. debug("Error.. %s failed, check sysrstcmd\n",
  184. __FUNCTION__);
  185. return;
  186. }
  187. debug("Starting %s process...\n", __FUNCTION__);
  188. ret = run_command(s, 0);
  189. if (ret < 0)
  190. debug("Error.. %s failed\n", __FUNCTION__);
  191. else
  192. debug("%s process finished\n", __FUNCTION__);
  193. }
  194. static void kw_sysrst_check(void)
  195. {
  196. u32 sysrst_cnt, sysrst_dly;
  197. char *s;
  198. /*
  199. * no action if sysrstdelay environment variable is not defined
  200. */
  201. s = getenv("sysrstdelay");
  202. if (s == NULL)
  203. return;
  204. /* read sysrstdelay value */
  205. sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
  206. /* read SysRst Length counter register (bits 28:0) */
  207. sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
  208. debug("H/w Rst hold time: %d.%d secs\n",
  209. sysrst_cnt / SYSRST_CNT_1SEC_VAL,
  210. sysrst_cnt % SYSRST_CNT_1SEC_VAL);
  211. /* clear the counter for next valid read*/
  212. writel(1 << 31, KW_REG_SYSRST_CNT);
  213. /*
  214. * sysrst_action:
  215. * if H/w Reset key is pressed and hold for time
  216. * more than sysrst_dly in seconds
  217. */
  218. if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
  219. kw_sysrst_action();
  220. }
  221. #if defined(CONFIG_DISPLAY_CPUINFO)
  222. int print_cpuinfo(void)
  223. {
  224. char *rev;
  225. u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
  226. u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
  227. if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
  228. printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
  229. return -1;
  230. }
  231. switch (revid) {
  232. case 0:
  233. rev = "Z0";
  234. break;
  235. case 2:
  236. rev = "A0";
  237. break;
  238. case 3:
  239. rev = "A1";
  240. break;
  241. default:
  242. rev = "??";
  243. break;
  244. }
  245. printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
  246. return 0;
  247. }
  248. #endif /* CONFIG_DISPLAY_CPUINFO */
  249. #ifdef CONFIG_ARCH_CPU_INIT
  250. int arch_cpu_init(void)
  251. {
  252. u32 reg;
  253. struct kwcpu_registers *cpureg =
  254. (struct kwcpu_registers *)KW_CPU_REG_BASE;
  255. /* Linux expects` the internal registers to be at 0xf1000000 */
  256. writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
  257. /* Enable and invalidate L2 cache in write through mode */
  258. writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
  259. invalidate_l2_cache();
  260. kw_config_adr_windows();
  261. #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
  262. /*
  263. * Configures the I/O voltage of the pads connected to Egigabit
  264. * Ethernet interface to 1.8V
  265. * By default it is set to 3.3V
  266. */
  267. reg = readl(KW_REG_MPP_OUT_DRV_REG);
  268. reg |= (1 << 7);
  269. writel(reg, KW_REG_MPP_OUT_DRV_REG);
  270. #endif
  271. #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
  272. /*
  273. * Set egiga port0/1 in normal functional mode
  274. * This is required becasue on kirkwood by default ports are in reset mode
  275. * OS egiga driver may not have provision to set them in normal mode
  276. * and if u-boot is build without network support, network may fail at OS level
  277. */
  278. reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
  279. reg &= ~(1 << 4); /* Clear PortReset Bit */
  280. writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
  281. reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
  282. reg &= ~(1 << 4); /* Clear PortReset Bit */
  283. writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
  284. #endif
  285. #ifdef CONFIG_KIRKWOOD_PCIE_INIT
  286. /*
  287. * Enable PCI Express Port0
  288. */
  289. reg = readl(&cpureg->ctrl_stat);
  290. reg |= (1 << 0); /* Set PEX0En Bit */
  291. writel(reg, &cpureg->ctrl_stat);
  292. #endif
  293. return 0;
  294. }
  295. #endif /* CONFIG_ARCH_CPU_INIT */
  296. /*
  297. * SOC specific misc init
  298. */
  299. #if defined(CONFIG_ARCH_MISC_INIT)
  300. int arch_misc_init(void)
  301. {
  302. volatile u32 temp;
  303. /*CPU streaming & write allocate */
  304. temp = readfr_extra_feature_reg();
  305. temp &= ~(1 << 28); /* disable wr alloc */
  306. writefr_extra_feature_reg(temp);
  307. temp = readfr_extra_feature_reg();
  308. temp &= ~(1 << 29); /* streaming disabled */
  309. writefr_extra_feature_reg(temp);
  310. /* L2Cache settings */
  311. temp = readfr_extra_feature_reg();
  312. /* Disable L2C pre fetch - Set bit 24 */
  313. temp |= (1 << 24);
  314. /* enable L2C - Set bit 22 */
  315. temp |= (1 << 22);
  316. writefr_extra_feature_reg(temp);
  317. icache_enable();
  318. /* Change reset vector to address 0x0 */
  319. temp = get_cr();
  320. set_cr(temp & ~CR_V);
  321. /* checks and execute resset to factory event */
  322. kw_sysrst_check();
  323. return 0;
  324. }
  325. #endif /* CONFIG_ARCH_MISC_INIT */
  326. #ifdef CONFIG_MVGBE
  327. int cpu_eth_init(bd_t *bis)
  328. {
  329. mvgbe_initialize(bis);
  330. return 0;
  331. }
  332. #endif