sun8i-v3s.dtsi 8.5 KB

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  1. /*
  2. * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. #include <dt-bindings/clock/sun8i-v3s-ccu.h>
  43. #include <dt-bindings/reset/sun8i-v3s-ccu.h>
  44. #include <dt-bindings/interrupt-controller/arm-gic.h>
  45. #include <dt-bindings/pinctrl/sun4i-a10.h>
  46. / {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. interrupt-parent = <&gic>;
  50. cpus {
  51. #address-cells = <1>;
  52. #size-cells = <0>;
  53. cpu@0 {
  54. compatible = "arm,cortex-a7";
  55. device_type = "cpu";
  56. reg = <0>;
  57. clocks = <&ccu CLK_CPU>;
  58. };
  59. };
  60. timer {
  61. compatible = "arm,armv7-timer";
  62. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  63. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  64. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  65. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  66. };
  67. clocks {
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. ranges;
  71. osc24M: osc24M_clk {
  72. #clock-cells = <0>;
  73. compatible = "fixed-clock";
  74. clock-frequency = <24000000>;
  75. clock-output-names = "osc24M";
  76. };
  77. osc32k: osc32k_clk {
  78. #clock-cells = <0>;
  79. compatible = "fixed-clock";
  80. clock-frequency = <32768>;
  81. clock-output-names = "osc32k";
  82. };
  83. };
  84. soc {
  85. compatible = "simple-bus";
  86. #address-cells = <1>;
  87. #size-cells = <1>;
  88. ranges;
  89. mmc0: mmc@01c0f000 {
  90. compatible = "allwinner,sun7i-a20-mmc";
  91. reg = <0x01c0f000 0x1000>;
  92. clocks = <&ccu CLK_BUS_MMC0>,
  93. <&ccu CLK_MMC0>,
  94. <&ccu CLK_MMC0_OUTPUT>,
  95. <&ccu CLK_MMC0_SAMPLE>;
  96. clock-names = "ahb",
  97. "mmc",
  98. "output",
  99. "sample";
  100. resets = <&ccu RST_BUS_MMC0>;
  101. reset-names = "ahb";
  102. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  103. status = "disabled";
  104. #address-cells = <1>;
  105. #size-cells = <0>;
  106. };
  107. mmc1: mmc@01c10000 {
  108. compatible = "allwinner,sun7i-a20-mmc";
  109. reg = <0x01c10000 0x1000>;
  110. clocks = <&ccu CLK_BUS_MMC1>,
  111. <&ccu CLK_MMC1>,
  112. <&ccu CLK_MMC1_OUTPUT>,
  113. <&ccu CLK_MMC1_SAMPLE>;
  114. clock-names = "ahb",
  115. "mmc",
  116. "output",
  117. "sample";
  118. resets = <&ccu RST_BUS_MMC1>;
  119. reset-names = "ahb";
  120. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  121. status = "disabled";
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. };
  125. mmc2: mmc@01c11000 {
  126. compatible = "allwinner,sun7i-a20-mmc";
  127. reg = <0x01c11000 0x1000>;
  128. clocks = <&ccu CLK_BUS_MMC2>,
  129. <&ccu CLK_MMC2>,
  130. <&ccu CLK_MMC2_OUTPUT>,
  131. <&ccu CLK_MMC2_SAMPLE>;
  132. clock-names = "ahb",
  133. "mmc",
  134. "output",
  135. "sample";
  136. resets = <&ccu RST_BUS_MMC2>;
  137. reset-names = "ahb";
  138. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  139. status = "disabled";
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. };
  143. usb_otg: usb@01c19000 {
  144. compatible = "allwinner,sun8i-h3-musb";
  145. reg = <0x01c19000 0x0400>;
  146. clocks = <&ccu CLK_BUS_OTG>;
  147. resets = <&ccu RST_BUS_OTG>;
  148. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  149. interrupt-names = "mc";
  150. phys = <&usbphy 0>;
  151. phy-names = "usb";
  152. extcon = <&usbphy 0>;
  153. status = "disabled";
  154. };
  155. usbphy: phy@01c19400 {
  156. compatible = "allwinner,sun8i-v3s-usb-phy";
  157. reg = <0x01c19400 0x2c>,
  158. <0x01c1a800 0x4>;
  159. reg-names = "phy_ctrl",
  160. "pmu0";
  161. clocks = <&ccu CLK_USB_PHY0>;
  162. clock-names = "usb0_phy";
  163. resets = <&ccu RST_USB_PHY0>;
  164. reset-names = "usb0_reset";
  165. status = "disabled";
  166. #phy-cells = <1>;
  167. };
  168. ccu: clock@01c20000 {
  169. compatible = "allwinner,sun8i-v3s-ccu";
  170. reg = <0x01c20000 0x400>;
  171. clocks = <&osc24M>, <&osc32k>;
  172. clock-names = "hosc", "losc";
  173. #clock-cells = <1>;
  174. #reset-cells = <1>;
  175. };
  176. rtc: rtc@01c20400 {
  177. compatible = "allwinner,sun6i-a31-rtc";
  178. reg = <0x01c20400 0x54>;
  179. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  180. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  181. };
  182. pio: pinctrl@01c20800 {
  183. compatible = "allwinner,sun8i-v3s-pinctrl";
  184. reg = <0x01c20800 0x400>;
  185. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  186. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  187. clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
  188. clock-names = "apb", "hosc", "losc";
  189. gpio-controller;
  190. #gpio-cells = <3>;
  191. interrupt-controller;
  192. #interrupt-cells = <3>;
  193. i2c0_pins: i2c0 {
  194. pins = "PB6", "PB7";
  195. function = "i2c0";
  196. };
  197. uart0_pins_a: uart0@0 {
  198. pins = "PB8", "PB9";
  199. function = "uart0";
  200. bias-pull-up;
  201. };
  202. mmc0_pins_a: mmc0@0 {
  203. pins = "PF0", "PF1", "PF2", "PF3",
  204. "PF4", "PF5";
  205. function = "mmc0";
  206. drive-strength = <30>;
  207. bias-pull-up;
  208. };
  209. };
  210. timer@01c20c00 {
  211. compatible = "allwinner,sun4i-a10-timer";
  212. reg = <0x01c20c00 0xa0>;
  213. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  214. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  215. clocks = <&osc24M>;
  216. };
  217. wdt0: watchdog@01c20ca0 {
  218. compatible = "allwinner,sun6i-a31-wdt";
  219. reg = <0x01c20ca0 0x20>;
  220. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  221. };
  222. uart0: serial@01c28000 {
  223. compatible = "snps,dw-apb-uart";
  224. reg = <0x01c28000 0x400>;
  225. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  226. reg-shift = <2>;
  227. reg-io-width = <4>;
  228. clocks = <&ccu CLK_BUS_UART0>;
  229. resets = <&ccu RST_BUS_UART0>;
  230. status = "disabled";
  231. };
  232. uart1: serial@01c28400 {
  233. compatible = "snps,dw-apb-uart";
  234. reg = <0x01c28400 0x400>;
  235. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  236. reg-shift = <2>;
  237. reg-io-width = <4>;
  238. clocks = <&ccu CLK_BUS_UART1>;
  239. resets = <&ccu RST_BUS_UART1>;
  240. status = "disabled";
  241. };
  242. uart2: serial@01c28800 {
  243. compatible = "snps,dw-apb-uart";
  244. reg = <0x01c28800 0x400>;
  245. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  246. reg-shift = <2>;
  247. reg-io-width = <4>;
  248. clocks = <&ccu CLK_BUS_UART2>;
  249. resets = <&ccu RST_BUS_UART2>;
  250. status = "disabled";
  251. };
  252. i2c0: i2c@01c2ac00 {
  253. compatible = "allwinner,sun6i-a31-i2c";
  254. reg = <0x01c2ac00 0x400>;
  255. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  256. clocks = <&ccu CLK_BUS_I2C0>;
  257. resets = <&ccu RST_BUS_I2C0>;
  258. pinctrl-names = "default";
  259. pinctrl-0 = <&i2c0_pins>;
  260. status = "disabled";
  261. #address-cells = <1>;
  262. #size-cells = <0>;
  263. };
  264. i2c1: i2c@01c2b000 {
  265. compatible = "allwinner,sun6i-a31-i2c";
  266. reg = <0x01c2b000 0x400>;
  267. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  268. clocks = <&ccu CLK_BUS_I2C1>;
  269. resets = <&ccu RST_BUS_I2C1>;
  270. status = "disabled";
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. };
  274. gic: interrupt-controller@01c81000 {
  275. compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  276. reg = <0x01c81000 0x1000>,
  277. <0x01c82000 0x1000>,
  278. <0x01c84000 0x2000>,
  279. <0x01c86000 0x2000>;
  280. interrupt-controller;
  281. #interrupt-cells = <3>;
  282. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  283. };
  284. };
  285. };