cam_enc_4xx.h 16 KB

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  1. /*
  2. * Copyright (C) 2009 Texas Instruments Incorporated
  3. *
  4. * Copyright (C) 2011
  5. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
  12. #define CONFIG_SYS_CONSOLE_INFO_QUIET
  13. /* SoC Configuration */
  14. #define CONFIG_ARM926EJS /* arm926ejs CPU */
  15. #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
  16. #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
  17. #define CONFIG_SYS_HZ 1000
  18. #define CONFIG_SOC_DM365
  19. #define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
  20. #define CONFIG_HOSTNAME cam_enc_4xx
  21. #define CONFIG_BOARD_LATE_INIT
  22. #define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
  23. /* Memory Info */
  24. #define CONFIG_NR_DRAM_BANKS 1
  25. #define PHYS_SDRAM_1 0x80000000
  26. #define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
  27. #define DDR_4BANKS /* 4-bank DDR2 (256MB) */
  28. #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
  29. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  30. /* Serial Driver info: UART0 for console */
  31. #define CONFIG_SYS_NS16550
  32. #define CONFIG_SYS_NS16550_SERIAL
  33. #define CONFIG_SYS_NS16550_REG_SIZE -4
  34. #define CONFIG_SYS_NS16550_COM1 0x01c20000
  35. #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
  36. #define CONFIG_CONS_INDEX 1
  37. #define CONFIG_BAUDRATE 115200
  38. /* Network Configuration */
  39. #define CONFIG_DRIVER_TI_EMAC
  40. #define CONFIG_EMAC_MDIO_PHY_NUM 0
  41. #define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
  42. #define CONFIG_MII
  43. #define CONFIG_BOOTP_DNS
  44. #define CONFIG_BOOTP_DNS2
  45. #define CONFIG_BOOTP_SEND_HOSTNAME
  46. #define CONFIG_NET_RETRY_COUNT 10
  47. #define CONFIG_CMD_MII
  48. #define CONFIG_SYS_DCACHE_OFF
  49. #define CONFIG_RESET_PHY_R
  50. /* I2C */
  51. #define CONFIG_HARD_I2C
  52. #define CONFIG_DRIVER_DAVINCI_I2C
  53. #define CONFIG_SYS_I2C_SPEED 400000
  54. #define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
  55. /* NAND: socketed, two chipselects, normally 2 GBytes */
  56. #define CONFIG_NAND_DAVINCI
  57. #define CONFIG_SYS_NAND_CS 2
  58. #define CONFIG_SYS_NAND_USE_FLASH_BBT
  59. #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  60. #define CONFIG_SYS_NAND_PAGE_2K
  61. #define CONFIG_SYS_NAND_LARGEPAGE
  62. #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
  63. /* socket has two chipselects, nCE0 gated by address BIT(14) */
  64. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  65. /* SPI support */
  66. #define CONFIG_SPI
  67. #define CONFIG_SPI_FLASH
  68. #define CONFIG_SPI_FLASH_STMICRO
  69. #define CONFIG_DAVINCI_SPI
  70. #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
  71. #define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
  72. #define CONFIG_SF_DEFAULT_SPEED 3000000
  73. #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  74. #define CONFIG_CMD_SF
  75. /* SD/MMC */
  76. #define CONFIG_MMC
  77. #define CONFIG_GENERIC_MMC
  78. #define CONFIG_DAVINCI_MMC
  79. #define CONFIG_MMC_MBLOCK
  80. /* U-Boot command configuration */
  81. #include <config_cmd_default.h>
  82. #define CONFIG_CMD_BDI
  83. #undef CONFIG_CMD_FLASH
  84. #undef CONFIG_CMD_FPGA
  85. #undef CONFIG_CMD_SETGETDCR
  86. #define CONFIG_CMD_ASKENV
  87. #define CONFIG_CMD_CACHE
  88. #define CONFIG_CMD_DHCP
  89. #define CONFIG_CMD_I2C
  90. #define CONFIG_CMD_PING
  91. #define CONFIG_CMD_SAVES
  92. #ifdef CONFIG_CMD_BDI
  93. #define CONFIG_CLOCKS
  94. #endif
  95. #ifdef CONFIG_MMC
  96. #define CONFIG_DOS_PARTITION
  97. #define CONFIG_CMD_EXT2
  98. #define CONFIG_CMD_FAT
  99. #define CONFIG_CMD_MMC
  100. #endif
  101. #ifdef CONFIG_NAND_DAVINCI
  102. #define CONFIG_CMD_MTDPARTS
  103. #define CONFIG_MTD_PARTITIONS
  104. #define CONFIG_MTD_DEVICE
  105. #define CONFIG_CMD_NAND
  106. #define CONFIG_CMD_UBI
  107. #define CONFIG_CMD_UBIFS
  108. #define CONFIG_RBTREE
  109. #define CONFIG_LZO
  110. #endif
  111. #define CONFIG_CRC32_VERIFY
  112. #define CONFIG_MX_CYCLIC
  113. /* U-Boot general configuration */
  114. #define CONFIG_BOOTFILE "uImage" /* Boot file name */
  115. #define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
  116. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  117. #define CONFIG_SYS_PBSIZE /* Print buffer size */ \
  118. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  119. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  120. #define CONFIG_SYS_HUSH_PARSER
  121. #define CONFIG_SYS_LONGHELP
  122. #define CONFIG_MENU
  123. #define CONFIG_MENU_SHOW
  124. #define CONFIG_FIT
  125. #define CONFIG_BOARD_IMG_ADDR_R 0x80000000
  126. #ifdef CONFIG_NAND_DAVINCI
  127. #define CONFIG_ENV_SIZE (16 << 10)
  128. #define CONFIG_ENV_IS_IN_NAND
  129. #define CONFIG_ENV_OFFSET 0x180000
  130. #define CONFIG_ENV_RANGE 0x040000
  131. #define CONFIG_ENV_OFFSET_REDUND 0x1c0000
  132. #undef CONFIG_ENV_IS_IN_FLASH
  133. #endif
  134. #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
  135. #define CONFIG_CMD_ENV
  136. #define CONFIG_SYS_MMC_ENV_DEV 0
  137. #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
  138. #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
  139. #define CONFIG_ENV_IS_IN_MMC
  140. #undef CONFIG_ENV_IS_IN_FLASH
  141. #endif
  142. #define CONFIG_BOOTDELAY 3
  143. /*
  144. * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
  145. * Timeout 1 second.
  146. */
  147. #define CONFIG_AIT_TIMER_TIMEOUT 0x186a00
  148. #define CONFIG_CMDLINE_EDITING
  149. #define CONFIG_VERSION_VARIABLE
  150. #define CONFIG_TIMESTAMP
  151. /* U-Boot memory configuration */
  152. #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
  153. #define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
  154. #define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
  155. /* Linux interfacing */
  156. #define CONFIG_CMDLINE_TAG
  157. #define CONFIG_SETUP_MEMORY_TAGS
  158. #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
  159. #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
  160. #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
  161. #define MTDPARTS_DEFAULT \
  162. "mtdparts=" \
  163. "davinci_nand.0:" \
  164. "128k(spl)," \
  165. "384k(UBLheader)," \
  166. "1m(u-boot)," \
  167. "512k(env)," \
  168. "-(ubi)"
  169. #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  170. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  171. /* Defines for SPL */
  172. #define CONFIG_SPL
  173. #define CONFIG_SPL_FRAMEWORK
  174. #define CONFIG_SPL_BOARD_INIT
  175. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  176. #define CONFIG_SPL_NAND_SUPPORT
  177. #define CONFIG_SPL_NAND_BASE
  178. #define CONFIG_SPL_NAND_DRIVERS
  179. #define CONFIG_SPL_NAND_ECC
  180. #define CONFIG_SPL_NAND_SIMPLE
  181. #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  182. #define CONFIG_SPL_SERIAL_SUPPORT
  183. #define CONFIG_SPL_POST_MEM_SUPPORT
  184. #define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
  185. #define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
  186. #define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/
  187. /* Provide at least 16MB spacing between us and the Linux Kernel image */
  188. #define CONFIG_SPL_PAD_TO 12320
  189. #define CONFIG_SPL_MAX_FOOTPRINT 12288
  190. #ifndef CONFIG_SPL_BUILD
  191. #define CONFIG_SYS_TEXT_BASE 0x81080000
  192. #endif
  193. #define CONFIG_SYS_NAND_BASE 0x02000000
  194. #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  195. CONFIG_SYS_NAND_PAGE_SIZE)
  196. #define CONFIG_SYS_NAND_ECCPOS { \
  197. 24, 25, 26, 27, 28, \
  198. 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
  199. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
  200. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
  201. 59, 60, 61, 62, 63 }
  202. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  203. #define CONFIG_SYS_NAND_ECCSIZE 0x200
  204. #define CONFIG_SYS_NAND_ECCBYTES 10
  205. #define CONFIG_SYS_NAND_OOBSIZE 64
  206. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  207. /*
  208. * RBL searches from Block n (n = 1..24)
  209. * so we can define, how many UBL Headers
  210. * we can write before the real spl code
  211. */
  212. #define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
  213. #define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
  214. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  215. /*
  216. * Post tests for memory testing
  217. */
  218. #define CONFIG_POST CONFIG_SYS_POST_MEMORY
  219. #define _POST_WORD_ADDR 0x0
  220. #define CONFIG_DISPLAY_BOARDINFO
  221. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
  222. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  223. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
  224. #define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE 0x100000
  225. /* for UBL header */
  226. #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
  227. #define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
  228. #define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
  229. #define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
  230. #define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
  231. #define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
  232. #define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
  233. #define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
  234. /* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
  235. #define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
  236. /*
  237. * POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
  238. * interface clk)
  239. */
  240. #define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
  241. /* POST DIV 680/2 = 340Mhz -> VPSS */
  242. #define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
  243. /* POST DIV 680/9 = 75.6 Mhz -> VENC */
  244. #define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
  245. /*
  246. * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
  247. * down to 340 Mhz)
  248. */
  249. #define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
  250. /* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
  251. #define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
  252. /* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
  253. #define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
  254. #define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
  255. /* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
  256. #define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
  257. #define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
  258. /* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
  259. #define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
  260. /* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
  261. #define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
  262. /*
  263. * READ LATENCY 7 (CL + 2)
  264. * CONFIG_PWRDNEN = 1
  265. * CONFIG_EXT_STRBEN = 1
  266. */
  267. #define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
  268. | DV_DDR_PHY_EXT_STRBEN \
  269. | DV_DDR_PHY_PWRDNEN \
  270. | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  271. /*
  272. * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
  273. * T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
  274. * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
  275. * T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
  276. * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
  277. * T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
  278. * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
  279. * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
  280. */
  281. #define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
  282. | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
  283. | (4 << DV_DDR_SDTMR1_RP_SHIFT) \
  284. | (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
  285. | (5 << DV_DDR_SDTMR1_WR_SHIFT) \
  286. | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
  287. | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
  288. | (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
  289. | (2 << DV_DDR_SDTMR1_WTR_SHIFT))
  290. /*
  291. * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
  292. * T_XP = tCKE - 1 = 3 - 2
  293. * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
  294. * T_XSRD = txsrd - 1 = 200 - 1
  295. * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
  296. * T_CKE = tcke - 1 = 3 - 1
  297. */
  298. #define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
  299. | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
  300. | (2 << DV_DDR_SDTMR2_XP_SHIFT) \
  301. | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
  302. | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
  303. | (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
  304. | (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  305. /* PR_OLD_COUNT = 0xfe */
  306. #define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
  307. /* refresh rate = 0x768 */
  308. #define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
  309. #define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
  310. | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
  311. | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
  312. | (5 << DV_DDR_SDCR_CL_SHIFT) \
  313. | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
  314. | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
  315. | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
  316. | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
  317. | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
  318. | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
  319. | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
  320. #define CONFIG_SYS_DM36x_AWCCR 0xff
  321. #define CONFIG_SYS_DM36x_AB1CR 0x40400204
  322. #define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
  323. /* All Video Inputs */
  324. #define CONFIG_SYS_DM36x_PINMUX0 0x00000000
  325. /*
  326. * All Video Outputs,
  327. * GPIO 86, 87 + 90 0x0000f030
  328. */
  329. #define CONFIG_SYS_DM36x_PINMUX1 0x00530002
  330. #define CONFIG_SYS_DM36x_PINMUX2 0x00001815
  331. /*
  332. * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
  333. * GPIO 25 0x60000000
  334. */
  335. #define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
  336. /*
  337. * MMC/SD0 instead of MS, SPI0
  338. * GPIO 34 0x0000c000
  339. */
  340. #define CONFIG_SYS_DM36x_PINMUX4 0x00002655
  341. /*
  342. * Default environment settings
  343. */
  344. #define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
  345. /* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
  346. #define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
  347. /*
  348. * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
  349. * CONFIG_SYS_NAND_PAGE_SIZE))
  350. */
  351. #define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
  352. #define CONFIG_EXTRA_ENV_SETTINGS \
  353. "u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
  354. "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
  355. "load=tftp ${u_boot_addr_r} ${u-boot}\0" \
  356. "pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
  357. "writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \
  358. "nand write ${u_boot_addr_r} 20000 ${pagesz};" \
  359. "nandrbl uboot\0" \
  360. "writenand_spl=nandrbl rbl;nand erase 0 3000;" \
  361. "nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
  362. " 0 3000;nandrbl uboot\0" \
  363. "writeuboot=nandrbl uboot;" \
  364. "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
  365. __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
  366. ";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT) \
  367. " " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
  368. __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
  369. "update=run load writenand_spl writeuboot\0" \
  370. "bootcmd=run net_nfs\0" \
  371. "rootpath=/opt/eldk-arm/arm\0" \
  372. "mtdids=" MTDIDS_DEFAULT "\0" \
  373. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  374. "netdev=eth0\0" \
  375. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  376. "addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0" \
  377. "addcon=setenv bootargs ${bootargs} console=ttyS0," \
  378. "${baudrate}n8\0" \
  379. "addip=setenv bootargs ${bootargs} " \
  380. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  381. ":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0" \
  382. "rootpath=/opt/eldk-arm/arm\0" \
  383. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  384. "nfsroot=${serverip}:${rootpath}\0" \
  385. "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
  386. "kernel_addr_r=80600000\0" \
  387. "load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
  388. "ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \
  389. "ubifsload ${kernel_addr_r} boot/uImage\0" \
  390. "fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
  391. "img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
  392. "img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0" \
  393. "header_addr=20000\0" \
  394. "img_writeheader=nandrbl rbl;" \
  395. "nand erase ${header_addr} ${pagesz};" \
  396. "nand write ${img_addr_r} ${header_addr} ${pagesz};" \
  397. "nandrbl uboot\0" \
  398. "img_writespl=nandrbl rbl;nand erase 0 3000;" \
  399. "nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
  400. "img_writeuboot=nandrbl uboot;" \
  401. "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
  402. __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
  403. ";nand write ${img_addr_r} " \
  404. __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
  405. __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
  406. "img_writedfenv=ubi part ubi 2048;" \
  407. "ubi write ${img_addr_r} default ${filesize}\0" \
  408. "img_volume=rootfs1\0" \
  409. "img_writeramdisk=ubi part ubi 2048;" \
  410. "ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \
  411. "load_img=tftp ${fit_addr_r} ${img_file}\0" \
  412. "net_nfs=run load_kernel; " \
  413. "run nfsargs addip addcon addmtd addmisc;" \
  414. "bootm ${kernel_addr_r}\0" \
  415. "ubi_ubi=run ubi_load_kernel; " \
  416. "run ubiargs addip addcon addmtd addmisc;" \
  417. "bootm ${kernel_addr_r}\0" \
  418. "ubiargs=setenv bootargs ubi.mtd=4,2048" \
  419. " root=ubi0:${img_volume} rw rootfstype=ubifs\0" \
  420. "app_reset=no\0" \
  421. "dvn_app_vers=void\0" \
  422. "dvn_boot_vers=void\0" \
  423. "savenewvers=run savetmpparms restoreparms; saveenv;" \
  424. "run restoretmpparms\0" \
  425. "savetmpparms=setenv y_ipaddr ${ipaddr};" \
  426. "setenv y_netmask ${netmask};" \
  427. "setenv y_serverip ${serverip};" \
  428. "setenv y_gatewayip ${gatewayip}\0" \
  429. "saveparms=setenv x_ipaddr ${ipaddr};" \
  430. "setenv x_netmask ${netmask};" \
  431. "setenv x_serverip ${serverip};" \
  432. "setenv x_gatewayip ${gatewayip}\0" \
  433. "restoreparms=setenv ipaddr ${x_ipaddr};" \
  434. "setenv netmask ${x_netmask};" \
  435. "setenv serverip ${x_serverip};" \
  436. "setenv gatewayip ${x_gatewayip}\0" \
  437. "restoretmpparms=setenv ipaddr ${y_ipaddr};" \
  438. "setenv netmask ${y_netmask};" \
  439. "setenv serverip ${y_serverip};" \
  440. "setenv gatewayip ${y_gatewayip}\0" \
  441. "\0"
  442. /* USB Configuration */
  443. #define CONFIG_USB_DAVINCI
  444. #define CONFIG_MUSB_HCD
  445. #define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
  446. USBPHY_PHY24MHZ)
  447. #define CONFIG_CMD_USB /* include support for usb cmd */
  448. #define CONFIG_USB_STORAGE /* MSC class support */
  449. #define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
  450. #define CONFIG_CMD_FAT /* inclue support for FAT/storage */
  451. #define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
  452. #undef DAVINCI_DM365EVM
  453. #define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
  454. #define PINMUX4_USBDRVBUS_BITSET 0x2000
  455. #endif /* __CONFIG_H */