controlcenterd.h 9.5 KB

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  1. /*
  2. * (C) Copyright 2013
  3. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  4. *
  5. * based on P1022DS.h
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. #include <linux/stringify.h>
  28. #ifdef CONFIG_SDCARD
  29. #define CONFIG_RAMBOOT_SDCARD
  30. #endif
  31. #ifdef CONFIG_SPIFLASH
  32. #define CONFIG_RAMBOOT_SPIFLASH
  33. #endif
  34. /* High Level Configuration Options */
  35. #define CONFIG_CONTROLCENTERD
  36. #define CONFIG_ENABLE_36BIT_PHYS
  37. #ifdef CONFIG_PHYS_64BIT
  38. #define CONFIG_ADDR_MAP
  39. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  40. #endif
  41. #define CONFIG_L2_CACHE
  42. #define CONFIG_BTB
  43. #define CONFIG_SYS_CLK_FREQ 66666600
  44. #define CONFIG_DDR_CLK_FREQ 66666600
  45. #define CONFIG_SYS_RAMBOOT
  46. #ifdef CONFIG_TRAILBLAZER
  47. #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
  48. #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
  49. /*
  50. * Config the L2 Cache
  51. */
  52. #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
  53. #ifdef CONFIG_PHYS_64BIT
  54. #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
  55. #else
  56. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  57. #endif
  58. #define CONFIG_SYS_L2_SIZE (256 << 10)
  59. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  60. #else /* CONFIG_TRAILBLAZER */
  61. #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  62. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  63. #endif /* CONFIG_TRAILBLAZER */
  64. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  65. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  66. /*
  67. * Memory map
  68. *
  69. * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
  70. * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
  71. * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
  72. *
  73. * Localbus non-cacheable
  74. * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
  75. * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
  76. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  77. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  78. */
  79. #define CONFIG_SYS_INIT_RAM_LOCK
  80. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  81. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
  82. #define CONFIG_SYS_GBL_DATA_OFFSET \
  83. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  84. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  85. #ifdef CONFIG_TRAILBLAZER
  86. /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
  87. #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
  88. #else
  89. #define CONFIG_SYS_CCSRBAR 0xffe00000
  90. #endif
  91. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  92. #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
  93. /*
  94. * DDR Setup
  95. */
  96. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  97. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  98. #define CONFIG_SYS_SDRAM_SIZE 1024
  99. #define CONFIG_VERY_BIG_RAM
  100. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  101. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  102. #ifdef CONFIG_TRAILBLAZER
  103. #define CONFIG_SPD_EEPROM
  104. #define SPD_EEPROM_ADDRESS 0x52
  105. /*#define CONFIG_FSL_DDR_INTERACTIVE*/
  106. #endif
  107. /*
  108. * Local Bus Definitions
  109. */
  110. #define CONFIG_SYS_ELBC_BASE 0xe0000000
  111. #ifdef CONFIG_PHYS_64BIT
  112. #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
  113. #else
  114. #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
  115. #endif
  116. #define CONFIG_UART_BR_PRELIM \
  117. (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
  118. #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
  119. #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
  120. #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
  121. #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
  122. #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
  123. /*
  124. * Serial Port
  125. */
  126. #define CONFIG_SYS_NS16550_SERIAL
  127. #define CONFIG_SYS_NS16550_REG_SIZE 1
  128. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  129. #define CONFIG_SYS_BAUDRATE_TABLE \
  130. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  131. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  132. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  133. /*
  134. * I2C
  135. */
  136. #define CONFIG_SYS_I2C
  137. #define CONFIG_SYS_I2C_FSL
  138. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  139. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  140. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  141. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  142. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  143. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  144. #define CONFIG_PCA9698 /* NXP PCA9698 */
  145. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  146. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  147. /*
  148. * MMC
  149. */
  150. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  151. #ifndef CONFIG_TRAILBLAZER
  152. /*
  153. * Video
  154. */
  155. #define CONFIG_FSL_DIU_FB
  156. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
  157. /*
  158. * General PCI
  159. * Memory space is mapped 1-1, but I/O space must start from 0.
  160. */
  161. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  162. #define CONFIG_PCI_INDIRECT_BRIDGE
  163. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  164. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  165. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  166. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  167. #ifdef CONFIG_PHYS_64BIT
  168. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  169. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  170. #else
  171. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  172. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  173. #endif
  174. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  175. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  176. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  177. #ifdef CONFIG_PHYS_64BIT
  178. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  179. #else
  180. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  181. #endif
  182. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  183. /*
  184. * SATA
  185. */
  186. #define CONFIG_LBA48
  187. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  188. #define CONFIG_SATA1
  189. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  190. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  191. #define CONFIG_SATA2
  192. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  193. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  194. /*
  195. * Ethernet
  196. */
  197. #define CONFIG_TSECV2
  198. #define CONFIG_TSEC1 1
  199. #define CONFIG_TSEC1_NAME "eTSEC1"
  200. #define CONFIG_TSEC2 1
  201. #define CONFIG_TSEC2_NAME "eTSEC2"
  202. #define TSEC1_PHY_ADDR 0
  203. #define TSEC2_PHY_ADDR 1
  204. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  205. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  206. #define TSEC1_PHYIDX 0
  207. #define TSEC2_PHYIDX 0
  208. #define CONFIG_ETHPRIME "eTSEC1"
  209. /*
  210. * USB
  211. */
  212. #define CONFIG_HAS_FSL_DR_USB
  213. #define CONFIG_USB_EHCI_FSL
  214. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  215. #endif /* CONFIG_TRAILBLAZER */
  216. /*
  217. * Environment
  218. */
  219. #if defined(CONFIG_TRAILBLAZER)
  220. #elif defined(CONFIG_RAMBOOT_SDCARD)
  221. #define CONFIG_FSL_FIXED_MMC_LOCATION
  222. #define CONFIG_SYS_MMC_ENV_DEV 0
  223. #endif
  224. /*
  225. * Command line configuration.
  226. */
  227. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  228. #ifndef CONFIG_TRAILBLAZER
  229. /*
  230. * Board initialisation callbacks
  231. */
  232. #endif /* CONFIG_TRAILBLAZER */
  233. /*
  234. * Miscellaneous configurable options
  235. */
  236. #define CONFIG_HW_WATCHDOG
  237. #define CONFIG_LOADS_ECHO
  238. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  239. /*
  240. * For booting Linux, the board info and command line data
  241. * have to be in the first 64 MB of memory, since this is
  242. * the maximum mapped by the Linux kernel during initialization.
  243. */
  244. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
  245. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  246. /*
  247. * Environment Configuration
  248. */
  249. #ifdef CONFIG_TRAILBLAZER
  250. #define CONFIG_EXTRA_ENV_SETTINGS \
  251. "mp_holdoff=1\0"
  252. #else
  253. #define CONFIG_HOSTNAME "controlcenterd"
  254. #define CONFIG_ROOTPATH "/opt/nfsroot"
  255. #define CONFIG_BOOTFILE "uImage"
  256. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
  257. #define CONFIG_LOADADDR 1000000
  258. #define CONFIG_EXTRA_ENV_SETTINGS \
  259. "netdev=eth0\0" \
  260. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  261. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  262. "tftpflash=tftpboot $loadaddr $uboot && " \
  263. "protect off $ubootaddr +$filesize && " \
  264. "erase $ubootaddr +$filesize && " \
  265. "cp.b $loadaddr $ubootaddr $filesize && " \
  266. "protect on $ubootaddr +$filesize && " \
  267. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  268. "consoledev=ttyS1\0" \
  269. "ramdiskaddr=2000000\0" \
  270. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  271. "fdtaddr=1e00000\0" \
  272. "fdtfile=controlcenterd.dtb\0" \
  273. "bdev=sda3\0"
  274. /* these are used and NUL-terminated in env_default.h */
  275. #define CONFIG_NFSBOOTCOMMAND \
  276. "setenv bootargs root=/dev/nfs rw " \
  277. "nfsroot=$serverip:$rootpath " \
  278. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  279. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  280. "tftp $loadaddr $bootfile;" \
  281. "tftp $fdtaddr $fdtfile;" \
  282. "bootm $loadaddr - $fdtaddr"
  283. #define CONFIG_RAMBOOTCOMMAND \
  284. "setenv bootargs root=/dev/ram rw " \
  285. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  286. "tftp $ramdiskaddr $ramdiskfile;" \
  287. "tftp $loadaddr $bootfile;" \
  288. "tftp $fdtaddr $fdtfile;" \
  289. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  290. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  291. #endif /* CONFIG_TRAILBLAZER */
  292. #endif