T102xQDS.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * T1024/T1023 QDS board configuration file
  8. */
  9. #ifndef __T1024QDS_H
  10. #define __T1024QDS_H
  11. #include <linux/stringify.h>
  12. /* High Level Configuration Options */
  13. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  14. #define CONFIG_ENABLE_36BIT_PHYS
  15. #ifdef CONFIG_PHYS_64BIT
  16. #define CONFIG_ADDR_MAP 1
  17. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  18. #endif
  19. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  20. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  21. #define CONFIG_ENV_OVERWRITE
  22. #define CONFIG_DEEP_SLEEP
  23. #ifdef CONFIG_RAMBOOT_PBL
  24. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  25. #define CONFIG_SPL_FLUSH_IMAGE
  26. #define CONFIG_SPL_PAD_TO 0x40000
  27. #define CONFIG_SPL_MAX_SIZE 0x28000
  28. #define RESET_VECTOR_OFFSET 0x27FFC
  29. #define BOOT_PAGE_OFFSET 0x27000
  30. #ifdef CONFIG_SPL_BUILD
  31. #define CONFIG_SPL_SKIP_RELOCATE
  32. #define CONFIG_SPL_COMMON_INIT_DDR
  33. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  34. #endif
  35. #ifdef CONFIG_MTD_RAW_NAND
  36. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  37. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  38. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  39. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  40. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  41. #endif
  42. #ifdef CONFIG_SPIFLASH
  43. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  44. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  45. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  46. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  47. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  48. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  49. #ifndef CONFIG_SPL_BUILD
  50. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  51. #endif
  52. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  53. #endif
  54. #ifdef CONFIG_SDCARD
  55. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  56. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  57. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  58. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  59. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  60. #ifndef CONFIG_SPL_BUILD
  61. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  62. #endif
  63. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  64. #endif
  65. #endif /* CONFIG_RAMBOOT_PBL */
  66. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  67. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  68. #endif
  69. /* PCIe Boot - Master */
  70. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  71. /*
  72. * for slave u-boot IMAGE instored in master memory space,
  73. * PHYS must be aligned based on the SIZE
  74. */
  75. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  76. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  77. #ifdef CONFIG_PHYS_64BIT
  78. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  79. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  80. #else
  81. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  82. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  83. #endif
  84. /*
  85. * for slave UCODE and ENV instored in master memory space,
  86. * PHYS must be aligned based on the SIZE
  87. */
  88. #ifdef CONFIG_PHYS_64BIT
  89. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  90. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  91. #else
  92. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  93. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
  94. #endif
  95. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  96. /* slave core release by master*/
  97. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  98. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  99. /* PCIe Boot - Slave */
  100. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  101. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  102. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  103. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  104. /* Set 1M boot space for PCIe boot */
  105. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  106. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  107. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  108. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  109. #endif
  110. #if defined(CONFIG_SPIFLASH)
  111. #elif defined(CONFIG_SDCARD)
  112. #define CONFIG_SYS_MMC_ENV_DEV 0
  113. #endif
  114. #ifndef __ASSEMBLY__
  115. unsigned long get_board_sys_clk(void);
  116. unsigned long get_board_ddr_clk(void);
  117. #endif
  118. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  119. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  120. /*
  121. * These can be toggled for performance analysis, otherwise use default.
  122. */
  123. #define CONFIG_SYS_CACHE_STASHING
  124. #define CONFIG_BACKSIDE_L2_CACHE
  125. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  126. #define CONFIG_BTB /* toggle branch predition */
  127. #define CONFIG_DDR_ECC
  128. #ifdef CONFIG_DDR_ECC
  129. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  130. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  131. #endif
  132. /*
  133. * Config the L3 Cache as L3 SRAM
  134. */
  135. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  136. #define CONFIG_SYS_L3_SIZE (256 << 10)
  137. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  138. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  139. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  140. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  141. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  142. #ifdef CONFIG_PHYS_64BIT
  143. #define CONFIG_SYS_DCSRBAR 0xf0000000
  144. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  145. #endif
  146. /* EEPROM */
  147. #define CONFIG_ID_EEPROM
  148. #define CONFIG_SYS_I2C_EEPROM_NXID
  149. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  150. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  151. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  152. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  153. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  154. /*
  155. * DDR Setup
  156. */
  157. #define CONFIG_VERY_BIG_RAM
  158. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  159. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  160. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  161. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  162. #define CONFIG_DDR_SPD
  163. #define CONFIG_SYS_SPD_BUS_NUM 0
  164. #define SPD_EEPROM_ADDRESS 0x51
  165. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  166. /*
  167. * IFC Definitions
  168. */
  169. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  170. #ifdef CONFIG_PHYS_64BIT
  171. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  172. #else
  173. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  174. #endif
  175. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  176. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  177. + 0x8000000) | \
  178. CSPR_PORT_SIZE_16 | \
  179. CSPR_MSEL_NOR | \
  180. CSPR_V)
  181. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  182. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  183. CSPR_PORT_SIZE_16 | \
  184. CSPR_MSEL_NOR | \
  185. CSPR_V)
  186. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  187. /* NOR Flash Timing Params */
  188. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  189. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  190. FTIM0_NOR_TEADC(0x5) | \
  191. FTIM0_NOR_TEAHC(0x5))
  192. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  193. FTIM1_NOR_TRAD_NOR(0x1A) |\
  194. FTIM1_NOR_TSEQRAD_NOR(0x13))
  195. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  196. FTIM2_NOR_TCH(0x4) | \
  197. FTIM2_NOR_TWPH(0x0E) | \
  198. FTIM2_NOR_TWP(0x1c))
  199. #define CONFIG_SYS_NOR_FTIM3 0x0
  200. #define CONFIG_SYS_FLASH_QUIET_TEST
  201. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  202. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  203. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  204. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  205. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  206. #define CONFIG_SYS_FLASH_EMPTY_INFO
  207. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  208. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  209. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  210. #define QIXIS_BASE 0xffdf0000
  211. #ifdef CONFIG_PHYS_64BIT
  212. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  213. #else
  214. #define QIXIS_BASE_PHYS QIXIS_BASE
  215. #endif
  216. #define QIXIS_LBMAP_SWITCH 0x06
  217. #define QIXIS_LBMAP_MASK 0x0f
  218. #define QIXIS_LBMAP_SHIFT 0
  219. #define QIXIS_LBMAP_DFLTBANK 0x00
  220. #define QIXIS_LBMAP_ALTBANK 0x04
  221. #define QIXIS_RST_CTL_RESET 0x31
  222. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  223. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  224. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  225. #define QIXIS_RST_FORCE_MEM 0x01
  226. #define CONFIG_SYS_CSPR3_EXT (0xf)
  227. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  228. | CSPR_PORT_SIZE_8 \
  229. | CSPR_MSEL_GPCM \
  230. | CSPR_V)
  231. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  232. #define CONFIG_SYS_CSOR3 0x0
  233. /* QIXIS Timing parameters for IFC CS3 */
  234. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  235. FTIM0_GPCM_TEADC(0x0e) | \
  236. FTIM0_GPCM_TEAHC(0x0e))
  237. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  238. FTIM1_GPCM_TRAD(0x3f))
  239. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  240. FTIM2_GPCM_TCH(0x8) | \
  241. FTIM2_GPCM_TWP(0x1f))
  242. #define CONFIG_SYS_CS3_FTIM3 0x0
  243. #define CONFIG_NAND_FSL_IFC
  244. #define CONFIG_SYS_NAND_BASE 0xff800000
  245. #ifdef CONFIG_PHYS_64BIT
  246. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  247. #else
  248. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  249. #endif
  250. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  251. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  252. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  253. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  254. | CSPR_V)
  255. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  256. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  257. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  258. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  259. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  260. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  261. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  262. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  263. #define CONFIG_SYS_NAND_ONFI_DETECTION
  264. /* ONFI NAND Flash mode0 Timing Params */
  265. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  266. FTIM0_NAND_TWP(0x18) | \
  267. FTIM0_NAND_TWCHT(0x07) | \
  268. FTIM0_NAND_TWH(0x0a))
  269. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  270. FTIM1_NAND_TWBE(0x39) | \
  271. FTIM1_NAND_TRR(0x0e) | \
  272. FTIM1_NAND_TRP(0x18))
  273. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  274. FTIM2_NAND_TREH(0x0a) | \
  275. FTIM2_NAND_TWHRE(0x1e))
  276. #define CONFIG_SYS_NAND_FTIM3 0x0
  277. #define CONFIG_SYS_NAND_DDR_LAW 11
  278. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  279. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  280. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  281. #if defined(CONFIG_MTD_RAW_NAND)
  282. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  283. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  284. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  285. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  286. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  287. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  288. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  289. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  290. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  291. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  292. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  293. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  294. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  295. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  296. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  297. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  298. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  299. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  300. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  301. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  302. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  303. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  304. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  305. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  306. #else
  307. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  308. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  309. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  310. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  311. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  312. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  313. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  314. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  315. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  316. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  317. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  318. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  319. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  320. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  321. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  322. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  323. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  324. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  325. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  326. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  327. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  328. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  329. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  330. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  331. #endif
  332. #ifdef CONFIG_SPL_BUILD
  333. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  334. #else
  335. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  336. #endif
  337. #if defined(CONFIG_RAMBOOT_PBL)
  338. #define CONFIG_SYS_RAMBOOT
  339. #endif
  340. #define CONFIG_HWCONFIG
  341. /* define to use L1 as initial stack */
  342. #define CONFIG_L1_INIT_RAM
  343. #define CONFIG_SYS_INIT_RAM_LOCK
  344. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  345. #ifdef CONFIG_PHYS_64BIT
  346. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  347. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  348. /* The assembler doesn't like typecast */
  349. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  350. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  351. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  352. #else
  353. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
  354. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  355. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  356. #endif
  357. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  358. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  359. GENERATED_GBL_DATA_SIZE)
  360. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  361. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  362. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  363. /* Serial Port */
  364. #define CONFIG_SYS_NS16550_SERIAL
  365. #define CONFIG_SYS_NS16550_REG_SIZE 1
  366. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  367. #define CONFIG_SYS_BAUDRATE_TABLE \
  368. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  369. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  370. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  371. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  372. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  373. /* Video */
  374. #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
  375. #define CONFIG_FSL_DIU_FB
  376. #ifdef CONFIG_FSL_DIU_FB
  377. #define CONFIG_FSL_DIU_CH7301
  378. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  379. #define CONFIG_VIDEO_LOGO
  380. #define CONFIG_VIDEO_BMP_LOGO
  381. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  382. /*
  383. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  384. * disable empty flash sector detection, which is I/O-intensive.
  385. */
  386. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  387. #endif
  388. #endif
  389. /* I2C */
  390. #ifndef CONFIG_DM_I2C
  391. #define CONFIG_SYS_I2C
  392. #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
  393. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  394. #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
  395. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  396. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  397. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  398. #else
  399. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  400. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  401. #endif
  402. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  403. #define I2C_MUX_PCA_ADDR 0x77
  404. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  405. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  406. #define I2C_RETIMER_ADDR 0x18
  407. /* I2C bus multiplexer */
  408. #define I2C_MUX_CH_DEFAULT 0x8
  409. #define I2C_MUX_CH_DIU 0xC
  410. #define I2C_MUX_CH5 0xD
  411. #define I2C_MUX_CH7 0xF
  412. /* LDI/DVI Encoder for display */
  413. #define CONFIG_SYS_I2C_LDI_ADDR 0x38
  414. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  415. #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
  416. /*
  417. * RTC configuration
  418. */
  419. #define RTC
  420. #define CONFIG_RTC_DS3231 1
  421. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  422. /*
  423. * eSPI - Enhanced SPI
  424. */
  425. /*
  426. * General PCIe
  427. * Memory space is mapped 1-1, but I/O space must start from 0.
  428. */
  429. #define CONFIG_PCIE1 /* PCIE controller 1 */
  430. #define CONFIG_PCIE2 /* PCIE controller 2 */
  431. #define CONFIG_PCIE3 /* PCIE controller 3 */
  432. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  433. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  434. #define CONFIG_PCI_INDIRECT_BRIDGE
  435. #ifdef CONFIG_PCI
  436. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  437. #ifdef CONFIG_PCIE1
  438. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  439. #ifdef CONFIG_PHYS_64BIT
  440. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  441. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  442. #else
  443. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  444. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  445. #endif
  446. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  447. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  448. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  449. #ifdef CONFIG_PHYS_64BIT
  450. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  451. #else
  452. #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
  453. #endif
  454. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  455. #endif
  456. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  457. #ifdef CONFIG_PCIE2
  458. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  459. #ifdef CONFIG_PHYS_64BIT
  460. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  461. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  462. #else
  463. #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
  464. #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
  465. #endif
  466. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  467. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  468. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  469. #ifdef CONFIG_PHYS_64BIT
  470. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  471. #else
  472. #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
  473. #endif
  474. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  475. #endif
  476. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  477. #ifdef CONFIG_PCIE3
  478. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  479. #ifdef CONFIG_PHYS_64BIT
  480. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  481. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  482. #else
  483. #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
  484. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
  485. #endif
  486. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  487. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  488. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  489. #ifdef CONFIG_PHYS_64BIT
  490. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  491. #else
  492. #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
  493. #endif
  494. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  495. #endif
  496. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  497. #endif /* CONFIG_PCI */
  498. /*
  499. *SATA
  500. */
  501. #define CONFIG_FSL_SATA_V2
  502. #ifdef CONFIG_FSL_SATA_V2
  503. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  504. #define CONFIG_SATA1
  505. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  506. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  507. #define CONFIG_LBA48
  508. #endif
  509. /*
  510. * USB
  511. */
  512. #define CONFIG_HAS_FSL_DR_USB
  513. #ifdef CONFIG_HAS_FSL_DR_USB
  514. #define CONFIG_USB_EHCI_FSL
  515. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  516. #endif
  517. /*
  518. * SDHC
  519. */
  520. #ifdef CONFIG_MMC
  521. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  522. #endif
  523. /* Qman/Bman */
  524. #ifndef CONFIG_NOBQFMAN
  525. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  526. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  527. #ifdef CONFIG_PHYS_64BIT
  528. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  529. #else
  530. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  531. #endif
  532. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  533. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  534. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  535. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  536. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  537. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  538. CONFIG_SYS_BMAN_CENA_SIZE)
  539. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  540. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  541. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  542. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  543. #ifdef CONFIG_PHYS_64BIT
  544. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  545. #else
  546. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  547. #endif
  548. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  549. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  550. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  551. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  552. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  553. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  554. CONFIG_SYS_QMAN_CENA_SIZE)
  555. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  556. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  557. #define CONFIG_SYS_DPAA_FMAN
  558. /* Default address of microcode for the Linux FMan driver */
  559. #if defined(CONFIG_SPIFLASH)
  560. /*
  561. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  562. * env, so we got 0x110000.
  563. */
  564. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  565. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  566. #elif defined(CONFIG_SDCARD)
  567. /*
  568. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  569. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  570. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  571. */
  572. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  573. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  574. #elif defined(CONFIG_MTD_RAW_NAND)
  575. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  576. #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
  577. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  578. /*
  579. * Slave has no ucode locally, it can fetch this from remote. When implementing
  580. * in two corenet boards, slave's ucode could be stored in master's memory
  581. * space, the address can be mapped from slave TLB->slave LAW->
  582. * slave SRIO or PCIE outbound window->master inbound window->
  583. * master LAW->the ucode address in master's memory space.
  584. */
  585. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  586. #else
  587. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  588. #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
  589. #endif
  590. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  591. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  592. #endif /* CONFIG_NOBQFMAN */
  593. #ifdef CONFIG_SYS_DPAA_FMAN
  594. #define RGMII_PHY1_ADDR 0x1
  595. #define RGMII_PHY2_ADDR 0x2
  596. #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
  597. #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
  598. #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
  599. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  600. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  601. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  602. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  603. #endif
  604. #ifdef CONFIG_FMAN_ENET
  605. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  606. #endif
  607. /*
  608. * Dynamic MTD Partition support with mtdparts
  609. */
  610. /*
  611. * Environment
  612. */
  613. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  614. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  615. /*
  616. * Miscellaneous configurable options
  617. */
  618. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  619. /*
  620. * For booting Linux, the board info and command line data
  621. * have to be in the first 64 MB of memory, since this is
  622. * the maximum mapped by the Linux kernel during initialization.
  623. */
  624. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  625. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  626. #ifdef CONFIG_CMD_KGDB
  627. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  628. #endif
  629. /*
  630. * Environment Configuration
  631. */
  632. #define CONFIG_ROOTPATH "/opt/nfsroot"
  633. #define CONFIG_BOOTFILE "uImage"
  634. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  635. #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
  636. #define __USB_PHY_TYPE utmi
  637. #define CONFIG_EXTRA_ENV_SETTINGS \
  638. "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
  639. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  640. "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
  641. "ramdiskfile=t1024qds/ramdisk.uboot\0" \
  642. "fdtfile=t1024qds/t1024qds.dtb\0" \
  643. "netdev=eth0\0" \
  644. "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
  645. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  646. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  647. "tftpflash=tftpboot $loadaddr $uboot && " \
  648. "protect off $ubootaddr +$filesize && " \
  649. "erase $ubootaddr +$filesize && " \
  650. "cp.b $loadaddr $ubootaddr $filesize && " \
  651. "protect on $ubootaddr +$filesize && " \
  652. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  653. "consoledev=ttyS0\0" \
  654. "ramdiskaddr=2000000\0" \
  655. "fdtaddr=d00000\0" \
  656. "bdev=sda3\0"
  657. #define CONFIG_LINUX \
  658. "setenv bootargs root=/dev/ram rw " \
  659. "console=$consoledev,$baudrate $othbootargs;" \
  660. "setenv ramdiskaddr 0x02000000;" \
  661. "setenv fdtaddr 0x00c00000;" \
  662. "setenv loadaddr 0x1000000;" \
  663. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  664. #define CONFIG_NFSBOOTCOMMAND \
  665. "setenv bootargs root=/dev/nfs rw " \
  666. "nfsroot=$serverip:$rootpath " \
  667. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  668. "console=$consoledev,$baudrate $othbootargs;" \
  669. "tftp $loadaddr $bootfile;" \
  670. "tftp $fdtaddr $fdtfile;" \
  671. "bootm $loadaddr - $fdtaddr"
  672. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  673. #include <asm/fsl_secure_boot.h>
  674. #endif /* __T1024QDS_H */