P2041RDB.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * P2041 RDB board configuration file
  8. * Also supports P2040 RDB
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. #ifdef CONFIG_RAMBOOT_PBL
  13. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  14. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  15. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  16. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  17. #endif
  18. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  19. /* Set 1M boot space */
  20. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  21. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  22. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  23. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  24. #endif
  25. /* High Level Configuration Options */
  26. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  27. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  28. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  29. #endif
  30. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  31. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  32. #define CONFIG_PCIE1 /* PCIE controller 1 */
  33. #define CONFIG_PCIE2 /* PCIE controller 2 */
  34. #define CONFIG_PCIE3 /* PCIE controller 3 */
  35. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  36. #define CONFIG_SYS_SRIO
  37. #define CONFIG_SRIO1 /* SRIO port 1 */
  38. #define CONFIG_SRIO2 /* SRIO port 2 */
  39. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  40. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  41. #define CONFIG_ENV_OVERWRITE
  42. #if defined(CONFIG_SPIFLASH)
  43. #elif defined(CONFIG_SDCARD)
  44. #define CONFIG_FSL_FIXED_MMC_LOCATION
  45. #define CONFIG_SYS_MMC_ENV_DEV 0
  46. #endif
  47. #ifndef __ASSEMBLY__
  48. unsigned long get_board_sys_clk(unsigned long dummy);
  49. #include <linux/stringify.h>
  50. #endif
  51. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  52. /*
  53. * These can be toggled for performance analysis, otherwise use default.
  54. */
  55. #define CONFIG_SYS_CACHE_STASHING
  56. #define CONFIG_BACKSIDE_L2_CACHE
  57. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  58. #define CONFIG_BTB /* toggle branch predition */
  59. #define CONFIG_ENABLE_36BIT_PHYS
  60. #ifdef CONFIG_PHYS_64BIT
  61. #define CONFIG_ADDR_MAP
  62. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  63. #endif
  64. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  65. /*
  66. * Config the L3 Cache as L3 SRAM
  67. */
  68. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  69. #ifdef CONFIG_PHYS_64BIT
  70. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
  71. CONFIG_RAMBOOT_TEXT_BASE)
  72. #else
  73. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  74. #endif
  75. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  76. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  77. #ifdef CONFIG_PHYS_64BIT
  78. #define CONFIG_SYS_DCSRBAR 0xf0000000
  79. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  80. #endif
  81. /* EEPROM */
  82. #define CONFIG_ID_EEPROM
  83. #define CONFIG_SYS_I2C_EEPROM_NXID
  84. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  85. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  86. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  87. /*
  88. * DDR Setup
  89. */
  90. #define CONFIG_VERY_BIG_RAM
  91. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  92. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  93. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  94. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  95. #define CONFIG_DDR_SPD
  96. #define CONFIG_SYS_SPD_BUS_NUM 0
  97. #define SPD_EEPROM_ADDRESS 0x52
  98. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  99. /*
  100. * Local Bus Definitions
  101. */
  102. /* Set the local bus clock 1/8 of platform clock */
  103. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  104. /*
  105. * This board doesn't have a promjet connector.
  106. * However, it uses commone corenet board LAW and TLB.
  107. * It is necessary to use the same start address with proper offset.
  108. */
  109. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  110. #ifdef CONFIG_PHYS_64BIT
  111. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  112. #else
  113. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  114. #endif
  115. #define CONFIG_SYS_FLASH_BR_PRELIM \
  116. (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
  117. BR_PS_16 | BR_V)
  118. #define CONFIG_SYS_FLASH_OR_PRELIM \
  119. ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  120. | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
  121. #define CONFIG_FSL_CPLD
  122. #define CPLD_BASE 0xffdf0000 /* CPLD registers */
  123. #ifdef CONFIG_PHYS_64BIT
  124. #define CPLD_BASE_PHYS 0xfffdf0000ull
  125. #else
  126. #define CPLD_BASE_PHYS CPLD_BASE
  127. #endif
  128. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
  129. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  130. #define PIXIS_LBMAP_SWITCH 7
  131. #define PIXIS_LBMAP_MASK 0xf0
  132. #define PIXIS_LBMAP_SHIFT 4
  133. #define PIXIS_LBMAP_ALTBANK 0x40
  134. #define CONFIG_SYS_FLASH_QUIET_TEST
  135. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  136. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  137. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  138. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
  139. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
  140. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  141. #if defined(CONFIG_RAMBOOT_PBL)
  142. #define CONFIG_SYS_RAMBOOT
  143. #endif
  144. #define CONFIG_NAND_FSL_ELBC
  145. /* Nand Flash */
  146. #ifdef CONFIG_NAND_FSL_ELBC
  147. #define CONFIG_SYS_NAND_BASE 0xffa00000
  148. #ifdef CONFIG_PHYS_64BIT
  149. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  150. #else
  151. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  152. #endif
  153. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  154. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  155. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  156. /* NAND flash config */
  157. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  158. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  159. | BR_PS_8 /* Port Size = 8 bit */ \
  160. | BR_MS_FCM /* MSEL = FCM */ \
  161. | BR_V) /* valid */
  162. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  163. | OR_FCM_PGS /* Large Page*/ \
  164. | OR_FCM_CSCT \
  165. | OR_FCM_CST \
  166. | OR_FCM_CHT \
  167. | OR_FCM_SCY_1 \
  168. | OR_FCM_TRLX \
  169. | OR_FCM_EHTR)
  170. #ifdef CONFIG_MTD_RAW_NAND
  171. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  172. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  173. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  174. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  175. #else
  176. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  177. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  178. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  179. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  180. #endif
  181. #else
  182. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  183. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  184. #endif /* CONFIG_NAND_FSL_ELBC */
  185. #define CONFIG_SYS_FLASH_EMPTY_INFO
  186. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  187. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  188. #define CONFIG_HWCONFIG
  189. /* define to use L1 as initial stack */
  190. #define CONFIG_L1_INIT_RAM
  191. #define CONFIG_SYS_INIT_RAM_LOCK
  192. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  193. #ifdef CONFIG_PHYS_64BIT
  194. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  195. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  196. /* The assembler doesn't like typecast */
  197. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  198. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  199. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  200. #else
  201. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  202. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  203. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  204. #endif
  205. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  206. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  207. GENERATED_GBL_DATA_SIZE)
  208. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  209. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  210. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  211. /* Serial Port - controlled on board with jumper J8
  212. * open - index 2
  213. * shorted - index 1
  214. */
  215. #define CONFIG_SYS_NS16550_SERIAL
  216. #define CONFIG_SYS_NS16550_REG_SIZE 1
  217. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  218. #define CONFIG_SYS_BAUDRATE_TABLE \
  219. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  220. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  221. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  222. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  223. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  224. /* I2C */
  225. #ifndef CONFIG_DM_I2C
  226. #define CONFIG_SYS_I2C
  227. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  228. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  229. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  230. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  231. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  232. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  233. #else
  234. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  235. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  236. #endif
  237. #define CONFIG_SYS_I2C_FSL
  238. /*
  239. * RapidIO
  240. */
  241. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  242. #ifdef CONFIG_PHYS_64BIT
  243. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  244. #else
  245. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  246. #endif
  247. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  248. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  249. #ifdef CONFIG_PHYS_64BIT
  250. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  251. #else
  252. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  253. #endif
  254. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  255. /*
  256. * for slave u-boot IMAGE instored in master memory space,
  257. * PHYS must be aligned based on the SIZE
  258. */
  259. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  260. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  261. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  262. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  263. /*
  264. * for slave UCODE and ENV instored in master memory space,
  265. * PHYS must be aligned based on the SIZE
  266. */
  267. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  268. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  269. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  270. /* slave core release by master*/
  271. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  272. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  273. /*
  274. * SRIO_PCIE_BOOT - SLAVE
  275. */
  276. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  277. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  278. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  279. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  280. #endif
  281. /*
  282. * eSPI - Enhanced SPI
  283. */
  284. /*
  285. * General PCI
  286. * Memory space is mapped 1-1, but I/O space must start from 0.
  287. */
  288. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  289. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  290. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  291. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  292. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  293. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  294. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  295. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  296. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  297. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  298. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  299. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  300. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  301. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  302. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  303. /* Qman/Bman */
  304. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  305. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  306. #ifdef CONFIG_PHYS_64BIT
  307. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  308. #else
  309. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  310. #endif
  311. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  312. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  313. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  314. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  315. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  316. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  317. CONFIG_SYS_BMAN_CENA_SIZE)
  318. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  319. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  320. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  321. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  322. #ifdef CONFIG_PHYS_64BIT
  323. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  324. #else
  325. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  326. #endif
  327. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  328. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  329. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  330. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  331. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  332. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  333. CONFIG_SYS_QMAN_CENA_SIZE)
  334. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  335. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  336. #define CONFIG_SYS_DPAA_FMAN
  337. #define CONFIG_SYS_DPAA_PME
  338. /* Default address of microcode for the Linux Fman driver */
  339. #if defined(CONFIG_SPIFLASH)
  340. /*
  341. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  342. * env, so we got 0x110000.
  343. */
  344. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  345. #elif defined(CONFIG_SDCARD)
  346. /*
  347. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  348. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  349. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  350. */
  351. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  352. #elif defined(CONFIG_MTD_RAW_NAND)
  353. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  354. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  355. /*
  356. * Slave has no ucode locally, it can fetch this from remote. When implementing
  357. * in two corenet boards, slave's ucode could be stored in master's memory
  358. * space, the address can be mapped from slave TLB->slave LAW->
  359. * slave SRIO or PCIE outbound window->master inbound window->
  360. * master LAW->the ucode address in master's memory space.
  361. */
  362. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  363. #else
  364. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  365. #endif
  366. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  367. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  368. #ifdef CONFIG_PCI
  369. #if !defined(CONFIG_DM_PCI)
  370. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  371. #define CONFIG_PCI_INDIRECT_BRIDGE
  372. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  373. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  374. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  375. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  376. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  377. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  378. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  379. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  380. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  381. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  382. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  383. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  384. #endif
  385. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  386. #endif /* CONFIG_PCI */
  387. /* SATA */
  388. #define CONFIG_FSL_SATA_V2
  389. #ifdef CONFIG_FSL_SATA_V2
  390. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  391. #define CONFIG_SATA1
  392. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  393. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  394. #define CONFIG_SATA2
  395. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  396. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  397. #define CONFIG_LBA48
  398. #endif
  399. #ifdef CONFIG_FMAN_ENET
  400. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
  401. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
  402. #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
  403. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
  404. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
  405. #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
  406. #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
  407. #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
  408. #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
  409. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
  410. #define CONFIG_SYS_TBIPA_VALUE 8
  411. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  412. #endif
  413. /*
  414. * Environment
  415. */
  416. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  417. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  418. /*
  419. * Command line configuration.
  420. */
  421. /*
  422. * USB
  423. */
  424. #define CONFIG_HAS_FSL_DR_USB
  425. #define CONFIG_HAS_FSL_MPH_USB
  426. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  427. #define CONFIG_USB_EHCI_FSL
  428. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  429. #endif
  430. #ifdef CONFIG_MMC
  431. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  432. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  433. #endif
  434. /*
  435. * Miscellaneous configurable options
  436. */
  437. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  438. /*
  439. * For booting Linux, the board info and command line data
  440. * have to be in the first 64 MB of memory, since this is
  441. * the maximum mapped by the Linux kernel during initialization.
  442. */
  443. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
  444. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  445. #ifdef CONFIG_CMD_KGDB
  446. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  447. #endif
  448. /*
  449. * Environment Configuration
  450. */
  451. #define CONFIG_ROOTPATH "/opt/nfsroot"
  452. #define CONFIG_BOOTFILE "uImage"
  453. #define CONFIG_UBOOTPATH u-boot.bin
  454. /* default location for tftp and bootm */
  455. #define CONFIG_LOADADDR 1000000
  456. #define __USB_PHY_TYPE utmi
  457. #define CONFIG_EXTRA_ENV_SETTINGS \
  458. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  459. "bank_intlv=cs0_cs1\0" \
  460. "netdev=eth0\0" \
  461. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  462. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  463. "tftpflash=tftpboot $loadaddr $uboot && " \
  464. "protect off $ubootaddr +$filesize && " \
  465. "erase $ubootaddr +$filesize && " \
  466. "cp.b $loadaddr $ubootaddr $filesize && " \
  467. "protect on $ubootaddr +$filesize && " \
  468. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  469. "consoledev=ttyS0\0" \
  470. "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  471. "usb_dr_mode=host\0" \
  472. "ramdiskaddr=2000000\0" \
  473. "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
  474. "fdtaddr=1e00000\0" \
  475. "fdtfile=p2041rdb/p2041rdb.dtb\0" \
  476. "bdev=sda3\0"
  477. #define CONFIG_HDBOOT \
  478. "setenv bootargs root=/dev/$bdev rw " \
  479. "console=$consoledev,$baudrate $othbootargs;" \
  480. "tftp $loadaddr $bootfile;" \
  481. "tftp $fdtaddr $fdtfile;" \
  482. "bootm $loadaddr - $fdtaddr"
  483. #define CONFIG_NFSBOOTCOMMAND \
  484. "setenv bootargs root=/dev/nfs rw " \
  485. "nfsroot=$serverip:$rootpath " \
  486. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  487. "console=$consoledev,$baudrate $othbootargs;" \
  488. "tftp $loadaddr $bootfile;" \
  489. "tftp $fdtaddr $fdtfile;" \
  490. "bootm $loadaddr - $fdtaddr"
  491. #define CONFIG_RAMBOOTCOMMAND \
  492. "setenv bootargs root=/dev/ram rw " \
  493. "console=$consoledev,$baudrate $othbootargs;" \
  494. "tftp $ramdiskaddr $ramdiskfile;" \
  495. "tftp $loadaddr $bootfile;" \
  496. "tftp $fdtaddr $fdtfile;" \
  497. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  498. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  499. #include <asm/fsl_secure_boot.h>
  500. #endif /* __CONFIG_H */