MPC8641HPCN.h 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2006, 2010-2011 Freescale Semiconductor.
  4. *
  5. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  6. */
  7. /*
  8. * MPC8641HPCN board configuration file
  9. *
  10. * Make sure you change the MAC address and other network params first,
  11. * search for CONFIG_SERVERIP, etc. in this file.
  12. */
  13. #ifndef __CONFIG_H
  14. #define __CONFIG_H
  15. #include <linux/stringify.h>
  16. /* High Level Configuration Options */
  17. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  18. #define CONFIG_ADDR_MAP 1 /* Use addr map */
  19. /*
  20. * default CCSRBAR is at 0xff700000
  21. * assume U-Boot is less than 0.5MB
  22. */
  23. #ifdef RUN_DIAG
  24. #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
  25. #endif
  26. /*
  27. * virtual address to be used for temporary mappings. There
  28. * should be 128k free at this VA.
  29. */
  30. #define CONFIG_SYS_SCRATCH_VA 0xe0000000
  31. #define CONFIG_SYS_SRIO
  32. #define CONFIG_SRIO1 /* SRIO port 1 */
  33. #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
  34. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
  35. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  36. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  37. #define CONFIG_ENV_OVERWRITE
  38. #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
  39. #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
  40. #define CONFIG_ALTIVEC 1
  41. /*
  42. * L2CR setup -- make sure this is right for your board!
  43. */
  44. #define CONFIG_SYS_L2
  45. #define L2_INIT 0
  46. #define L2_ENABLE (L2CR_L2E)
  47. #ifndef CONFIG_SYS_CLK_FREQ
  48. #ifndef __ASSEMBLY__
  49. extern unsigned long get_board_sys_clk(unsigned long dummy);
  50. #endif
  51. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  52. #endif
  53. /*
  54. * With the exception of PCI Memory and Rapid IO, most devices will simply
  55. * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  56. * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
  57. */
  58. #ifdef CONFIG_PHYS_64BIT
  59. #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  60. #else
  61. #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  62. #endif
  63. /*
  64. * Base addresses -- Note these are effective addresses where the
  65. * actual resources get mapped (not physical addresses)
  66. */
  67. #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  68. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  69. /* Physical addresses */
  70. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  71. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
  72. #define CONFIG_SYS_CCSRBAR_PHYS \
  73. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  74. CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  75. #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
  76. /*
  77. * DDR Setup
  78. */
  79. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  80. #define CONFIG_DDR_SPD
  81. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  82. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  83. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  84. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  85. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  86. #define CONFIG_VERY_BIG_RAM
  87. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  88. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  89. /*
  90. * I2C addresses of SPD EEPROMs
  91. */
  92. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  93. #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
  94. #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
  95. #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
  96. /*
  97. * These are used when DDR doesn't use SPD.
  98. */
  99. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  100. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  101. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
  102. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  103. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  104. #define CONFIG_SYS_DDR_TIMING_1 0x39357322
  105. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  106. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  107. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  108. #define CONFIG_SYS_DDR_INTERVAL 0x06090100
  109. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  110. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  111. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  112. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  113. #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
  114. #define CONFIG_SYS_DDR_CONTROL2 0x04400000
  115. #define CONFIG_ID_EEPROM
  116. #define CONFIG_SYS_I2C_EEPROM_NXID
  117. #define CONFIG_ID_EEPROM
  118. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  119. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  120. #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
  121. #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
  122. #define CONFIG_SYS_FLASH_BASE_PHYS \
  123. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  124. CONFIG_SYS_PHYS_ADDR_HIGH)
  125. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  126. #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  127. | 0x00001001) /* port size 16bit */
  128. #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
  129. #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
  130. | 0x00001001) /* port size 16bit */
  131. #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
  132. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
  133. | 0x00000801) /* port size 8bit */
  134. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
  135. /*
  136. * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
  137. * The PIXIS and CF by themselves aren't large enough to take up the 128k
  138. * required for the smallest BAT mapping, so there's a 64k hole.
  139. */
  140. #define CONFIG_SYS_LBC_BASE 0xffde0000
  141. #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
  142. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  143. #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
  144. #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
  145. #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
  146. CONFIG_SYS_PHYS_ADDR_HIGH)
  147. #define PIXIS_SIZE 0x00008000 /* 32k */
  148. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  149. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  150. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  151. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  152. #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
  153. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  154. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  155. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  156. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  157. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  158. #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
  159. #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
  160. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  161. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  162. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  163. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  164. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
  165. /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
  166. #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
  167. #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
  168. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  169. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  170. #undef CONFIG_SYS_FLASH_CHECKSUM
  171. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  172. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  173. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  174. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  175. #define CONFIG_SYS_FLASH_EMPTY_INFO
  176. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  177. #define CONFIG_SYS_RAMBOOT
  178. #else
  179. #undef CONFIG_SYS_RAMBOOT
  180. #endif
  181. #if defined(CONFIG_SYS_RAMBOOT)
  182. #undef CONFIG_SPD_EEPROM
  183. #define CONFIG_SYS_SDRAM_SIZE 256
  184. #endif
  185. #undef CONFIG_CLOCKS_IN_MHZ
  186. #define CONFIG_SYS_INIT_RAM_LOCK 1
  187. #ifndef CONFIG_SYS_INIT_RAM_LOCK
  188. #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
  189. #else
  190. #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
  191. #endif
  192. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  193. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  194. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  195. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  196. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  197. /* Serial Port */
  198. #define CONFIG_SYS_NS16550_SERIAL
  199. #define CONFIG_SYS_NS16550_REG_SIZE 1
  200. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  201. #define CONFIG_SYS_BAUDRATE_TABLE \
  202. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  203. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  204. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  205. /*
  206. * I2C
  207. */
  208. #define CONFIG_SYS_I2C
  209. #define CONFIG_SYS_I2C_FSL
  210. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  211. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  212. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  213. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  214. /*
  215. * RapidIO MMU
  216. */
  217. #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
  218. #ifdef CONFIG_PHYS_64BIT
  219. #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
  220. #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
  221. #else
  222. #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
  223. #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
  224. #endif
  225. #define CONFIG_SYS_SRIO1_MEM_PHYS \
  226. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  227. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
  228. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
  229. /*
  230. * General PCI
  231. * Addresses are mapped 1-1.
  232. */
  233. #define CONFIG_SYS_PCIE1_NAME "ULI"
  234. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  235. #ifdef CONFIG_PHYS_64BIT
  236. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  237. #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
  238. #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
  239. #else
  240. #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
  241. #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
  242. #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
  243. #endif
  244. #define CONFIG_SYS_PCIE1_MEM_PHYS \
  245. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  246. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
  247. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  248. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  249. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  250. #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
  251. #define CONFIG_SYS_PCIE1_IO_PHYS \
  252. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  253. CONFIG_SYS_PHYS_ADDR_HIGH)
  254. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
  255. #ifdef CONFIG_PHYS_64BIT
  256. /*
  257. * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
  258. * This will increase the amount of PCI address space available for
  259. * for mapping RAM.
  260. */
  261. #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
  262. #else
  263. #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
  264. + CONFIG_SYS_PCIE1_MEM_SIZE)
  265. #endif
  266. #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
  267. + CONFIG_SYS_PCIE1_MEM_SIZE)
  268. #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
  269. + CONFIG_SYS_PCIE1_MEM_SIZE)
  270. #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
  271. #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
  272. + CONFIG_SYS_PCIE1_MEM_SIZE)
  273. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  274. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  275. #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
  276. + CONFIG_SYS_PCIE1_IO_SIZE)
  277. #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
  278. + CONFIG_SYS_PCIE1_IO_SIZE)
  279. #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
  280. + CONFIG_SYS_PCIE1_IO_SIZE)
  281. #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
  282. #if defined(CONFIG_PCI)
  283. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  284. #undef CONFIG_EEPRO100
  285. #undef CONFIG_TULIP
  286. /************************************************************
  287. * USB support
  288. ************************************************************/
  289. #define CONFIG_PCI_OHCI 1
  290. #define CONFIG_USB_OHCI_NEW 1
  291. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  292. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  293. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  294. /*PCIE video card used*/
  295. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
  296. /*PCI video card used*/
  297. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
  298. /* video */
  299. #if defined(CONFIG_VIDEO)
  300. #define CONFIG_BIOSEMU
  301. #define CONFIG_ATI_RADEON_FB
  302. #define CONFIG_VIDEO_LOGO
  303. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
  304. #endif
  305. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  306. #ifdef CONFIG_SCSI_AHCI
  307. #define CONFIG_SATA_ULI5288
  308. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  309. #define CONFIG_SYS_SCSI_MAX_LUN 1
  310. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  311. #endif
  312. #endif /* CONFIG_PCI */
  313. #if defined(CONFIG_TSEC_ENET)
  314. #define CONFIG_TSEC1 1
  315. #define CONFIG_TSEC1_NAME "eTSEC1"
  316. #define CONFIG_TSEC2 1
  317. #define CONFIG_TSEC2_NAME "eTSEC2"
  318. #define CONFIG_TSEC3 1
  319. #define CONFIG_TSEC3_NAME "eTSEC3"
  320. #define CONFIG_TSEC4 1
  321. #define CONFIG_TSEC4_NAME "eTSEC4"
  322. #define TSEC1_PHY_ADDR 0
  323. #define TSEC2_PHY_ADDR 1
  324. #define TSEC3_PHY_ADDR 2
  325. #define TSEC4_PHY_ADDR 3
  326. #define TSEC1_PHYIDX 0
  327. #define TSEC2_PHYIDX 0
  328. #define TSEC3_PHYIDX 0
  329. #define TSEC4_PHYIDX 0
  330. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  331. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  332. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  333. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  334. #define CONFIG_ETHPRIME "eTSEC1"
  335. #endif /* CONFIG_TSEC_ENET */
  336. #ifdef CONFIG_PHYS_64BIT
  337. #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
  338. #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
  339. /* Put physical address into the BAT format */
  340. #define BAT_PHYS_ADDR(low, high) \
  341. (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
  342. /* Convert high/low pairs to actual 64-bit value */
  343. #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
  344. #else
  345. /* 32-bit systems just ignore the "high" bits */
  346. #define BAT_PHYS_ADDR(low, high) (low)
  347. #define PAIRED_PHYS_TO_PHYS(low, high) (low)
  348. #endif
  349. /*
  350. * BAT0 DDR
  351. */
  352. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  353. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  354. /*
  355. * BAT1 LBC (PIXIS/CF)
  356. */
  357. #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
  358. CONFIG_SYS_PHYS_ADDR_HIGH) \
  359. | BATL_PP_RW | BATL_CACHEINHIBIT | \
  360. BATL_GUARDEDSTORAGE)
  361. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
  362. | BATU_VS | BATU_VP)
  363. #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
  364. CONFIG_SYS_PHYS_ADDR_HIGH) \
  365. | BATL_PP_RW | BATL_MEMCOHERENCE)
  366. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  367. /* if CONFIG_PCI:
  368. * BAT2 PCIE1 and PCIE1 MEM
  369. * if CONFIG_RIO
  370. * BAT2 Rapidio Memory
  371. */
  372. #ifdef CONFIG_PCI
  373. #define CONFIG_PCI_INDIRECT_BRIDGE
  374. #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  375. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
  376. | BATL_PP_RW | BATL_CACHEINHIBIT \
  377. | BATL_GUARDEDSTORAGE)
  378. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
  379. | BATU_VS | BATU_VP)
  380. #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  381. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
  382. | BATL_PP_RW | BATL_CACHEINHIBIT)
  383. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  384. #else /* CONFIG_RIO */
  385. #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  386. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
  387. | BATL_PP_RW | BATL_CACHEINHIBIT | \
  388. BATL_GUARDEDSTORAGE)
  389. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
  390. | BATU_VS | BATU_VP)
  391. #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  392. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
  393. | BATL_PP_RW | BATL_CACHEINHIBIT)
  394. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  395. #endif
  396. /*
  397. * BAT3 CCSR Space
  398. */
  399. #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  400. CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
  401. | BATL_PP_RW | BATL_CACHEINHIBIT \
  402. | BATL_GUARDEDSTORAGE)
  403. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
  404. | BATU_VP)
  405. #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  406. CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
  407. | BATL_PP_RW | BATL_CACHEINHIBIT)
  408. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  409. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  410. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  411. | BATL_PP_RW | BATL_CACHEINHIBIT \
  412. | BATL_GUARDEDSTORAGE)
  413. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
  414. | BATU_BL_1M | BATU_VS | BATU_VP)
  415. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  416. | BATL_PP_RW | BATL_CACHEINHIBIT)
  417. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  418. #endif
  419. /*
  420. * BAT4 PCIE1_IO and PCIE2_IO
  421. */
  422. #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  423. CONFIG_SYS_PHYS_ADDR_HIGH) \
  424. | BATL_PP_RW | BATL_CACHEINHIBIT \
  425. | BATL_GUARDEDSTORAGE)
  426. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
  427. | BATU_VS | BATU_VP)
  428. #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  429. CONFIG_SYS_PHYS_ADDR_HIGH) \
  430. | BATL_PP_RW | BATL_CACHEINHIBIT)
  431. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  432. /*
  433. * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
  434. */
  435. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  436. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  437. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  438. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  439. /*
  440. * BAT6 FLASH
  441. */
  442. #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  443. CONFIG_SYS_PHYS_ADDR_HIGH) \
  444. | BATL_PP_RW | BATL_CACHEINHIBIT \
  445. | BATL_GUARDEDSTORAGE)
  446. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
  447. | BATU_VP)
  448. #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  449. CONFIG_SYS_PHYS_ADDR_HIGH) \
  450. | BATL_PP_RW | BATL_MEMCOHERENCE)
  451. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  452. /* Map the last 1M of flash where we're running from reset */
  453. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  454. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  455. #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  456. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  457. | BATL_MEMCOHERENCE)
  458. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  459. /*
  460. * BAT7 FREE - used later for tmp mappings
  461. */
  462. #define CONFIG_SYS_DBAT7L 0x00000000
  463. #define CONFIG_SYS_DBAT7U 0x00000000
  464. #define CONFIG_SYS_IBAT7L 0x00000000
  465. #define CONFIG_SYS_IBAT7U 0x00000000
  466. /*
  467. * Environment
  468. */
  469. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  470. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  471. /*
  472. * BOOTP options
  473. */
  474. #define CONFIG_BOOTP_BOOTFILESIZE
  475. #undef CONFIG_WATCHDOG /* watchdog disabled */
  476. /*
  477. * Miscellaneous configurable options
  478. */
  479. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  480. /*
  481. * For booting Linux, the board info and command line data
  482. * have to be in the first 8 MB of memory, since this is
  483. * the maximum mapped by the Linux kernel during initialization.
  484. */
  485. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
  486. #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
  487. #if defined(CONFIG_CMD_KGDB)
  488. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  489. #endif
  490. /*
  491. * Environment Configuration
  492. */
  493. #define CONFIG_HAS_ETH0 1
  494. #define CONFIG_HAS_ETH1 1
  495. #define CONFIG_HAS_ETH2 1
  496. #define CONFIG_HAS_ETH3 1
  497. #define CONFIG_IPADDR 192.168.1.100
  498. #define CONFIG_HOSTNAME "unknown"
  499. #define CONFIG_ROOTPATH "/opt/nfsroot"
  500. #define CONFIG_BOOTFILE "uImage"
  501. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  502. #define CONFIG_SERVERIP 192.168.1.1
  503. #define CONFIG_GATEWAYIP 192.168.1.1
  504. #define CONFIG_NETMASK 255.255.255.0
  505. /* default location for tftp and bootm */
  506. #define CONFIG_LOADADDR 0x10000000
  507. #define CONFIG_EXTRA_ENV_SETTINGS \
  508. "netdev=eth0\0" \
  509. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  510. "tftpflash=tftpboot $loadaddr $uboot; " \
  511. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  512. " +$filesize; " \
  513. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  514. " +$filesize; " \
  515. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  516. " $filesize; " \
  517. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  518. " +$filesize; " \
  519. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  520. " $filesize\0" \
  521. "consoledev=ttyS0\0" \
  522. "ramdiskaddr=0x18000000\0" \
  523. "ramdiskfile=your.ramdisk.u-boot\0" \
  524. "fdtaddr=0x17c00000\0" \
  525. "fdtfile=mpc8641_hpcn.dtb\0" \
  526. "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
  527. "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
  528. "maxcpus=2"
  529. #define CONFIG_NFSBOOTCOMMAND \
  530. "setenv bootargs root=/dev/nfs rw " \
  531. "nfsroot=$serverip:$rootpath " \
  532. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  533. "console=$consoledev,$baudrate $othbootargs;" \
  534. "tftp $loadaddr $bootfile;" \
  535. "tftp $fdtaddr $fdtfile;" \
  536. "bootm $loadaddr - $fdtaddr"
  537. #define CONFIG_RAMBOOTCOMMAND \
  538. "setenv bootargs root=/dev/ram rw " \
  539. "console=$consoledev,$baudrate $othbootargs;" \
  540. "tftp $ramdiskaddr $ramdiskfile;" \
  541. "tftp $loadaddr $bootfile;" \
  542. "tftp $fdtaddr $fdtfile;" \
  543. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  544. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  545. #endif /* __CONFIG_H */