MPC8536DS.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * mpc8536ds board configuration file
  7. *
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #include "../board/freescale/common/ics307_clk.h"
  13. #ifdef CONFIG_SDCARD
  14. #define CONFIG_RAMBOOT_SDCARD 1
  15. #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
  16. #endif
  17. #ifdef CONFIG_SPIFLASH
  18. #define CONFIG_RAMBOOT_SPIFLASH 1
  19. #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
  20. #endif
  21. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  22. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  23. #endif
  24. #ifndef CONFIG_SYS_MONITOR_BASE
  25. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  26. #endif
  27. #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
  28. #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
  29. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
  30. #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
  31. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  32. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  33. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  34. #define CONFIG_ENV_OVERWRITE
  35. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  36. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  37. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  38. /*
  39. * These can be toggled for performance analysis, otherwise use default.
  40. */
  41. #define CONFIG_L2_CACHE /* toggle L2 cache */
  42. #define CONFIG_BTB /* toggle branch predition */
  43. #define CONFIG_ENABLE_36BIT_PHYS 1
  44. #ifdef CONFIG_PHYS_64BIT
  45. #define CONFIG_ADDR_MAP 1
  46. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  47. #endif
  48. /*
  49. * Config the L2 Cache as L2 SRAM
  50. */
  51. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  52. #ifdef CONFIG_PHYS_64BIT
  53. #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
  54. #else
  55. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  56. #endif
  57. #define CONFIG_SYS_L2_SIZE (512 << 10)
  58. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  59. #define CONFIG_SYS_CCSRBAR 0xffe00000
  60. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  61. #if defined(CONFIG_NAND_SPL)
  62. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  63. #endif
  64. /* DDR Setup */
  65. #define CONFIG_VERY_BIG_RAM
  66. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  67. #define CONFIG_DDR_SPD
  68. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  69. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  70. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  71. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  72. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  73. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  74. /* I2C addresses of SPD EEPROMs */
  75. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  76. #define CONFIG_SYS_SPD_BUS_NUM 1
  77. /* These are used when DDR doesn't use SPD. */
  78. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  79. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
  80. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
  81. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  82. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  83. #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
  84. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  85. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  86. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  87. #define CONFIG_SYS_DDR_INTERVAL 0x06180100
  88. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  89. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  90. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  91. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  92. #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
  93. #define CONFIG_SYS_DDR_CONTROL2 0x04400010
  94. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  95. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  96. #define CONFIG_SYS_DDR_SBE 0x00010000
  97. /* Make sure required options are set */
  98. #ifndef CONFIG_SPD_EEPROM
  99. #error ("CONFIG_SPD_EEPROM is required")
  100. #endif
  101. #undef CONFIG_CLOCKS_IN_MHZ
  102. /*
  103. * Memory map -- xxx -this is wrong, needs updating
  104. *
  105. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  106. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  107. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  108. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  109. *
  110. * Localbus cacheable (TBD)
  111. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  112. *
  113. * Localbus non-cacheable
  114. * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
  115. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  116. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  117. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  118. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  119. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  120. */
  121. /*
  122. * Local Bus Definitions
  123. */
  124. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  125. #ifdef CONFIG_PHYS_64BIT
  126. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  127. #else
  128. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  129. #endif
  130. #define CONFIG_FLASH_BR_PRELIM \
  131. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
  132. #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
  133. #define CONFIG_SYS_BR1_PRELIM \
  134. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  135. | BR_PS_16 | BR_V)
  136. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  137. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
  138. CONFIG_SYS_FLASH_BASE_PHYS }
  139. #define CONFIG_SYS_FLASH_QUIET_TEST
  140. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  141. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  142. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  143. #undef CONFIG_SYS_FLASH_CHECKSUM
  144. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  145. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  146. #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
  147. #define CONFIG_SYS_RAMBOOT
  148. #else
  149. #undef CONFIG_SYS_RAMBOOT
  150. #endif
  151. #define CONFIG_SYS_FLASH_EMPTY_INFO
  152. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  153. #define CONFIG_HWCONFIG /* enable hwconfig */
  154. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  155. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  156. #ifdef CONFIG_PHYS_64BIT
  157. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  158. #else
  159. #define PIXIS_BASE_PHYS PIXIS_BASE
  160. #endif
  161. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  162. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  163. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  164. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  165. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  166. #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
  167. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  168. #define PIXIS_PWR 0x5 /* PIXIS Power status register */
  169. #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
  170. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  171. #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
  172. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  173. #define PIXIS_VSTAT 0x11 /* VELA Status Register */
  174. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  175. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  176. #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
  177. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  178. #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
  179. #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
  180. #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
  181. #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
  182. #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
  183. #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
  184. #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
  185. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  186. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  187. #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
  188. #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
  189. #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
  190. #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
  191. #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
  192. #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
  193. #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
  194. #define PIXIS_VWATCH 0x24 /* Watchdog Register */
  195. #define PIXIS_LED 0x25 /* LED Register */
  196. #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
  197. /* old pixis referenced names */
  198. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  199. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  200. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
  201. #define CONFIG_SYS_INIT_RAM_LOCK 1
  202. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  203. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  204. #define CONFIG_SYS_GBL_DATA_OFFSET \
  205. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  206. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  207. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  208. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  209. #ifndef CONFIG_NAND_SPL
  210. #define CONFIG_SYS_NAND_BASE 0xffa00000
  211. #ifdef CONFIG_PHYS_64BIT
  212. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  213. #else
  214. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  215. #endif
  216. #else
  217. #define CONFIG_SYS_NAND_BASE 0xfff00000
  218. #ifdef CONFIG_PHYS_64BIT
  219. #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
  220. #else
  221. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  222. #endif
  223. #endif
  224. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
  225. CONFIG_SYS_NAND_BASE + 0x40000, \
  226. CONFIG_SYS_NAND_BASE + 0x80000, \
  227. CONFIG_SYS_NAND_BASE + 0xC0000}
  228. #define CONFIG_SYS_MAX_NAND_DEVICE 4
  229. #define CONFIG_NAND_FSL_ELBC 1
  230. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  231. /* NAND boot: 4K NAND loader config */
  232. #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
  233. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
  234. #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
  235. #define CONFIG_SYS_NAND_U_BOOT_START \
  236. (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
  237. #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
  238. #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
  239. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  240. /* NAND flash config */
  241. #define CONFIG_SYS_NAND_BR_PRELIM \
  242. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  243. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  244. | BR_PS_8 /* Port Size = 8 bit */ \
  245. | BR_MS_FCM /* MSEL = FCM */ \
  246. | BR_V) /* valid */
  247. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  248. | OR_FCM_PGS /* Large Page*/ \
  249. | OR_FCM_CSCT \
  250. | OR_FCM_CST \
  251. | OR_FCM_CHT \
  252. | OR_FCM_SCY_1 \
  253. | OR_FCM_TRLX \
  254. | OR_FCM_EHTR)
  255. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  256. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  257. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  258. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  259. #define CONFIG_SYS_BR4_PRELIM \
  260. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
  261. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  262. | BR_PS_8 /* Port Size = 8 bit */ \
  263. | BR_MS_FCM /* MSEL = FCM */ \
  264. | BR_V) /* valid */
  265. #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  266. #define CONFIG_SYS_BR5_PRELIM \
  267. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
  268. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  269. | BR_PS_8 /* Port Size = 8 bit */ \
  270. | BR_MS_FCM /* MSEL = FCM */ \
  271. | BR_V) /* valid */
  272. #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  273. #define CONFIG_SYS_BR6_PRELIM \
  274. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
  275. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  276. | BR_PS_8 /* Port Size = 8 bit */ \
  277. | BR_MS_FCM /* MSEL = FCM */ \
  278. | BR_V) /* valid */
  279. #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  280. /* Serial Port - controlled on board with jumper J8
  281. * open - index 2
  282. * shorted - index 1
  283. */
  284. #define CONFIG_SYS_NS16550_SERIAL
  285. #define CONFIG_SYS_NS16550_REG_SIZE 1
  286. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  287. #ifdef CONFIG_NAND_SPL
  288. #define CONFIG_NS16550_MIN_FUNCTIONS
  289. #endif
  290. #define CONFIG_SYS_BAUDRATE_TABLE \
  291. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  292. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  293. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  294. /*
  295. * I2C
  296. */
  297. #define CONFIG_SYS_I2C
  298. #define CONFIG_SYS_I2C_FSL
  299. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  300. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  301. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  302. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  303. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  304. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  305. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  306. /*
  307. * I2C2 EEPROM
  308. */
  309. #define CONFIG_ID_EEPROM
  310. #ifdef CONFIG_ID_EEPROM
  311. #define CONFIG_SYS_I2C_EEPROM_NXID
  312. #endif
  313. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  314. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  315. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  316. /*
  317. * General PCI
  318. * Memory space is mapped 1-1, but I/O space must start from 0.
  319. */
  320. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  321. #ifdef CONFIG_PHYS_64BIT
  322. #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
  323. #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
  324. #else
  325. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  326. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  327. #endif
  328. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  329. #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
  330. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  331. #ifdef CONFIG_PHYS_64BIT
  332. #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
  333. #else
  334. #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
  335. #endif
  336. #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
  337. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  338. #define CONFIG_SYS_PCIE1_NAME "Slot 1"
  339. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
  340. #ifdef CONFIG_PHYS_64BIT
  341. #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
  342. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
  343. #else
  344. #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
  345. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
  346. #endif
  347. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
  348. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
  349. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  350. #ifdef CONFIG_PHYS_64BIT
  351. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
  352. #else
  353. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
  354. #endif
  355. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  356. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  357. #define CONFIG_SYS_PCIE2_NAME "Slot 2"
  358. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
  359. #ifdef CONFIG_PHYS_64BIT
  360. #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
  361. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
  362. #else
  363. #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
  364. #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
  365. #endif
  366. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
  367. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
  368. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  369. #ifdef CONFIG_PHYS_64BIT
  370. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
  371. #else
  372. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
  373. #endif
  374. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  375. /* controller 3, direct to uli, tgtid 3, Base address 8000 */
  376. #define CONFIG_SYS_PCIE3_NAME "Slot 3"
  377. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  378. #ifdef CONFIG_PHYS_64BIT
  379. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  380. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  381. #else
  382. #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
  383. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
  384. #endif
  385. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  386. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
  387. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  388. #ifdef CONFIG_PHYS_64BIT
  389. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
  390. #else
  391. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
  392. #endif
  393. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  394. #if defined(CONFIG_PCI)
  395. /*PCIE video card used*/
  396. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
  397. /*PCI video card used*/
  398. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
  399. /* video */
  400. #if defined(CONFIG_VIDEO)
  401. #define CONFIG_BIOSEMU
  402. #define CONFIG_ATI_RADEON_FB
  403. #define CONFIG_VIDEO_LOGO
  404. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
  405. #endif
  406. #undef CONFIG_EEPRO100
  407. #undef CONFIG_TULIP
  408. #ifndef CONFIG_PCI_PNP
  409. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
  410. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
  411. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  412. #endif
  413. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  414. #endif /* CONFIG_PCI */
  415. /* SATA */
  416. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  417. #define CONFIG_SATA1
  418. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  419. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  420. #define CONFIG_SATA2
  421. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  422. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  423. #ifdef CONFIG_FSL_SATA
  424. #define CONFIG_LBA48
  425. #endif
  426. #if defined(CONFIG_TSEC_ENET)
  427. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  428. #define CONFIG_TSEC1 1
  429. #define CONFIG_TSEC1_NAME "eTSEC1"
  430. #define CONFIG_TSEC3 1
  431. #define CONFIG_TSEC3_NAME "eTSEC3"
  432. #define CONFIG_FSL_SGMII_RISER 1
  433. #define SGMII_RISER_PHY_OFFSET 0x1c
  434. #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
  435. #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
  436. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  437. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  438. #define TSEC1_PHYIDX 0
  439. #define TSEC3_PHYIDX 0
  440. #define CONFIG_ETHPRIME "eTSEC1"
  441. #endif /* CONFIG_TSEC_ENET */
  442. /*
  443. * Environment
  444. */
  445. #if defined(CONFIG_SYS_RAMBOOT)
  446. #if defined(CONFIG_RAMBOOT_SPIFLASH)
  447. #elif defined(CONFIG_RAMBOOT_SDCARD)
  448. #define CONFIG_FSL_FIXED_MMC_LOCATION
  449. #define CONFIG_SYS_MMC_ENV_DEV 0
  450. #endif
  451. #endif
  452. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  453. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  454. #undef CONFIG_WATCHDOG /* watchdog disabled */
  455. #ifdef CONFIG_MMC
  456. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  457. #endif
  458. /*
  459. * USB
  460. */
  461. #define CONFIG_HAS_FSL_MPH_USB
  462. #ifdef CONFIG_HAS_FSL_MPH_USB
  463. #ifdef CONFIG_USB_EHCI_HCD
  464. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  465. #define CONFIG_USB_EHCI_FSL
  466. #endif
  467. #endif
  468. /*
  469. * Miscellaneous configurable options
  470. */
  471. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  472. /*
  473. * For booting Linux, the board info and command line data
  474. * have to be in the first 64 MB of memory, since this is
  475. * the maximum mapped by the Linux kernel during initialization.
  476. */
  477. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  478. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  479. #if defined(CONFIG_CMD_KGDB)
  480. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  481. #endif
  482. /*
  483. * Environment Configuration
  484. */
  485. /* The mac addresses for all ethernet interface */
  486. #if defined(CONFIG_TSEC_ENET)
  487. #define CONFIG_HAS_ETH0
  488. #define CONFIG_HAS_ETH1
  489. #define CONFIG_HAS_ETH2
  490. #define CONFIG_HAS_ETH3
  491. #endif
  492. #define CONFIG_IPADDR 192.168.1.254
  493. #define CONFIG_HOSTNAME "unknown"
  494. #define CONFIG_ROOTPATH "/opt/nfsroot"
  495. #define CONFIG_BOOTFILE "uImage"
  496. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  497. #define CONFIG_SERVERIP 192.168.1.1
  498. #define CONFIG_GATEWAYIP 192.168.1.1
  499. #define CONFIG_NETMASK 255.255.255.0
  500. /* default location for tftp and bootm */
  501. #define CONFIG_LOADADDR 1000000
  502. #define CONFIG_EXTRA_ENV_SETTINGS \
  503. "netdev=eth0\0" \
  504. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  505. "tftpflash=tftpboot $loadaddr $uboot; " \
  506. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  507. " +$filesize; " \
  508. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  509. " +$filesize; " \
  510. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  511. " $filesize; " \
  512. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  513. " +$filesize; " \
  514. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  515. " $filesize\0" \
  516. "consoledev=ttyS0\0" \
  517. "ramdiskaddr=2000000\0" \
  518. "ramdiskfile=8536ds/ramdisk.uboot\0" \
  519. "fdtaddr=1e00000\0" \
  520. "fdtfile=8536ds/mpc8536ds.dtb\0" \
  521. "bdev=sda3\0" \
  522. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
  523. #define CONFIG_HDBOOT \
  524. "setenv bootargs root=/dev/$bdev rw " \
  525. "console=$consoledev,$baudrate $othbootargs;" \
  526. "tftp $loadaddr $bootfile;" \
  527. "tftp $fdtaddr $fdtfile;" \
  528. "bootm $loadaddr - $fdtaddr"
  529. #define CONFIG_NFSBOOTCOMMAND \
  530. "setenv bootargs root=/dev/nfs rw " \
  531. "nfsroot=$serverip:$rootpath " \
  532. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  533. "console=$consoledev,$baudrate $othbootargs;" \
  534. "tftp $loadaddr $bootfile;" \
  535. "tftp $fdtaddr $fdtfile;" \
  536. "bootm $loadaddr - $fdtaddr"
  537. #define CONFIG_RAMBOOTCOMMAND \
  538. "setenv bootargs root=/dev/ram rw " \
  539. "console=$consoledev,$baudrate $othbootargs;" \
  540. "tftp $ramdiskaddr $ramdiskfile;" \
  541. "tftp $loadaddr $bootfile;" \
  542. "tftp $fdtaddr $fdtfile;" \
  543. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  544. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  545. #endif /* __CONFIG_H */