M5253DEMO.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3. * Hayden Fraser (Hayden.Fraser@freescale.com)
  4. */
  5. #ifndef _M5253DEMO_H
  6. #define _M5253DEMO_H
  7. #include <linux/stringify.h>
  8. #define CONFIG_MCFTMR
  9. #define CONFIG_MCFUART
  10. #define CONFIG_SYS_UART_PORT (0)
  11. #undef CONFIG_WATCHDOG /* disable watchdog */
  12. /* Configuration for environment
  13. * Environment is embedded in u-boot in the second sector of the flash
  14. */
  15. #define LDS_BOARD_TEXT \
  16. . = DEFINED(env_offset) ? env_offset : .; \
  17. env/embedded.o(.text*);
  18. /*
  19. * Command line configuration.
  20. */
  21. #ifdef CONFIG_IDE
  22. /* ATA */
  23. # define CONFIG_IDE_RESET 1
  24. # define CONFIG_IDE_PREINIT 1
  25. # define CONFIG_ATAPI
  26. # undef CONFIG_LBA48
  27. # define CONFIG_SYS_IDE_MAXBUS 1
  28. # define CONFIG_SYS_IDE_MAXDEVICE 2
  29. # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
  30. # define CONFIG_SYS_ATA_IDE0_OFFSET 0
  31. # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
  32. # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
  33. # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
  34. # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
  35. #endif
  36. #define CONFIG_DRIVER_DM9000
  37. #ifdef CONFIG_DRIVER_DM9000
  38. # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
  39. # define DM9000_IO CONFIG_DM9000_BASE
  40. # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
  41. # undef CONFIG_DM9000_DEBUG
  42. # define CONFIG_DM9000_BYTE_SWAPPED
  43. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  44. # define CONFIG_EXTRA_ENV_SETTINGS \
  45. "netdev=eth0\0" \
  46. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  47. "loadaddr=10000\0" \
  48. "u-boot=u-boot.bin\0" \
  49. "load=tftp ${loadaddr) ${u-boot}\0" \
  50. "upd=run load; run prog\0" \
  51. "prog=prot off 0xff800000 0xff82ffff;" \
  52. "era 0xff800000 0xff82ffff;" \
  53. "cp.b ${loadaddr} 0xff800000 ${filesize};" \
  54. "save\0" \
  55. ""
  56. #endif
  57. #define CONFIG_HOSTNAME "M5253DEMO"
  58. /* I2C */
  59. #define CONFIG_SYS_I2C
  60. #define CONFIG_SYS_I2C_FSL
  61. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  62. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  63. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
  64. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  65. #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
  66. #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
  67. #define CONFIG_SYS_I2C_PINMUX_SET (0)
  68. #define CONFIG_SYS_LOAD_ADDR 0x00100000
  69. #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
  70. #define CONFIG_SYS_FAST_CLK
  71. #ifdef CONFIG_SYS_FAST_CLK
  72. # define CONFIG_SYS_PLLCR 0x1243E054
  73. # define CONFIG_SYS_CLK 140000000
  74. #else
  75. # define CONFIG_SYS_PLLCR 0x135a4140
  76. # define CONFIG_SYS_CLK 70000000
  77. #endif
  78. /*
  79. * Low Level Configuration Settings
  80. * (address mappings, register initial values, etc.)
  81. * You should know what you are doing if you make changes here.
  82. */
  83. #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
  84. #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
  85. /*
  86. * Definitions for initial stack pointer and data area (in DPRAM)
  87. */
  88. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  89. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
  90. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  91. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  92. /*
  93. * Start addresses for the final memory configuration
  94. * (Set up by the startup code)
  95. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  96. */
  97. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  98. #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
  99. #ifdef CONFIG_MONITOR_IS_IN_RAM
  100. # define CONFIG_SYS_MONITOR_BASE 0x20000
  101. #else
  102. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  103. #endif
  104. #define CONFIG_SYS_MONITOR_LEN 0x40000
  105. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  106. #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
  107. /*
  108. * For booting Linux, the board info and command line data
  109. * have to be in the first 8 MB of memory, since this is
  110. * the maximum mapped by the Linux kernel during initialization ??
  111. */
  112. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  113. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  114. /* FLASH organization */
  115. #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  116. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  117. #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
  118. #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
  119. #define FLASH_SST6401B 0x200
  120. #define SST_ID_xF6401B 0x236D236D
  121. #ifdef CONFIG_SYS_FLASH_CFI
  122. /*
  123. * Unable to use CFI driver, due to incompatible sector erase command by SST.
  124. * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
  125. * 0x30 is block erase in SST
  126. */
  127. # define CONFIG_SYS_FLASH_SIZE 0x800000
  128. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  129. # define CONFIG_FLASH_CFI_LEGACY
  130. #else
  131. # define CONFIG_SYS_SST_SECT 2048
  132. # define CONFIG_SYS_SST_SECTSZ 0x1000
  133. # define CONFIG_SYS_FLASH_WRITE_TOUT 500
  134. #endif
  135. /* Cache Configuration */
  136. #define CONFIG_SYS_CACHELINE_SIZE 16
  137. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  138. CONFIG_SYS_INIT_RAM_SIZE - 8)
  139. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  140. CONFIG_SYS_INIT_RAM_SIZE - 4)
  141. #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
  142. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
  143. CF_ADDRMASK(8) | \
  144. CF_ACR_EN | CF_ACR_SM_ALL)
  145. #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
  146. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  147. CF_ACR_EN | CF_ACR_SM_ALL)
  148. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
  149. CF_CACR_DBWE)
  150. /* Port configuration */
  151. #define CONFIG_SYS_FECI2C 0xF0
  152. #define CONFIG_SYS_CS0_BASE 0xFF800000
  153. #define CONFIG_SYS_CS0_MASK 0x007F0021
  154. #define CONFIG_SYS_CS0_CTRL 0x00001D80
  155. #define CONFIG_SYS_CS1_BASE 0xE0000000
  156. #define CONFIG_SYS_CS1_MASK 0x00000001
  157. #define CONFIG_SYS_CS1_CTRL 0x00003DD8
  158. /*-----------------------------------------------------------------------
  159. * Port configuration
  160. */
  161. #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
  162. #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
  163. #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
  164. #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
  165. #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
  166. #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
  167. #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
  168. #endif /* _M5253DEMO_H */