C29XPCIE.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * C29XPCIE board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <linux/stringify.h>
  11. #ifdef CONFIG_SPIFLASH
  12. #define CONFIG_RAMBOOT_SPIFLASH
  13. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  14. #endif
  15. #ifdef CONFIG_MTD_RAW_NAND
  16. #ifdef CONFIG_TPL_BUILD
  17. #define CONFIG_SPL_FLUSH_IMAGE
  18. #define CONFIG_SPL_NAND_INIT
  19. #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
  20. #define CONFIG_SPL_COMMON_INIT_DDR
  21. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  22. #define CONFIG_TPL_TEXT_BASE 0xf8f81000
  23. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  24. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  25. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  26. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  27. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  28. #elif defined(CONFIG_SPL_BUILD)
  29. #define CONFIG_SPL_INIT_MINIMAL
  30. #define CONFIG_SPL_NAND_MINIMAL
  31. #define CONFIG_SPL_FLUSH_IMAGE
  32. #define CONFIG_SPL_MAX_SIZE 8192
  33. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  34. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  35. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  36. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  37. #endif
  38. #define CONFIG_SPL_PAD_TO 0x20000
  39. #define CONFIG_TPL_PAD_TO 0x20000
  40. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  41. #endif
  42. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  43. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  44. #endif
  45. #ifdef CONFIG_TPL_BUILD
  46. #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
  47. #elif defined(CONFIG_SPL_BUILD)
  48. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  49. #else
  50. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  51. #endif
  52. #ifdef CONFIG_SPL_BUILD
  53. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  54. #endif
  55. /* High Level Configuration Options */
  56. #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
  57. #ifdef CONFIG_PCI
  58. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  59. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  60. #define CONFIG_PCI_INDIRECT_BRIDGE
  61. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  62. /*
  63. * PCI Windows
  64. * Memory space is mapped 1-1, but I/O space must start from 0.
  65. */
  66. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  67. #define CONFIG_SYS_PCIE1_NAME "Slot 1"
  68. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  69. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  70. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  71. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  72. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  73. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  74. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  75. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  76. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  77. #endif
  78. #define CONFIG_ENV_OVERWRITE
  79. #define CONFIG_DDR_CLK_FREQ 100000000
  80. #define CONFIG_SYS_CLK_FREQ 66666666
  81. #define CONFIG_HWCONFIG
  82. /*
  83. * These can be toggled for performance analysis, otherwise use default.
  84. */
  85. #define CONFIG_L2_CACHE /* toggle L2 cache */
  86. #define CONFIG_BTB /* toggle branch predition */
  87. #define CONFIG_ENABLE_36BIT_PHYS
  88. #define CONFIG_ADDR_MAP 1
  89. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  90. /* DDR Setup */
  91. #define CONFIG_DDR_SPD
  92. #define CONFIG_SYS_SPD_BUS_NUM 0
  93. #define SPD_EEPROM_ADDRESS 0x50
  94. #define CONFIG_SYS_DDR_RAW_TIMING
  95. /* DDR ECC Setup*/
  96. #define CONFIG_DDR_ECC
  97. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  98. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  99. #define CONFIG_SYS_SDRAM_SIZE 512
  100. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  101. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  102. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  103. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  104. #define CONFIG_SYS_CCSRBAR 0xffe00000
  105. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  106. /* Platform SRAM setting */
  107. #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
  108. #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
  109. (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
  110. #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
  111. /*
  112. * IFC Definitions
  113. */
  114. /* NOR Flash on IFC */
  115. #define CONFIG_SYS_FLASH_BASE 0xec000000
  116. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  117. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  118. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
  119. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  120. #define CONFIG_SYS_FLASH_QUIET_TEST
  121. #define CONFIG_FLASH_SHOW_PROGRESS 45
  122. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
  123. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
  124. /* 16Bit NOR Flash - S29GL512S10TFI01 */
  125. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  126. CSPR_PORT_SIZE_16 | \
  127. CSPR_MSEL_NOR | \
  128. CSPR_V)
  129. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
  130. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
  131. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  132. FTIM0_NOR_TEADC(0x5) | \
  133. FTIM0_NOR_TEAHC(0x5))
  134. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  135. FTIM1_NOR_TRAD_NOR(0x1A) |\
  136. FTIM1_NOR_TSEQRAD_NOR(0x13))
  137. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  138. FTIM2_NOR_TCH(0x4) | \
  139. FTIM2_NOR_TWPH(0x0E) | \
  140. FTIM2_NOR_TWP(0x1c))
  141. #define CONFIG_SYS_NOR_FTIM3 0x0
  142. /* CFI for NOR Flash */
  143. #define CONFIG_SYS_FLASH_EMPTY_INFO
  144. /* NAND Flash on IFC */
  145. #define CONFIG_NAND_FSL_IFC
  146. #define CONFIG_SYS_NAND_BASE 0xff800000
  147. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  148. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  149. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  150. #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
  151. /* 8Bit NAND Flash - K9F1G08U0B */
  152. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  153. | CSPR_PORT_SIZE_8 \
  154. | CSPR_MSEL_NAND \
  155. | CSPR_V)
  156. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  157. #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
  158. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  159. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  160. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  161. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  162. | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
  163. | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
  164. | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
  165. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
  166. FTIM0_NAND_TWP(0x0c) | \
  167. FTIM0_NAND_TWCHT(0x08) | \
  168. FTIM0_NAND_TWH(0x06))
  169. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
  170. FTIM1_NAND_TWBE(0x1d) | \
  171. FTIM1_NAND_TRR(0x08) | \
  172. FTIM1_NAND_TRP(0x0c))
  173. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
  174. FTIM2_NAND_TREH(0x0a) | \
  175. FTIM2_NAND_TWHRE(0x18))
  176. #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
  177. #define CONFIG_SYS_NAND_DDR_LAW 11
  178. /* Set up IFC registers for boot location NOR/NAND */
  179. #ifdef CONFIG_MTD_RAW_NAND
  180. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  181. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  182. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  183. #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
  184. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  185. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  186. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  187. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  188. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  189. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  190. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  191. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  192. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  193. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  194. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  195. #else
  196. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  197. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  198. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  199. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  200. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  201. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  202. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  203. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  204. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  205. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  206. #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
  207. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  208. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  209. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  210. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  211. #endif
  212. /* CPLD on IFC, selected by CS2 */
  213. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  214. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
  215. | CONFIG_SYS_CPLD_BASE)
  216. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  217. | CSPR_PORT_SIZE_8 \
  218. | CSPR_MSEL_GPCM \
  219. | CSPR_V)
  220. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  221. #define CONFIG_SYS_CSOR2 0x0
  222. /* CPLD Timing parameters for IFC CS2 */
  223. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  224. FTIM0_GPCM_TEADC(0x0e) | \
  225. FTIM0_GPCM_TEAHC(0x0e))
  226. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  227. FTIM1_GPCM_TRAD(0x1f))
  228. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  229. FTIM2_GPCM_TCH(0x8) | \
  230. FTIM2_GPCM_TWP(0x1f))
  231. #define CONFIG_SYS_CS2_FTIM3 0x0
  232. #if defined(CONFIG_RAMBOOT_SPIFLASH)
  233. #define CONFIG_SYS_RAMBOOT
  234. #endif
  235. #define CONFIG_SYS_INIT_RAM_LOCK
  236. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
  237. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  238. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  239. - GENERATED_GBL_DATA_SIZE)
  240. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  241. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  242. #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
  243. /*
  244. * Config the L2 Cache as L2 SRAM
  245. */
  246. #if defined(CONFIG_SPL_BUILD)
  247. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  248. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  249. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  250. #define CONFIG_SYS_L2_SIZE (256 << 10)
  251. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  252. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  253. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
  254. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
  255. #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
  256. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  257. #elif defined(CONFIG_MTD_RAW_NAND)
  258. #ifdef CONFIG_TPL_BUILD
  259. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  260. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  261. #define CONFIG_SYS_L2_SIZE (256 << 10)
  262. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  263. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  264. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  265. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  266. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  267. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  268. #else
  269. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  270. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  271. #define CONFIG_SYS_L2_SIZE (256 << 10)
  272. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  273. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
  274. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  275. #endif
  276. #endif
  277. #endif
  278. /* Serial Port */
  279. #define CONFIG_SYS_NS16550_SERIAL
  280. #define CONFIG_SYS_NS16550_REG_SIZE 1
  281. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  282. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  283. #define CONFIG_NS16550_MIN_FUNCTIONS
  284. #endif
  285. #define CONFIG_SYS_BAUDRATE_TABLE \
  286. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  287. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  288. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  289. #define CONFIG_SYS_I2C
  290. #define CONFIG_SYS_I2C_FSL
  291. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  292. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  293. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  294. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  295. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  296. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  297. /* I2C EEPROM */
  298. /* enable read and write access to EEPROM */
  299. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  300. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  301. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  302. /* eSPI - Enhanced SPI */
  303. #ifdef CONFIG_TSEC_ENET
  304. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  305. #define CONFIG_TSEC1 1
  306. #define CONFIG_TSEC1_NAME "eTSEC1"
  307. #define CONFIG_TSEC2 1
  308. #define CONFIG_TSEC2_NAME "eTSEC2"
  309. /* Default mode is RGMII mode */
  310. #define TSEC1_PHY_ADDR 0
  311. #define TSEC2_PHY_ADDR 2
  312. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  313. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  314. #define CONFIG_ETHPRIME "eTSEC1"
  315. #endif /* CONFIG_TSEC_ENET */
  316. /*
  317. * Environment
  318. */
  319. #if defined(CONFIG_SYS_RAMBOOT)
  320. #elif defined(CONFIG_MTD_RAW_NAND)
  321. #ifdef CONFIG_TPL_BUILD
  322. #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  323. #else
  324. #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
  325. #endif
  326. #endif
  327. #define CONFIG_LOADS_ECHO
  328. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  329. /*
  330. * Miscellaneous configurable options
  331. */
  332. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  333. /*
  334. * For booting Linux, the board info and command line data
  335. * have to be in the first 64 MB of memory, since this is
  336. * the maximum mapped by the Linux kernel during initialization.
  337. */
  338. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  339. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  340. /*
  341. * Environment Configuration
  342. */
  343. #ifdef CONFIG_TSEC_ENET
  344. #define CONFIG_HAS_ETH0
  345. #define CONFIG_HAS_ETH1
  346. #endif
  347. #define CONFIG_ROOTPATH "/opt/nfsroot"
  348. #define CONFIG_BOOTFILE "uImage"
  349. #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
  350. /* default location for tftp and bootm */
  351. #define CONFIG_LOADADDR 1000000
  352. #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
  353. #define CONFIG_EXTRA_ENV_SETTINGS \
  354. "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
  355. "netdev=eth0\0" \
  356. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  357. "loadaddr=1000000\0" \
  358. "consoledev=ttyS0\0" \
  359. "ramdiskaddr=2000000\0" \
  360. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  361. "fdtaddr=1e00000\0" \
  362. "fdtfile=name/of/device-tree.dtb\0" \
  363. "othbootargs=ramdisk_size=600000\0" \
  364. #define CONFIG_RAMBOOTCOMMAND \
  365. "setenv bootargs root=/dev/ram rw " \
  366. "console=$consoledev,$baudrate $othbootargs; " \
  367. "tftp $ramdiskaddr $ramdiskfile;" \
  368. "tftp $loadaddr $bootfile;" \
  369. "tftp $fdtaddr $fdtfile;" \
  370. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  371. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  372. #include <asm/fsl_secure_boot.h>
  373. #endif /* __CONFIG_H */