clk_rk322x.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/cru_rk322x.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <dm/lists.h>
  17. #include <dt-bindings/clock/rk3228-cru.h>
  18. #include <linux/log2.h>
  19. #include <linux/stringify.h>
  20. enum {
  21. VCO_MAX_HZ = 3200U * 1000000,
  22. VCO_MIN_HZ = 800 * 1000000,
  23. OUTPUT_MAX_HZ = 3200U * 1000000,
  24. OUTPUT_MIN_HZ = 24 * 1000000,
  25. };
  26. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  27. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  28. .refdiv = _refdiv,\
  29. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
  30. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
  31. _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
  32. OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
  33. #hz "Hz cannot be hit with PLL "\
  34. "divisors on line " __stringify(__LINE__));
  35. /* use integer mode*/
  36. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  37. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  38. static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
  39. const struct pll_div *div)
  40. {
  41. int pll_id = rk_pll_id(clk_id);
  42. struct rk322x_pll *pll = &cru->pll[pll_id];
  43. /* All PLLs have same VCO and output frequency range restrictions. */
  44. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  45. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  46. debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
  47. pll, div->fbdiv, div->refdiv, div->postdiv1,
  48. div->postdiv2, vco_hz, output_hz);
  49. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  50. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  51. /* use integer mode */
  52. rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  53. /* Power down */
  54. rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
  55. rk_clrsetreg(&pll->con0,
  56. PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  57. (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  58. rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  59. (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  60. div->refdiv << PLL_REFDIV_SHIFT));
  61. /* Power Up */
  62. rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
  63. /* waiting for pll lock */
  64. while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  65. udelay(1);
  66. return 0;
  67. }
  68. static void rkclk_init(struct rk322x_cru *cru)
  69. {
  70. u32 aclk_div;
  71. u32 hclk_div;
  72. u32 pclk_div;
  73. /* pll enter slow-mode */
  74. rk_clrsetreg(&cru->cru_mode_con,
  75. GPLL_MODE_MASK | APLL_MODE_MASK,
  76. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  77. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  78. /* init pll */
  79. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  80. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  81. /*
  82. * select apll as cpu/core clock pll source and
  83. * set up dependent divisors for PERI and ACLK clocks.
  84. * core hz : apll = 1:1
  85. */
  86. aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
  87. assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
  88. pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
  89. assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
  90. rk_clrsetreg(&cru->cru_clksel_con[0],
  91. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
  92. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  93. 0 << CORE_DIV_CON_SHIFT);
  94. rk_clrsetreg(&cru->cru_clksel_con[1],
  95. CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
  96. aclk_div << CORE_ACLK_DIV_SHIFT |
  97. pclk_div << CORE_PERI_DIV_SHIFT);
  98. /*
  99. * select gpll as pd_bus bus clock source and
  100. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  101. */
  102. aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
  103. assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  104. pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
  105. assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
  106. hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
  107. assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
  108. rk_clrsetreg(&cru->cru_clksel_con[0],
  109. BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  110. BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
  111. aclk_div << BUS_ACLK_DIV_SHIFT);
  112. rk_clrsetreg(&cru->cru_clksel_con[1],
  113. BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
  114. pclk_div << BUS_PCLK_DIV_SHIFT |
  115. hclk_div << BUS_HCLK_DIV_SHIFT);
  116. /*
  117. * select gpll as pd_peri bus clock source and
  118. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  119. */
  120. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  121. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  122. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  123. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  124. PERI_ACLK_HZ && (hclk_div < 0x4));
  125. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  126. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  127. PERI_ACLK_HZ && pclk_div < 0x8);
  128. rk_clrsetreg(&cru->cru_clksel_con[10],
  129. PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
  130. PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
  131. PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
  132. pclk_div << PERI_PCLK_DIV_SHIFT |
  133. hclk_div << PERI_HCLK_DIV_SHIFT |
  134. aclk_div << PERI_ACLK_DIV_SHIFT);
  135. /* PLL enter normal-mode */
  136. rk_clrsetreg(&cru->cru_mode_con,
  137. GPLL_MODE_MASK | APLL_MODE_MASK,
  138. GPLL_MODE_NORM << GPLL_MODE_SHIFT |
  139. APLL_MODE_NORM << APLL_MODE_SHIFT);
  140. }
  141. /* Get pll rate by id */
  142. static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
  143. enum rk_clk_id clk_id)
  144. {
  145. uint32_t refdiv, fbdiv, postdiv1, postdiv2;
  146. uint32_t con;
  147. int pll_id = rk_pll_id(clk_id);
  148. struct rk322x_pll *pll = &cru->pll[pll_id];
  149. static u8 clk_shift[CLK_COUNT] = {
  150. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
  151. GPLL_MODE_SHIFT, 0xff
  152. };
  153. static u32 clk_mask[CLK_COUNT] = {
  154. 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
  155. GPLL_MODE_MASK, 0xff
  156. };
  157. uint shift;
  158. uint mask;
  159. con = readl(&cru->cru_mode_con);
  160. shift = clk_shift[clk_id];
  161. mask = clk_mask[clk_id];
  162. switch ((con & mask) >> shift) {
  163. case GPLL_MODE_SLOW:
  164. return OSC_HZ;
  165. case GPLL_MODE_NORM:
  166. /* normal mode */
  167. con = readl(&pll->con0);
  168. postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
  169. fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
  170. con = readl(&pll->con1);
  171. postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
  172. refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
  173. return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  174. default:
  175. return 32768;
  176. }
  177. }
  178. static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
  179. int periph)
  180. {
  181. uint src_rate;
  182. uint div, mux;
  183. u32 con;
  184. switch (periph) {
  185. case HCLK_EMMC:
  186. case SCLK_EMMC:
  187. case SCLK_EMMC_SAMPLE:
  188. con = readl(&cru->cru_clksel_con[11]);
  189. mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  190. con = readl(&cru->cru_clksel_con[12]);
  191. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  192. break;
  193. case HCLK_SDMMC:
  194. case SCLK_SDMMC:
  195. con = readl(&cru->cru_clksel_con[11]);
  196. mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  197. div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  198. break;
  199. default:
  200. return -EINVAL;
  201. }
  202. src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
  203. return DIV_TO_RATE(src_rate, div) / 2;
  204. }
  205. static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
  206. {
  207. ulong ret;
  208. /*
  209. * The gmac clock can be derived either from an external clock
  210. * or can be generated from internally by a divider from SCLK_MAC.
  211. */
  212. if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
  213. /* An external clock will always generate the right rate... */
  214. ret = freq;
  215. } else {
  216. u32 con = readl(&cru->cru_clksel_con[5]);
  217. ulong pll_rate;
  218. u8 div;
  219. if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
  220. pll_rate = GPLL_HZ;
  221. else
  222. /* CPLL is not set */
  223. return -EPERM;
  224. div = DIV_ROUND_UP(pll_rate, freq) - 1;
  225. if (div <= 0x1f)
  226. rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
  227. div << CLK_MAC_DIV_SHIFT);
  228. else
  229. debug("Unsupported div for gmac:%d\n", div);
  230. return DIV_TO_RATE(pll_rate, div);
  231. }
  232. return ret;
  233. }
  234. static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
  235. int periph, uint freq)
  236. {
  237. int src_clk_div;
  238. int mux;
  239. debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
  240. /* mmc clock defaulg div 2 internal, need provide double in cru */
  241. src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
  242. if (src_clk_div > 128) {
  243. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
  244. assert(src_clk_div - 1 < 128);
  245. mux = EMMC_SEL_24M;
  246. } else {
  247. mux = EMMC_SEL_GPLL;
  248. }
  249. switch (periph) {
  250. case HCLK_EMMC:
  251. case SCLK_EMMC:
  252. case SCLK_EMMC_SAMPLE:
  253. rk_clrsetreg(&cru->cru_clksel_con[11],
  254. EMMC_PLL_MASK,
  255. mux << EMMC_PLL_SHIFT);
  256. rk_clrsetreg(&cru->cru_clksel_con[12],
  257. EMMC_DIV_MASK,
  258. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  259. break;
  260. case HCLK_SDMMC:
  261. case SCLK_SDMMC:
  262. rk_clrsetreg(&cru->cru_clksel_con[11],
  263. MMC0_PLL_MASK | MMC0_DIV_MASK,
  264. mux << MMC0_PLL_SHIFT |
  265. (src_clk_div - 1) << MMC0_DIV_SHIFT);
  266. break;
  267. default:
  268. return -EINVAL;
  269. }
  270. return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
  271. }
  272. static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
  273. {
  274. struct pll_div dpll_cfg;
  275. /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
  276. switch (set_rate) {
  277. case 400*MHz:
  278. dpll_cfg = (struct pll_div)
  279. {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
  280. break;
  281. case 600*MHz:
  282. dpll_cfg = (struct pll_div)
  283. {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
  284. break;
  285. case 800*MHz:
  286. dpll_cfg = (struct pll_div)
  287. {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
  288. break;
  289. }
  290. /* pll enter slow-mode */
  291. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
  292. DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
  293. rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
  294. /* PLL enter normal-mode */
  295. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
  296. DPLL_MODE_NORM << DPLL_MODE_SHIFT);
  297. return set_rate;
  298. }
  299. static ulong rk322x_clk_get_rate(struct clk *clk)
  300. {
  301. struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
  302. ulong rate, gclk_rate;
  303. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  304. switch (clk->id) {
  305. case 0 ... 63:
  306. rate = rkclk_pll_get_rate(priv->cru, clk->id);
  307. break;
  308. case HCLK_EMMC:
  309. case SCLK_EMMC:
  310. case HCLK_SDMMC:
  311. case SCLK_SDMMC:
  312. rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
  313. break;
  314. default:
  315. return -ENOENT;
  316. }
  317. return rate;
  318. }
  319. static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
  320. {
  321. struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
  322. ulong new_rate, gclk_rate;
  323. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  324. switch (clk->id) {
  325. case HCLK_EMMC:
  326. case SCLK_EMMC:
  327. case HCLK_SDMMC:
  328. case SCLK_SDMMC:
  329. new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
  330. clk->id, rate);
  331. break;
  332. case CLK_DDR:
  333. new_rate = rk322x_ddr_set_clk(priv->cru, rate);
  334. break;
  335. case SCLK_MAC:
  336. new_rate = rk322x_mac_set_clk(priv->cru, rate);
  337. break;
  338. case PLL_GPLL:
  339. return 0;
  340. default:
  341. return -ENOENT;
  342. }
  343. return new_rate;
  344. }
  345. static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
  346. {
  347. struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
  348. struct rk322x_cru *cru = priv->cru;
  349. /*
  350. * If the requested parent is in the same clock-controller and the id
  351. * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
  352. */
  353. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
  354. debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
  355. rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
  356. return 0;
  357. }
  358. /*
  359. * If the requested parent is in the same clock-controller and the id
  360. * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
  361. */
  362. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
  363. debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
  364. rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
  365. return 0;
  366. }
  367. return -EINVAL;
  368. }
  369. static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
  370. {
  371. struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
  372. const char *clock_output_name;
  373. struct rk322x_cru *cru = priv->cru;
  374. int ret;
  375. ret = dev_read_string_index(parent->dev, "clock-output-names",
  376. parent->id, &clock_output_name);
  377. if (ret < 0)
  378. return -ENODATA;
  379. if (!strcmp(clock_output_name, "ext_gmac")) {
  380. debug("%s: switching gmac extclk to ext_gmac\n", __func__);
  381. rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
  382. return 0;
  383. } else if (!strcmp(clock_output_name, "phy_50m_out")) {
  384. debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
  385. rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
  386. return 0;
  387. }
  388. return -EINVAL;
  389. }
  390. static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
  391. {
  392. switch (clk->id) {
  393. case SCLK_MAC:
  394. return rk322x_gmac_set_parent(clk, parent);
  395. case SCLK_MAC_EXTCLK:
  396. return rk322x_gmac_extclk_set_parent(clk, parent);
  397. }
  398. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  399. return -ENOENT;
  400. }
  401. static struct clk_ops rk322x_clk_ops = {
  402. .get_rate = rk322x_clk_get_rate,
  403. .set_rate = rk322x_clk_set_rate,
  404. .set_parent = rk322x_clk_set_parent,
  405. };
  406. static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
  407. {
  408. struct rk322x_clk_priv *priv = dev_get_priv(dev);
  409. priv->cru = dev_read_addr_ptr(dev);
  410. return 0;
  411. }
  412. static int rk322x_clk_probe(struct udevice *dev)
  413. {
  414. struct rk322x_clk_priv *priv = dev_get_priv(dev);
  415. rkclk_init(priv->cru);
  416. return 0;
  417. }
  418. static int rk322x_clk_bind(struct udevice *dev)
  419. {
  420. int ret;
  421. struct udevice *sys_child;
  422. struct sysreset_reg *priv;
  423. /* The reset driver does not have a device node, so bind it here */
  424. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  425. &sys_child);
  426. if (ret) {
  427. debug("Warning: No sysreset driver: ret=%d\n", ret);
  428. } else {
  429. priv = malloc(sizeof(struct sysreset_reg));
  430. priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
  431. cru_glb_srst_fst_value);
  432. priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
  433. cru_glb_srst_snd_value);
  434. sys_child->priv = priv;
  435. }
  436. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  437. ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
  438. ret = rockchip_reset_bind(dev, ret, 9);
  439. if (ret)
  440. debug("Warning: software reset driver bind faile\n");
  441. #endif
  442. return 0;
  443. }
  444. static const struct udevice_id rk322x_clk_ids[] = {
  445. { .compatible = "rockchip,rk3228-cru" },
  446. { }
  447. };
  448. U_BOOT_DRIVER(rockchip_rk322x_cru) = {
  449. .name = "clk_rk322x",
  450. .id = UCLASS_CLK,
  451. .of_match = rk322x_clk_ids,
  452. .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
  453. .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
  454. .ops = &rk322x_clk_ops,
  455. .bind = rk322x_clk_bind,
  456. .probe = rk322x_clk_probe,
  457. };