clk_rk3036.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/cru_rk3036.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <dm/lists.h>
  17. #include <dt-bindings/clock/rk3036-cru.h>
  18. #include <linux/log2.h>
  19. #include <linux/stringify.h>
  20. enum {
  21. VCO_MAX_HZ = 2400U * 1000000,
  22. VCO_MIN_HZ = 600 * 1000000,
  23. OUTPUT_MAX_HZ = 2400U * 1000000,
  24. OUTPUT_MIN_HZ = 24 * 1000000,
  25. };
  26. #define RATE_TO_DIV(input_rate, output_rate) \
  27. ((input_rate) / (output_rate) - 1);
  28. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  29. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  30. .refdiv = _refdiv,\
  31. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  32. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
  33. _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
  34. OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
  35. #hz "Hz cannot be hit with PLL "\
  36. "divisors on line " __stringify(__LINE__));
  37. /* use integer mode*/
  38. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  39. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  40. static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
  41. const struct pll_div *div)
  42. {
  43. int pll_id = rk_pll_id(clk_id);
  44. struct rk3036_pll *pll = &cru->pll[pll_id];
  45. /* All PLLs have same VCO and output frequency range restrictions. */
  46. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  47. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  48. debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
  49. vco=%u Hz, output=%u Hz\n",
  50. pll, div->fbdiv, div->refdiv, div->postdiv1,
  51. div->postdiv2, vco_hz, output_hz);
  52. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  53. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  54. /* use integer mode */
  55. rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  56. rk_clrsetreg(&pll->con0,
  57. PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  58. (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  59. rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  60. (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  61. div->refdiv << PLL_REFDIV_SHIFT));
  62. /* waiting for pll lock */
  63. while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  64. udelay(1);
  65. return 0;
  66. }
  67. static void rkclk_init(struct rk3036_cru *cru)
  68. {
  69. u32 aclk_div;
  70. u32 hclk_div;
  71. u32 pclk_div;
  72. /* pll enter slow-mode */
  73. rk_clrsetreg(&cru->cru_mode_con,
  74. GPLL_MODE_MASK | APLL_MODE_MASK,
  75. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  76. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  77. /* init pll */
  78. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  79. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  80. /*
  81. * select apll as cpu/core clock pll source and
  82. * set up dependent divisors for PERI and ACLK clocks.
  83. * core hz : apll = 1:1
  84. */
  85. aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
  86. assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
  87. pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
  88. assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
  89. rk_clrsetreg(&cru->cru_clksel_con[0],
  90. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
  91. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  92. 0 << CORE_DIV_CON_SHIFT);
  93. rk_clrsetreg(&cru->cru_clksel_con[1],
  94. CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
  95. aclk_div << CORE_ACLK_DIV_SHIFT |
  96. pclk_div << CORE_PERI_DIV_SHIFT);
  97. /*
  98. * select apll as pd_bus bus clock source and
  99. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  100. */
  101. aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
  102. assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  103. pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
  104. assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
  105. hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
  106. assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
  107. rk_clrsetreg(&cru->cru_clksel_con[0],
  108. BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  109. BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
  110. aclk_div << BUS_ACLK_DIV_SHIFT);
  111. rk_clrsetreg(&cru->cru_clksel_con[1],
  112. BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
  113. pclk_div << BUS_PCLK_DIV_SHIFT |
  114. hclk_div << BUS_HCLK_DIV_SHIFT);
  115. /*
  116. * select gpll as pd_peri bus clock source and
  117. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  118. */
  119. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  120. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  121. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  122. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  123. PERI_ACLK_HZ && (hclk_div < 0x4));
  124. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  125. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  126. PERI_ACLK_HZ && pclk_div < 0x8);
  127. rk_clrsetreg(&cru->cru_clksel_con[10],
  128. PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
  129. PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
  130. PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
  131. pclk_div << PERI_PCLK_DIV_SHIFT |
  132. hclk_div << PERI_HCLK_DIV_SHIFT |
  133. aclk_div << PERI_ACLK_DIV_SHIFT);
  134. /* PLL enter normal-mode */
  135. rk_clrsetreg(&cru->cru_mode_con,
  136. GPLL_MODE_MASK | APLL_MODE_MASK,
  137. GPLL_MODE_NORM << GPLL_MODE_SHIFT |
  138. APLL_MODE_NORM << APLL_MODE_SHIFT);
  139. }
  140. /* Get pll rate by id */
  141. static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
  142. enum rk_clk_id clk_id)
  143. {
  144. uint32_t refdiv, fbdiv, postdiv1, postdiv2;
  145. uint32_t con;
  146. int pll_id = rk_pll_id(clk_id);
  147. struct rk3036_pll *pll = &cru->pll[pll_id];
  148. static u8 clk_shift[CLK_COUNT] = {
  149. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
  150. GPLL_MODE_SHIFT, 0xff
  151. };
  152. static u32 clk_mask[CLK_COUNT] = {
  153. 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
  154. GPLL_MODE_MASK, 0xffffffff
  155. };
  156. uint shift;
  157. uint mask;
  158. con = readl(&cru->cru_mode_con);
  159. shift = clk_shift[clk_id];
  160. mask = clk_mask[clk_id];
  161. switch ((con & mask) >> shift) {
  162. case GPLL_MODE_SLOW:
  163. return OSC_HZ;
  164. case GPLL_MODE_NORM:
  165. /* normal mode */
  166. con = readl(&pll->con0);
  167. postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
  168. fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
  169. con = readl(&pll->con1);
  170. postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
  171. refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
  172. return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  173. case GPLL_MODE_DEEP:
  174. default:
  175. return 32768;
  176. }
  177. }
  178. static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
  179. int periph)
  180. {
  181. uint src_rate;
  182. uint div, mux;
  183. u32 con;
  184. switch (periph) {
  185. case HCLK_EMMC:
  186. case SCLK_EMMC:
  187. con = readl(&cru->cru_clksel_con[12]);
  188. mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  189. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  190. break;
  191. case HCLK_SDIO:
  192. case SCLK_SDIO:
  193. con = readl(&cru->cru_clksel_con[12]);
  194. mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  195. div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  196. break;
  197. default:
  198. return -EINVAL;
  199. }
  200. src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
  201. return DIV_TO_RATE(src_rate, div) / 2;
  202. }
  203. static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
  204. int periph, uint freq)
  205. {
  206. int src_clk_div;
  207. int mux;
  208. debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
  209. /* mmc clock auto divide 2 in internal */
  210. src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
  211. if (src_clk_div > 128) {
  212. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
  213. assert(src_clk_div - 1 < 128);
  214. mux = EMMC_SEL_24M;
  215. } else {
  216. mux = EMMC_SEL_GPLL;
  217. }
  218. switch (periph) {
  219. case HCLK_EMMC:
  220. case SCLK_EMMC:
  221. rk_clrsetreg(&cru->cru_clksel_con[12],
  222. EMMC_PLL_MASK | EMMC_DIV_MASK,
  223. mux << EMMC_PLL_SHIFT |
  224. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  225. break;
  226. case HCLK_SDIO:
  227. case SCLK_SDIO:
  228. rk_clrsetreg(&cru->cru_clksel_con[11],
  229. MMC0_PLL_MASK | MMC0_DIV_MASK,
  230. mux << MMC0_PLL_SHIFT |
  231. (src_clk_div - 1) << MMC0_DIV_SHIFT);
  232. break;
  233. default:
  234. return -EINVAL;
  235. }
  236. return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
  237. }
  238. static ulong rk3036_clk_get_rate(struct clk *clk)
  239. {
  240. struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
  241. switch (clk->id) {
  242. case 0 ... 63:
  243. return rkclk_pll_get_rate(priv->cru, clk->id);
  244. default:
  245. return -ENOENT;
  246. }
  247. }
  248. static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
  249. {
  250. struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
  251. ulong new_rate, gclk_rate;
  252. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  253. switch (clk->id) {
  254. case 0 ... 63:
  255. return 0;
  256. case HCLK_EMMC:
  257. case SCLK_EMMC:
  258. new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
  259. clk->id, rate);
  260. break;
  261. default:
  262. return -ENOENT;
  263. }
  264. return new_rate;
  265. }
  266. static struct clk_ops rk3036_clk_ops = {
  267. .get_rate = rk3036_clk_get_rate,
  268. .set_rate = rk3036_clk_set_rate,
  269. };
  270. static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
  271. {
  272. struct rk3036_clk_priv *priv = dev_get_priv(dev);
  273. priv->cru = dev_read_addr_ptr(dev);
  274. return 0;
  275. }
  276. static int rk3036_clk_probe(struct udevice *dev)
  277. {
  278. struct rk3036_clk_priv *priv = dev_get_priv(dev);
  279. rkclk_init(priv->cru);
  280. return 0;
  281. }
  282. static int rk3036_clk_bind(struct udevice *dev)
  283. {
  284. int ret;
  285. struct udevice *sys_child;
  286. struct sysreset_reg *priv;
  287. /* The reset driver does not have a device node, so bind it here */
  288. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  289. &sys_child);
  290. if (ret) {
  291. debug("Warning: No sysreset driver: ret=%d\n", ret);
  292. } else {
  293. priv = malloc(sizeof(struct sysreset_reg));
  294. priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
  295. cru_glb_srst_fst_value);
  296. priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
  297. cru_glb_srst_snd_value);
  298. sys_child->priv = priv;
  299. }
  300. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  301. ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
  302. ret = rockchip_reset_bind(dev, ret, 9);
  303. if (ret)
  304. debug("Warning: software reset driver bind faile\n");
  305. #endif
  306. return 0;
  307. }
  308. static const struct udevice_id rk3036_clk_ids[] = {
  309. { .compatible = "rockchip,rk3036-cru" },
  310. { }
  311. };
  312. U_BOOT_DRIVER(rockchip_rk3036_cru) = {
  313. .name = "clk_rk3036",
  314. .id = UCLASS_CLK,
  315. .of_match = rk3036_clk_ids,
  316. .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
  317. .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
  318. .ops = &rk3036_clk_ops,
  319. .bind = rk3036_clk_bind,
  320. .probe = rk3036_clk_probe,
  321. };