at91sam9n12_devices.c 5.0 KB

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  1. /*
  2. * (C) Copyright 2013 Atmel Corporation
  3. * Josh Wu <josh.wu@atmel.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/at91_common.h>
  10. #include <asm/arch/at91_pmc.h>
  11. #include <asm/arch/at91_pio.h>
  12. unsigned int has_lcdc()
  13. {
  14. return 1;
  15. }
  16. void at91_serial0_hw_init(void)
  17. {
  18. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  19. at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
  20. at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
  21. writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  22. }
  23. void at91_serial1_hw_init(void)
  24. {
  25. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  26. at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
  27. at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
  28. writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  29. }
  30. void at91_serial2_hw_init(void)
  31. {
  32. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  33. at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
  34. at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
  35. writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  36. }
  37. void at91_serial3_hw_init(void)
  38. {
  39. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  40. at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
  41. at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
  42. writel(1 << ATMEL_ID_USART3, &pmc->pcer);
  43. }
  44. void at91_seriald_hw_init(void)
  45. {
  46. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  47. at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
  48. at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
  49. writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  50. }
  51. #ifdef CONFIG_ATMEL_SPI
  52. void at91_spi0_hw_init(unsigned long cs_mask)
  53. {
  54. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  55. at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
  56. at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
  57. at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
  58. /* Enable clock */
  59. writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  60. if (cs_mask & (1 << 0))
  61. at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
  62. if (cs_mask & (1 << 1))
  63. at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
  64. if (cs_mask & (1 << 2))
  65. at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
  66. if (cs_mask & (1 << 3))
  67. at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
  68. }
  69. void at91_spi1_hw_init(unsigned long cs_mask)
  70. {
  71. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  72. at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
  73. at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
  74. at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
  75. /* Enable clock */
  76. writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
  77. if (cs_mask & (1 << 0))
  78. at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
  79. if (cs_mask & (1 << 1))
  80. at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
  81. if (cs_mask & (1 << 2))
  82. at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
  83. if (cs_mask & (1 << 3))
  84. at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
  85. }
  86. #endif
  87. void at91_mci_hw_init(void)
  88. {
  89. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  90. at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
  91. at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
  92. at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
  93. at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
  94. at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
  95. at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
  96. writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
  97. }
  98. #ifdef CONFIG_LCD
  99. void at91_lcd_hw_init(void)
  100. {
  101. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  102. at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
  103. at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
  104. at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
  105. at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
  106. at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
  107. at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
  108. at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
  109. at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
  110. at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
  111. at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
  112. at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
  113. at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
  114. at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
  115. at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
  116. at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
  117. at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
  118. at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
  119. at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
  120. at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
  121. at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
  122. at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
  123. at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
  124. at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
  125. at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
  126. at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
  127. at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
  128. at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
  129. at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
  130. at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
  131. at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
  132. writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  133. }
  134. #endif