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  1. /*
  2. * armboot - Startup Code for ARM925 CPU-core
  3. *
  4. * Copyright (c) 2003 Texas Instruments
  5. *
  6. * ----- Adapted for OMAP1510 from ARM920 code ------
  7. *
  8. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  9. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  10. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  11. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  12. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  13. *
  14. * SPDX-License-Identifier: GPL-2.0+
  15. */
  16. #include <asm-offsets.h>
  17. #include <config.h>
  18. #include <version.h>
  19. /*
  20. *************************************************************************
  21. *
  22. * Jump vector table as in table 3.1 in [1]
  23. *
  24. *************************************************************************
  25. */
  26. .globl _start
  27. _start: b reset
  28. ldr pc, _undefined_instruction
  29. ldr pc, _software_interrupt
  30. ldr pc, _prefetch_abort
  31. ldr pc, _data_abort
  32. ldr pc, _not_used
  33. ldr pc, _irq
  34. ldr pc, _fiq
  35. _undefined_instruction: .word undefined_instruction
  36. _software_interrupt: .word software_interrupt
  37. _prefetch_abort: .word prefetch_abort
  38. _data_abort: .word data_abort
  39. _not_used: .word not_used
  40. _irq: .word irq
  41. _fiq: .word fiq
  42. .balignl 16,0xdeadbeef
  43. /*
  44. *************************************************************************
  45. *
  46. * Startup Code (reset vector)
  47. *
  48. * do important init only if we don't start from memory!
  49. * setup Memory and board specific bits prior to relocation.
  50. * relocate armboot to ram
  51. * setup stack
  52. *
  53. *************************************************************************
  54. */
  55. .globl _TEXT_BASE
  56. _TEXT_BASE:
  57. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  58. .word CONFIG_SPL_TEXT_BASE
  59. #else
  60. .word CONFIG_SYS_TEXT_BASE
  61. #endif
  62. /*
  63. * These are defined in the board-specific linker script.
  64. * Subtracting _start from them lets the linker put their
  65. * relative position in the executable instead of leaving
  66. * them null.
  67. */
  68. .globl _bss_start_ofs
  69. _bss_start_ofs:
  70. .word __bss_start - _start
  71. .globl _bss_end_ofs
  72. _bss_end_ofs:
  73. .word __bss_end - _start
  74. .globl _end_ofs
  75. _end_ofs:
  76. .word _end - _start
  77. #ifdef CONFIG_USE_IRQ
  78. /* IRQ stack memory (calculated at run-time) */
  79. .globl IRQ_STACK_START
  80. IRQ_STACK_START:
  81. .word 0x0badc0de
  82. /* IRQ stack memory (calculated at run-time) */
  83. .globl FIQ_STACK_START
  84. FIQ_STACK_START:
  85. .word 0x0badc0de
  86. #endif
  87. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  88. .globl IRQ_STACK_START_IN
  89. IRQ_STACK_START_IN:
  90. .word 0x0badc0de
  91. /*
  92. * the actual reset code
  93. */
  94. reset:
  95. /*
  96. * set the cpu to SVC32 mode
  97. */
  98. mrs r0,cpsr
  99. bic r0,r0,#0x1f
  100. orr r0,r0,#0xd3
  101. msr cpsr,r0
  102. /*
  103. * Set up 925T mode
  104. */
  105. mov r1, #0x81 /* Set ARM925T configuration. */
  106. mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */
  107. /*
  108. * turn off the watchdog, unlock/diable sequence
  109. */
  110. mov r1, #0xF5
  111. ldr r0, =WDTIM_MODE
  112. strh r1, [r0]
  113. mov r1, #0xA0
  114. strh r1, [r0]
  115. /*
  116. * mask all IRQs by setting all bits in the INTMR - default
  117. */
  118. mov r1, #0xffffffff
  119. ldr r0, =REG_IHL1_MIR
  120. str r1, [r0]
  121. ldr r0, =REG_IHL2_MIR
  122. str r1, [r0]
  123. /*
  124. * wait for dpll to lock
  125. */
  126. ldr r0, =CK_DPLL1
  127. mov r1, #0x10
  128. strh r1, [r0]
  129. poll1:
  130. ldrh r1, [r0]
  131. ands r1, r1, #0x01
  132. beq poll1
  133. /*
  134. * we do sys-critical inits only at reboot,
  135. * not when booting from ram!
  136. */
  137. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  138. bl cpu_init_crit
  139. #endif
  140. bl _main
  141. /*------------------------------------------------------------------------------*/
  142. .globl c_runtime_cpu_setup
  143. c_runtime_cpu_setup:
  144. mov pc, lr
  145. /*
  146. *************************************************************************
  147. *
  148. * CPU_init_critical registers
  149. *
  150. * setup important registers
  151. * setup memory timing
  152. *
  153. *************************************************************************
  154. */
  155. cpu_init_crit:
  156. /*
  157. * flush v4 I/D caches
  158. */
  159. mov r0, #0
  160. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  161. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  162. /*
  163. * disable MMU stuff and caches
  164. */
  165. mrc p15, 0, r0, c1, c0, 0
  166. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  167. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  168. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  169. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  170. mcr p15, 0, r0, c1, c0, 0
  171. /*
  172. * Go setup Memory and board specific bits prior to relocation.
  173. */
  174. mov ip, lr /* perserve link reg across call */
  175. bl lowlevel_init /* go setup pll,mux,memory */
  176. mov lr, ip /* restore link */
  177. mov pc, lr /* back to my caller */
  178. /*
  179. *************************************************************************
  180. *
  181. * Interrupt handling
  182. *
  183. *************************************************************************
  184. */
  185. @
  186. @ IRQ stack frame.
  187. @
  188. #define S_FRAME_SIZE 72
  189. #define S_OLD_R0 68
  190. #define S_PSR 64
  191. #define S_PC 60
  192. #define S_LR 56
  193. #define S_SP 52
  194. #define S_IP 48
  195. #define S_FP 44
  196. #define S_R10 40
  197. #define S_R9 36
  198. #define S_R8 32
  199. #define S_R7 28
  200. #define S_R6 24
  201. #define S_R5 20
  202. #define S_R4 16
  203. #define S_R3 12
  204. #define S_R2 8
  205. #define S_R1 4
  206. #define S_R0 0
  207. #define MODE_SVC 0x13
  208. #define I_BIT 0x80
  209. /*
  210. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  211. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  212. */
  213. .macro bad_save_user_regs
  214. sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
  215. stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
  216. ldr r2, IRQ_STACK_START_IN
  217. ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
  218. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  219. add r5, sp, #S_SP
  220. mov r1, lr
  221. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  222. mov r0, sp @ save current stack into r0 (param register)
  223. .endm
  224. .macro irq_save_user_regs
  225. sub sp, sp, #S_FRAME_SIZE
  226. stmia sp, {r0 - r12} @ Calling r0-r12
  227. add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
  228. stmdb r8, {sp, lr}^ @ Calling SP, LR
  229. str lr, [r8, #0] @ Save calling PC
  230. mrs r6, spsr
  231. str r6, [r8, #4] @ Save CPSR
  232. str r0, [r8, #8] @ Save OLD_R0
  233. mov r0, sp
  234. .endm
  235. .macro irq_restore_user_regs
  236. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  237. mov r0, r0
  238. ldr lr, [sp, #S_PC] @ Get PC
  239. add sp, sp, #S_FRAME_SIZE
  240. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  241. .endm
  242. .macro get_bad_stack
  243. ldr r13, IRQ_STACK_START_IN
  244. str lr, [r13] @ save caller lr in position 0 of saved stack
  245. mrs lr, spsr @ get the spsr
  246. str lr, [r13, #4] @ save spsr in position 1 of saved stack
  247. mov r13, #MODE_SVC @ prepare SVC-Mode
  248. @ msr spsr_c, r13
  249. msr spsr, r13 @ switch modes, make sure moves will execute
  250. mov lr, pc @ capture return pc
  251. movs pc, lr @ jump to next instruction & switch modes.
  252. .endm
  253. .macro get_irq_stack @ setup IRQ stack
  254. ldr sp, IRQ_STACK_START
  255. .endm
  256. .macro get_fiq_stack @ setup FIQ stack
  257. ldr sp, FIQ_STACK_START
  258. .endm
  259. /*
  260. * exception handlers
  261. */
  262. .align 5
  263. undefined_instruction:
  264. get_bad_stack
  265. bad_save_user_regs
  266. bl do_undefined_instruction
  267. .align 5
  268. software_interrupt:
  269. get_bad_stack
  270. bad_save_user_regs
  271. bl do_software_interrupt
  272. .align 5
  273. prefetch_abort:
  274. get_bad_stack
  275. bad_save_user_regs
  276. bl do_prefetch_abort
  277. .align 5
  278. data_abort:
  279. get_bad_stack
  280. bad_save_user_regs
  281. bl do_data_abort
  282. .align 5
  283. not_used:
  284. get_bad_stack
  285. bad_save_user_regs
  286. bl do_not_used
  287. #ifdef CONFIG_USE_IRQ
  288. .align 5
  289. irq:
  290. get_irq_stack
  291. irq_save_user_regs
  292. bl do_irq
  293. irq_restore_user_regs
  294. .align 5
  295. fiq:
  296. get_fiq_stack
  297. /* someone ought to write a more effiction fiq_save_user_regs */
  298. irq_save_user_regs
  299. bl do_fiq
  300. irq_restore_user_regs
  301. #else
  302. .align 5
  303. irq:
  304. get_bad_stack
  305. bad_save_user_regs
  306. bl do_irq
  307. .align 5
  308. fiq:
  309. get_bad_stack
  310. bad_save_user_regs
  311. bl do_fiq
  312. #endif
  313. .align 5
  314. .globl reset_cpu
  315. reset_cpu:
  316. ldr r1, rstctl1 /* get clkm1 reset ctl */
  317. mov r3, #0x3 /* dsp_en + arm_rst = global reset */
  318. strh r3, [r1] /* force reset */
  319. mov r0, r0
  320. _loop_forever:
  321. b _loop_forever
  322. rstctl1:
  323. .word 0xfffece10