start.S 7.4 KB

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  1. /*
  2. * armboot - Startup Code for ARM920 CPU-core
  3. *
  4. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  5. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  6. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <asm-offsets.h>
  11. #include <common.h>
  12. #include <config.h>
  13. /*
  14. *************************************************************************
  15. *
  16. * Jump vector table as in table 3.1 in [1]
  17. *
  18. *************************************************************************
  19. */
  20. .globl _start
  21. _start: b start_code
  22. ldr pc, _undefined_instruction
  23. ldr pc, _software_interrupt
  24. ldr pc, _prefetch_abort
  25. ldr pc, _data_abort
  26. ldr pc, _not_used
  27. ldr pc, _irq
  28. ldr pc, _fiq
  29. _undefined_instruction: .word undefined_instruction
  30. _software_interrupt: .word software_interrupt
  31. _prefetch_abort: .word prefetch_abort
  32. _data_abort: .word data_abort
  33. _not_used: .word not_used
  34. _irq: .word irq
  35. _fiq: .word fiq
  36. .balignl 16,0xdeadbeef
  37. /*
  38. *************************************************************************
  39. *
  40. * Startup Code (called from the ARM reset exception vector)
  41. *
  42. * do important init only if we don't start from memory!
  43. * relocate armboot to ram
  44. * setup stack
  45. * jump to second stage
  46. *
  47. *************************************************************************
  48. */
  49. .globl _TEXT_BASE
  50. _TEXT_BASE:
  51. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  52. .word CONFIG_SPL_TEXT_BASE
  53. #else
  54. .word CONFIG_SYS_TEXT_BASE
  55. #endif
  56. /*
  57. * These are defined in the board-specific linker script.
  58. * Subtracting _start from them lets the linker put their
  59. * relative position in the executable instead of leaving
  60. * them null.
  61. */
  62. .globl _bss_start_ofs
  63. _bss_start_ofs:
  64. .word __bss_start - _start
  65. .globl _bss_end_ofs
  66. _bss_end_ofs:
  67. .word __bss_end - _start
  68. .globl _end_ofs
  69. _end_ofs:
  70. .word _end - _start
  71. #ifdef CONFIG_USE_IRQ
  72. /* IRQ stack memory (calculated at run-time) */
  73. .globl IRQ_STACK_START
  74. IRQ_STACK_START:
  75. .word 0x0badc0de
  76. /* IRQ stack memory (calculated at run-time) */
  77. .globl FIQ_STACK_START
  78. FIQ_STACK_START:
  79. .word 0x0badc0de
  80. #endif
  81. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  82. .globl IRQ_STACK_START_IN
  83. IRQ_STACK_START_IN:
  84. .word 0x0badc0de
  85. /*
  86. * the actual start code
  87. */
  88. start_code:
  89. /*
  90. * set the cpu to SVC32 mode
  91. */
  92. mrs r0, cpsr
  93. bic r0, r0, #0x1f
  94. orr r0, r0, #0xd3
  95. msr cpsr, r0
  96. #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  97. /*
  98. * relocate exception table
  99. */
  100. ldr r0, =_start
  101. ldr r1, =0x0
  102. mov r2, #16
  103. copyex:
  104. subs r2, r2, #1
  105. ldr r3, [r0], #4
  106. str r3, [r1], #4
  107. bne copyex
  108. #endif
  109. #ifdef CONFIG_S3C24X0
  110. /* turn off the watchdog */
  111. # if defined(CONFIG_S3C2400)
  112. # define pWTCON 0x15300000
  113. # define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
  114. # define CLKDIVN 0x14800014 /* clock divisor register */
  115. #else
  116. # define pWTCON 0x53000000
  117. # define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
  118. # define INTSUBMSK 0x4A00001C
  119. # define CLKDIVN 0x4C000014 /* clock divisor register */
  120. # endif
  121. ldr r0, =pWTCON
  122. mov r1, #0x0
  123. str r1, [r0]
  124. /*
  125. * mask all IRQs by setting all bits in the INTMR - default
  126. */
  127. mov r1, #0xffffffff
  128. ldr r0, =INTMSK
  129. str r1, [r0]
  130. # if defined(CONFIG_S3C2410)
  131. ldr r1, =0x3ff
  132. ldr r0, =INTSUBMSK
  133. str r1, [r0]
  134. # endif
  135. /* FCLK:HCLK:PCLK = 1:2:4 */
  136. /* default FCLK is 120 MHz ! */
  137. ldr r0, =CLKDIVN
  138. mov r1, #3
  139. str r1, [r0]
  140. #endif /* CONFIG_S3C24X0 */
  141. /*
  142. * we do sys-critical inits only at reboot,
  143. * not when booting from ram!
  144. */
  145. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  146. bl cpu_init_crit
  147. #endif
  148. bl _main
  149. /*------------------------------------------------------------------------------*/
  150. .globl c_runtime_cpu_setup
  151. c_runtime_cpu_setup:
  152. mov pc, lr
  153. /*
  154. *************************************************************************
  155. *
  156. * CPU_init_critical registers
  157. *
  158. * setup important registers
  159. * setup memory timing
  160. *
  161. *************************************************************************
  162. */
  163. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  164. cpu_init_crit:
  165. /*
  166. * flush v4 I/D caches
  167. */
  168. mov r0, #0
  169. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  170. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  171. /*
  172. * disable MMU stuff and caches
  173. */
  174. mrc p15, 0, r0, c1, c0, 0
  175. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  176. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  177. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  178. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  179. mcr p15, 0, r0, c1, c0, 0
  180. /*
  181. * before relocating, we have to setup RAM timing
  182. * because memory timing is board-dependend, you will
  183. * find a lowlevel_init.S in your board directory.
  184. */
  185. mov ip, lr
  186. bl lowlevel_init
  187. mov lr, ip
  188. mov pc, lr
  189. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  190. /*
  191. *************************************************************************
  192. *
  193. * Interrupt handling
  194. *
  195. *************************************************************************
  196. */
  197. @
  198. @ IRQ stack frame.
  199. @
  200. #define S_FRAME_SIZE 72
  201. #define S_OLD_R0 68
  202. #define S_PSR 64
  203. #define S_PC 60
  204. #define S_LR 56
  205. #define S_SP 52
  206. #define S_IP 48
  207. #define S_FP 44
  208. #define S_R10 40
  209. #define S_R9 36
  210. #define S_R8 32
  211. #define S_R7 28
  212. #define S_R6 24
  213. #define S_R5 20
  214. #define S_R4 16
  215. #define S_R3 12
  216. #define S_R2 8
  217. #define S_R1 4
  218. #define S_R0 0
  219. #define MODE_SVC 0x13
  220. #define I_BIT 0x80
  221. /*
  222. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  223. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  224. */
  225. .macro bad_save_user_regs
  226. sub sp, sp, #S_FRAME_SIZE
  227. stmia sp, {r0 - r12} @ Calling r0-r12
  228. ldr r2, IRQ_STACK_START_IN
  229. ldmia r2, {r2 - r3} @ get pc, cpsr
  230. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  231. add r5, sp, #S_SP
  232. mov r1, lr
  233. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  234. mov r0, sp
  235. .endm
  236. .macro irq_save_user_regs
  237. sub sp, sp, #S_FRAME_SIZE
  238. stmia sp, {r0 - r12} @ Calling r0-r12
  239. add r7, sp, #S_PC
  240. stmdb r7, {sp, lr}^ @ Calling SP, LR
  241. str lr, [r7, #0] @ Save calling PC
  242. mrs r6, spsr
  243. str r6, [r7, #4] @ Save CPSR
  244. str r0, [r7, #8] @ Save OLD_R0
  245. mov r0, sp
  246. .endm
  247. .macro irq_restore_user_regs
  248. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  249. mov r0, r0
  250. ldr lr, [sp, #S_PC] @ Get PC
  251. add sp, sp, #S_FRAME_SIZE
  252. /* return & move spsr_svc into cpsr */
  253. subs pc, lr, #4
  254. .endm
  255. .macro get_bad_stack
  256. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  257. str lr, [r13] @ save caller lr / spsr
  258. mrs lr, spsr
  259. str lr, [r13, #4]
  260. mov r13, #MODE_SVC @ prepare SVC-Mode
  261. @ msr spsr_c, r13
  262. msr spsr, r13
  263. mov lr, pc
  264. movs pc, lr
  265. .endm
  266. .macro get_irq_stack @ setup IRQ stack
  267. ldr sp, IRQ_STACK_START
  268. .endm
  269. .macro get_fiq_stack @ setup FIQ stack
  270. ldr sp, FIQ_STACK_START
  271. .endm
  272. /*
  273. * exception handlers
  274. */
  275. .align 5
  276. undefined_instruction:
  277. get_bad_stack
  278. bad_save_user_regs
  279. bl do_undefined_instruction
  280. .align 5
  281. software_interrupt:
  282. get_bad_stack
  283. bad_save_user_regs
  284. bl do_software_interrupt
  285. .align 5
  286. prefetch_abort:
  287. get_bad_stack
  288. bad_save_user_regs
  289. bl do_prefetch_abort
  290. .align 5
  291. data_abort:
  292. get_bad_stack
  293. bad_save_user_regs
  294. bl do_data_abort
  295. .align 5
  296. not_used:
  297. get_bad_stack
  298. bad_save_user_regs
  299. bl do_not_used
  300. #ifdef CONFIG_USE_IRQ
  301. .align 5
  302. irq:
  303. get_irq_stack
  304. irq_save_user_regs
  305. bl do_irq
  306. irq_restore_user_regs
  307. .align 5
  308. fiq:
  309. get_fiq_stack
  310. /* someone ought to write a more effiction fiq_save_user_regs */
  311. irq_save_user_regs
  312. bl do_fiq
  313. irq_restore_user_regs
  314. #else
  315. .align 5
  316. irq:
  317. get_bad_stack
  318. bad_save_user_regs
  319. bl do_irq
  320. .align 5
  321. fiq:
  322. get_bad_stack
  323. bad_save_user_regs
  324. bl do_fiq
  325. #endif