speed.c 2.3 KB

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  1. /*
  2. * (C) Copyright 2001-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2002
  6. * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /* This code should work for both the S3C2400 and the S3C2410
  11. * as they seem to have the same PLL and clock machinery inside.
  12. * The different address mapping is handled by the s3c24xx.h files below.
  13. */
  14. #include <common.h>
  15. #ifdef CONFIG_S3C24X0
  16. #include <asm/io.h>
  17. #include <asm/arch/s3c24x0_cpu.h>
  18. #define MPLL 0
  19. #define UPLL 1
  20. /* ------------------------------------------------------------------------- */
  21. /* NOTE: This describes the proper use of this file.
  22. *
  23. * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  24. *
  25. * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  26. * the specified bus in HZ.
  27. */
  28. /* ------------------------------------------------------------------------- */
  29. static ulong get_PLLCLK(int pllreg)
  30. {
  31. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  32. ulong r, m, p, s;
  33. if (pllreg == MPLL)
  34. r = readl(&clk_power->mpllcon);
  35. else if (pllreg == UPLL)
  36. r = readl(&clk_power->upllcon);
  37. else
  38. hang();
  39. m = ((r & 0xFF000) >> 12) + 8;
  40. p = ((r & 0x003F0) >> 4) + 2;
  41. s = r & 0x3;
  42. #if defined(CONFIG_S3C2440)
  43. if (pllreg == MPLL)
  44. return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
  45. #endif
  46. return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
  47. }
  48. /* return FCLK frequency */
  49. ulong get_FCLK(void)
  50. {
  51. return get_PLLCLK(MPLL);
  52. }
  53. /* return HCLK frequency */
  54. ulong get_HCLK(void)
  55. {
  56. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  57. #ifdef CONFIG_S3C2440
  58. switch (readl(&clk_power->clkdivn) & 0x6) {
  59. default:
  60. case 0:
  61. return get_FCLK();
  62. case 2:
  63. return get_FCLK() / 2;
  64. case 4:
  65. return (readl(&clk_power->camdivn) & (1 << 9)) ?
  66. get_FCLK() / 8 : get_FCLK() / 4;
  67. case 6:
  68. return (readl(&clk_power->camdivn) & (1 << 8)) ?
  69. get_FCLK() / 6 : get_FCLK() / 3;
  70. }
  71. #else
  72. return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
  73. #endif
  74. }
  75. /* return PCLK frequency */
  76. ulong get_PCLK(void)
  77. {
  78. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  79. return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
  80. }
  81. /* return UCLK frequency */
  82. ulong get_UCLK(void)
  83. {
  84. return get_PLLCLK(UPLL);
  85. }
  86. #endif /* CONFIG_S3C24X0 */