lowlevel_init.S 5.1 KB

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  1. /*
  2. * lowlevel_init.S - basic hardware initialization for the KS8695 CPU
  3. *
  4. * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <config.h>
  9. #include <version.h>
  10. #include <asm/arch/platform.h>
  11. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  12. /*
  13. *************************************************************************
  14. *
  15. * Handy dandy macros
  16. *
  17. *************************************************************************
  18. */
  19. /* Delay a bit */
  20. .macro DELAY_FOR cycles, reg0
  21. ldr \reg0, =\cycles
  22. subs \reg0, \reg0, #1
  23. subne pc, pc, #0xc
  24. .endm
  25. /*
  26. *************************************************************************
  27. *
  28. * Some local storage.
  29. *
  30. *************************************************************************
  31. */
  32. /* Should we boot with an interactive console or not */
  33. .globl serial_console
  34. /*
  35. *************************************************************************
  36. *
  37. * Raw hardware initialization code. The important thing is to get
  38. * SDRAM setup and running. We do some other basic things here too,
  39. * like getting the PLL set for high speed, and init the LEDs.
  40. *
  41. *************************************************************************
  42. */
  43. .globl lowlevel_init
  44. lowlevel_init:
  45. #if DEBUG
  46. /*
  47. * enable UART for early debug trace
  48. */
  49. ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
  50. mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
  51. str r2, [r1]
  52. ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
  53. mov r2, #KS8695_UART_LINEC_WLEN8
  54. str r2, [r1] /* 8 data bits, no parity, 1 stop */
  55. ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
  56. mov r2, #0x41
  57. str r2, [r1] /* write 'A' */
  58. #endif
  59. #if DEBUG
  60. ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
  61. mov r2, #0x42
  62. str r2, [r1]
  63. #endif
  64. /*
  65. * remap the memory and flash regions. we want to end up with
  66. * ram from address 0, and flash at 32MB.
  67. */
  68. ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
  69. ldr r2, =0xbfc00040
  70. str r2, [r1] /* large flash map */
  71. ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
  72. highflash:
  73. ldr r2, =0x8fe00040
  74. str r2, [r1] /* remap flash range */
  75. /*
  76. * remap the second select region to the 4MB immediately after
  77. * the first region. This way if you have a larger flash (say 8Mb)
  78. * then you can have it all mapped nicely. Has no effect if you
  79. * only have a 4Mb or smaller flash.
  80. */
  81. ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
  82. ldr r2, =0x9fe40040
  83. str r2, [r1] /* remap flash2 region, contiguous */
  84. ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
  85. ldr r2, =0x30000005
  86. str r2, [r1] /* enable both flash selects */
  87. #ifdef CONFIG_CM41xx
  88. /*
  89. * map the second flash chip, using the external IO lines.
  90. */
  91. ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
  92. ldr r2, =0xafe80b6d
  93. str r2, [r1] /* remap io0 region, contiguous */
  94. ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
  95. ldr r2, =0xbfec0b6d
  96. str r2, [r1] /* remap io1 region, contiguous */
  97. ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
  98. ldr r2, =0x30050005
  99. str r2, [r1] /* enable second flash */
  100. #endif
  101. /*
  102. * before relocating, we have to setup RAM timing
  103. */
  104. ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
  105. #if (PHYS_SDRAM_1_SIZE == 0x02000000)
  106. ldr r2, =0x7fc0000e /* 32MB */
  107. #else
  108. ldr r2, =0x3fc0000e /* 16MB */
  109. #endif
  110. str r2, [r1] /* configure sdram bank0 setup */
  111. ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
  112. mov r2, #0
  113. str r2, [r1] /* configure sdram bank1 setup */
  114. ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
  115. ldr r2, =0x0000000a
  116. str r2, [r1] /* set RAS/CAS timing */
  117. ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
  118. ldr r2, =0x00030000
  119. str r2, [r1] /* send NOP command */
  120. DELAY_FOR 0x100, r0
  121. ldr r2, =0x00010000
  122. str r2, [r1] /* send PRECHARGE-ALL */
  123. DELAY_FOR 0x100, r0
  124. ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
  125. ldr r2, =0x00000020
  126. str r2, [r1] /* set for fast refresh */
  127. DELAY_FOR 0x100, r0
  128. ldr r2, =0x00000190
  129. str r2, [r1] /* set normal refresh timing */
  130. ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
  131. ldr r2, =0x00020033
  132. str r2, [r1] /* send mode command */
  133. DELAY_FOR 0x100, r0
  134. ldr r2, =0x01f00000
  135. str r2, [r1] /* enable sdram fifos */
  136. /*
  137. * set pll to top speed
  138. */
  139. ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
  140. mov r2, #0
  141. str r2, [r1] /* set pll clock to 166MHz */
  142. ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
  143. ldr r2, [r1] /* Get switch ctrl0 register */
  144. and r2, r2, #0x0fc00000 /* Mask out LED control bits */
  145. orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
  146. str r2, [r1]
  147. #ifdef CONFIG_CM4008
  148. ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
  149. ldr r2, =0x0000fe30
  150. str r2, [r1] /* enable LED's as outputs */
  151. ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
  152. ldr r2, =0x0000fe20
  153. str r2, [r1] /* turn on power LED */
  154. #endif
  155. #if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
  156. ldr r2, [r1] /* get current GPIO input data */
  157. tst r2, #0x8 /* check if "erase" depressed */
  158. beq nobutton
  159. mov r2, #0 /* be quiet on boot, no console */
  160. ldr r1, =serial_console
  161. str r2, [r1]
  162. nobutton:
  163. #endif
  164. add lr, lr, #0x02000000 /* flash is now mapped high */
  165. add ip, ip, #0x02000000 /* this is a hack */
  166. mov pc, lr /* all done, return */
  167. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */