speed.c 2.4 KB

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  1. /*
  2. * Cirrus Logic EP93xx PLL support.
  3. *
  4. * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <asm/arch/ep93xx.h>
  10. #include <asm/io.h>
  11. #include <div64.h>
  12. /*
  13. * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  14. *
  15. * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  16. * the specified bus in HZ.
  17. */
  18. /*
  19. * return the PLL output frequency
  20. *
  21. * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
  22. * / (X2IPD + 1) / 2^PS
  23. */
  24. static ulong get_PLLCLK(uint32_t *pllreg)
  25. {
  26. uint8_t i;
  27. const uint32_t clkset = readl(pllreg);
  28. uint64_t rate = CONFIG_SYS_CLK_FREQ;
  29. rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
  30. rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
  31. do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
  32. for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
  33. rate >>= 1;
  34. return (ulong)rate;
  35. }
  36. /* return FCLK frequency */
  37. ulong get_FCLK()
  38. {
  39. const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
  40. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  41. const uint32_t clkset1 = readl(&syscon->clkset1);
  42. const uint8_t fclk_div =
  43. fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
  44. const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
  45. return fclk_rate;
  46. }
  47. /* return HCLK frequency */
  48. ulong get_HCLK(void)
  49. {
  50. const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
  51. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  52. const uint32_t clkset1 = readl(&syscon->clkset1);
  53. const uint8_t hclk_div =
  54. hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
  55. const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
  56. return hclk_rate;
  57. }
  58. /* return PCLK frequency */
  59. ulong get_PCLK(void)
  60. {
  61. const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
  62. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  63. const uint32_t clkset1 = readl(&syscon->clkset1);
  64. const uint8_t pclk_div =
  65. pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
  66. const ulong pclk_rate = get_HCLK() / pclk_div;
  67. return pclk_rate;
  68. }
  69. /* return UCLK frequency */
  70. ulong get_UCLK(void)
  71. {
  72. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  73. ulong uclk_rate;
  74. const uint32_t value = readl(&syscon->pwrcnt);
  75. if (value & SYSCON_PWRCNT_UART_BAUD)
  76. uclk_rate = CONFIG_SYS_CLK_FREQ;
  77. else
  78. uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
  79. return uclk_rate;
  80. }