timer.c 2.6 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Lineo, Inc. <www.lineo.com>
  4. * Bernhard Kuhn <bkuhn@lineo.com>
  5. *
  6. * (C) Copyright 2002
  7. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8. * Marius Groeger <mgroeger@sysgo.de>
  9. *
  10. * (C) Copyright 2002
  11. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12. * Alex Zuepke <azu@sysgo.de>
  13. *
  14. * SPDX-License-Identifier: GPL-2.0+
  15. */
  16. #include <common.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/at91_tc.h>
  20. #include <asm/arch/at91_pmc.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /* the number of clocks per CONFIG_SYS_HZ */
  23. #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
  24. int timer_init(void)
  25. {
  26. at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
  27. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  28. /* enables TC1.0 clock */
  29. writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */
  30. writel(0, &tc->bcr);
  31. writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
  32. AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
  33. writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
  34. /* set to MCLK/2 and restart the timer
  35. when the value in TC_RC is reached */
  36. writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
  37. writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
  38. writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
  39. writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
  40. gd->arch.lastinc = 0;
  41. gd->arch.tbl = 0;
  42. return 0;
  43. }
  44. /*
  45. * timer without interrupts
  46. */
  47. ulong get_timer(ulong base)
  48. {
  49. return get_timer_masked() - base;
  50. }
  51. void __udelay(unsigned long usec)
  52. {
  53. udelay_masked(usec);
  54. }
  55. ulong get_timer_raw(void)
  56. {
  57. at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
  58. u32 now;
  59. now = readl(&tc->tc[0].cv) & 0x0000ffff;
  60. if (now >= gd->arch.lastinc) {
  61. /* normal mode */
  62. gd->arch.tbl += now - gd->arch.lastinc;
  63. } else {
  64. /* we have an overflow ... */
  65. gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
  66. }
  67. gd->arch.lastinc = now;
  68. return gd->arch.tbl;
  69. }
  70. ulong get_timer_masked(void)
  71. {
  72. return get_timer_raw()/TIMER_LOAD_VAL;
  73. }
  74. void udelay_masked(unsigned long usec)
  75. {
  76. u32 tmo;
  77. u32 endtime;
  78. signed long diff;
  79. tmo = CONFIG_SYS_HZ_CLOCK / 1000;
  80. tmo *= usec;
  81. tmo /= 1000;
  82. endtime = get_timer_raw() + tmo;
  83. do {
  84. u32 now = get_timer_raw();
  85. diff = endtime - now;
  86. } while (diff >= 0);
  87. }
  88. /*
  89. * This function is derived from PowerPC code (read timebase as long long).
  90. * On ARM it just returns the timer value.
  91. */
  92. unsigned long long get_ticks(void)
  93. {
  94. return get_timer(0);
  95. }
  96. /*
  97. * This function is derived from PowerPC code (timebase clock frequency).
  98. * On ARM it returns the number of timer ticks per second.
  99. */
  100. ulong get_tbclk(void)
  101. {
  102. return CONFIG_SYS_HZ;
  103. }