lowlevel_init.S 3.5 KB

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  1. /*
  2. * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  3. * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  4. *
  5. * Modified for the at91rm9200dk board by
  6. * (C) Copyright 2004
  7. * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <config.h>
  12. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/at91_mc.h>
  15. #include <asm/arch/at91_pmc.h>
  16. #include <asm/arch/at91_pio.h>
  17. #define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
  18. _MTEXT_BASE:
  19. #undef START_FROM_MEM
  20. #ifdef START_FROM_MEM
  21. .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
  22. #else
  23. .word CONFIG_SYS_TEXT_BASE
  24. #endif
  25. .globl lowlevel_init
  26. lowlevel_init:
  27. ldr r1, =AT91_ASM_PMC_MOR
  28. /* Main oscillator Enable register */
  29. #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
  30. ldr r0, =0x0000FF01 /* Enable main oscillator */
  31. #else
  32. ldr r0, =0x0000FF00 /* Disable main oscillator */
  33. #endif
  34. str r0, [r1] /*AT91C_CKGR_MOR] */
  35. /* Add loop to compensate Main Oscillator startup time */
  36. ldr r0, =0x00000010
  37. LoopOsc:
  38. subs r0, r0, #1
  39. bhi LoopOsc
  40. /* memory control configuration */
  41. /* this isn't very elegant, but what the heck */
  42. ldr r0, =SMRDATA
  43. ldr r1, _MTEXT_BASE
  44. sub r0, r0, r1
  45. ldr r2, =SMRDATAE
  46. sub r2, r2, r1
  47. pllloop:
  48. /* the address */
  49. ldr r1, [r0], #4
  50. /* the value */
  51. ldr r3, [r0], #4
  52. str r3, [r1]
  53. cmp r2, r0
  54. bne pllloop
  55. /* delay - this is all done by guess */
  56. ldr r0, =0x00010000
  57. /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
  58. lock:
  59. subs r0, r0, #1
  60. bhi lock
  61. ldr r0, =SMRDATA1
  62. ldr r1, _MTEXT_BASE
  63. sub r0, r0, r1
  64. ldr r2, =SMRDATA1E
  65. sub r2, r2, r1
  66. sdinit:
  67. /* the address */
  68. ldr r1, [r0], #4
  69. /* the value */
  70. ldr r3, [r0], #4
  71. str r3, [r1]
  72. cmp r2, r0
  73. bne sdinit
  74. /* switch from FastBus to Asynchronous clock mode */
  75. mrc p15, 0, r0, c1, c0, 0
  76. orr r0, r0, #ARM920T_CONTROL
  77. mcr p15, 0, r0, c1, c0, 0
  78. /* everything is fine now */
  79. mov pc, lr
  80. .ltorg
  81. SMRDATA:
  82. .word AT91_ASM_MC_EBI_CFG
  83. .word CONFIG_SYS_EBI_CFGR_VAL
  84. .word AT91_ASM_MC_SMC_CSR0
  85. .word CONFIG_SYS_SMC_CSR0_VAL
  86. .word AT91_ASM_PMC_PLLAR
  87. .word CONFIG_SYS_PLLAR_VAL
  88. .word AT91_ASM_PMC_PLLBR
  89. .word CONFIG_SYS_PLLBR_VAL
  90. .word AT91_ASM_PMC_MCKR
  91. .word CONFIG_SYS_MCKR_VAL
  92. SMRDATAE:
  93. /* here there's a delay */
  94. SMRDATA1:
  95. .word AT91_ASM_PIOC_ASR
  96. .word CONFIG_SYS_PIOC_ASR_VAL
  97. .word AT91_ASM_PIOC_BSR
  98. .word CONFIG_SYS_PIOC_BSR_VAL
  99. .word AT91_ASM_PIOC_PDR
  100. .word CONFIG_SYS_PIOC_PDR_VAL
  101. .word AT91_ASM_MC_EBI_CSA
  102. .word CONFIG_SYS_EBI_CSA_VAL
  103. .word AT91_ASM_MC_SDRAMC_CR
  104. .word CONFIG_SYS_SDRC_CR_VAL
  105. .word AT91_ASM_MC_SDRAMC_MR
  106. .word CONFIG_SYS_SDRC_MR_VAL
  107. .word CONFIG_SYS_SDRAM
  108. .word CONFIG_SYS_SDRAM_VAL
  109. .word AT91_ASM_MC_SDRAMC_MR
  110. .word CONFIG_SYS_SDRC_MR_VAL1
  111. .word CONFIG_SYS_SDRAM
  112. .word CONFIG_SYS_SDRAM_VAL
  113. .word CONFIG_SYS_SDRAM
  114. .word CONFIG_SYS_SDRAM_VAL
  115. .word CONFIG_SYS_SDRAM
  116. .word CONFIG_SYS_SDRAM_VAL
  117. .word CONFIG_SYS_SDRAM
  118. .word CONFIG_SYS_SDRAM_VAL
  119. .word CONFIG_SYS_SDRAM
  120. .word CONFIG_SYS_SDRAM_VAL
  121. .word CONFIG_SYS_SDRAM
  122. .word CONFIG_SYS_SDRAM_VAL
  123. .word CONFIG_SYS_SDRAM
  124. .word CONFIG_SYS_SDRAM_VAL
  125. .word CONFIG_SYS_SDRAM
  126. .word CONFIG_SYS_SDRAM_VAL
  127. .word AT91_ASM_MC_SDRAMC_MR
  128. .word CONFIG_SYS_SDRC_MR_VAL2
  129. .word CONFIG_SYS_SDRAM1
  130. .word CONFIG_SYS_SDRAM_VAL
  131. .word AT91_ASM_MC_SDRAMC_TR
  132. .word CONFIG_SYS_SDRC_TR_VAL
  133. .word CONFIG_SYS_SDRAM
  134. .word CONFIG_SYS_SDRAM_VAL
  135. .word AT91_ASM_MC_SDRAMC_MR
  136. .word CONFIG_SYS_SDRC_MR_VAL3
  137. .word CONFIG_SYS_SDRAM
  138. .word CONFIG_SYS_SDRAM_VAL
  139. SMRDATA1E:
  140. /* SMRDATA1 is 176 bytes long */
  141. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */