clock.c 3.7 KB

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  1. /*
  2. * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
  3. *
  4. * Copyright (C) 2011 Andreas Bießmann
  5. * Copyright (C) 2005 David Brownell
  6. * Copyright (C) 2005 Ivan Kokshaysky
  7. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/at91_pmc.h>
  15. #include <asm/arch/clk.h>
  16. #if !defined(CONFIG_AT91FAMILY)
  17. # error You need to define CONFIG_AT91FAMILY in your board config!
  18. #endif
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static unsigned long at91_css_to_rate(unsigned long css)
  21. {
  22. switch (css) {
  23. case AT91_PMC_MCKR_CSS_SLOW:
  24. return CONFIG_SYS_AT91_SLOW_CLOCK;
  25. case AT91_PMC_MCKR_CSS_MAIN:
  26. return gd->arch.main_clk_rate_hz;
  27. case AT91_PMC_MCKR_CSS_PLLA:
  28. return gd->arch.plla_rate_hz;
  29. case AT91_PMC_MCKR_CSS_PLLB:
  30. return gd->arch.pllb_rate_hz;
  31. }
  32. return 0;
  33. }
  34. #ifdef CONFIG_USB_ATMEL
  35. static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
  36. {
  37. unsigned i, div = 0, mul = 0, diff = 1 << 30;
  38. unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
  39. /* PLL output max 240 MHz (or 180 MHz per errata) */
  40. if (out_freq > 240000000)
  41. goto fail;
  42. for (i = 1; i < 256; i++) {
  43. int diff1;
  44. unsigned input, mul1;
  45. /*
  46. * PLL input between 1MHz and 32MHz per spec, but lower
  47. * frequences seem necessary in some cases so allow 100K.
  48. * Warning: some newer products need 2MHz min.
  49. */
  50. input = main_freq / i;
  51. if (input < 100000)
  52. continue;
  53. if (input > 32000000)
  54. continue;
  55. mul1 = out_freq / input;
  56. if (mul1 > 2048)
  57. continue;
  58. if (mul1 < 2)
  59. goto fail;
  60. diff1 = out_freq - input * mul1;
  61. if (diff1 < 0)
  62. diff1 = -diff1;
  63. if (diff > diff1) {
  64. diff = diff1;
  65. div = i;
  66. mul = mul1;
  67. if (diff == 0)
  68. break;
  69. }
  70. }
  71. if (i == 256 && diff > (out_freq >> 5))
  72. goto fail;
  73. return ret | ((mul - 1) << 16) | div;
  74. fail:
  75. return 0;
  76. }
  77. #endif
  78. static u32 at91_pll_rate(u32 freq, u32 reg)
  79. {
  80. unsigned mul, div;
  81. div = reg & 0xff;
  82. mul = (reg >> 16) & 0x7ff;
  83. if (div && mul) {
  84. freq /= div;
  85. freq *= mul + 1;
  86. } else
  87. freq = 0;
  88. return freq;
  89. }
  90. int at91_clock_init(unsigned long main_clock)
  91. {
  92. unsigned freq, mckr;
  93. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  94. #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
  95. unsigned tmp;
  96. /*
  97. * When the bootloader initialized the main oscillator correctly,
  98. * there's no problem using the cycle counter. But if it didn't,
  99. * or when using oscillator bypass mode, we must be told the speed
  100. * of the main clock.
  101. */
  102. if (!main_clock) {
  103. do {
  104. tmp = readl(&pmc->mcfr);
  105. } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
  106. tmp &= AT91_PMC_MCFR_MAINF_MASK;
  107. main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
  108. }
  109. #endif
  110. gd->arch.main_clk_rate_hz = main_clock;
  111. /* report if PLLA is more than mildly overclocked */
  112. gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
  113. #ifdef CONFIG_USB_ATMEL
  114. /*
  115. * USB clock init: choose 48 MHz PLLB value,
  116. * disable 48MHz clock during usb peripheral suspend.
  117. *
  118. * REVISIT: assumes MCK doesn't derive from PLLB!
  119. */
  120. gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
  121. AT91_PMC_PLLBR_USBDIV_2;
  122. gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
  123. gd->arch.at91_pllb_usb_init);
  124. #endif
  125. /*
  126. * MCK and CPU derive from one of those primary clocks.
  127. * For now, assume this parentage won't change.
  128. */
  129. mckr = readl(&pmc->mckr);
  130. gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
  131. freq = gd->arch.mck_rate_hz;
  132. freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
  133. /* mdiv */
  134. gd->arch.mck_rate_hz = freq /
  135. (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
  136. gd->arch.cpu_clk_rate_hz = freq;
  137. return 0;
  138. }