cpu.h 1.9 KB

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  1. /*
  2. * (C) Copyright 2010-2011
  3. * NVIDIA Corporation <www.nvidia.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <asm/types.h>
  8. /* Stabilization delays, in usec */
  9. #define PLL_STABILIZATION_DELAY (300)
  10. #define IO_STABILIZATION_DELAY (1000)
  11. #if defined(CONFIG_TEGRA20)
  12. #define NVBL_PLLP_KHZ (216000)
  13. #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
  14. #define NVBL_PLLP_KHZ (408000)
  15. #else
  16. #error "Unknown Tegra chip!"
  17. #endif
  18. #define PLLX_ENABLED (1 << 30)
  19. #define CCLK_BURST_POLICY 0x20008888
  20. #define SUPER_CCLK_DIVIDER 0x80000000
  21. /* Calculate clock fractional divider value from ref and target frequencies */
  22. #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
  23. /* Calculate clock frequency value from reference and clock divider value */
  24. #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
  25. /* AVP/CPU ID */
  26. #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
  27. #define PG_UP_TAG_0 0x0
  28. #define CORESIGHT_UNLOCK 0xC5ACCE55;
  29. #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
  30. #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
  31. #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
  32. #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
  33. #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
  34. #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
  35. #define FLOW_MODE_STOP 2
  36. #define HALT_COP_EVENT_JTAG (1 << 28)
  37. #define HALT_COP_EVENT_IRQ_1 (1 << 11)
  38. #define HALT_COP_EVENT_FIQ_1 (1 << 9)
  39. #define FLOW_MODE_NONE 0
  40. #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
  41. struct clk_pll_table {
  42. u16 n;
  43. u16 m;
  44. u8 p;
  45. u8 cpcon;
  46. };
  47. void clock_enable_coresight(int enable);
  48. void enable_cpu_clock(int enable);
  49. void halt_avp(void) __attribute__ ((noreturn));
  50. void init_pllx(void);
  51. void powerup_cpu(void);
  52. void reset_A9_cpu(int reset);
  53. void start_cpu(u32 reset_vector);
  54. int tegra_get_chip(void);
  55. int tegra_get_sku_info(void);
  56. int tegra_get_chip_sku(void);
  57. void adjust_pllp_out_freqs(void);